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rtime.felk.cvut.cz Git - fpga/virtex2/blink.git/log
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Vladimir Burian [Sat, 8 Jan 2011 23:46:02 +0000 (00:46 +0100)]
+ Top level design
Design can be now implemented and downloaded to the target.
Vladimir Burian [Sat, 8 Jan 2011 23:43:57 +0000 (00:43 +0100)]
+ Softcore software.
Vladimir Burian [Sat, 8 Jan 2011 23:34:49 +0000 (00:34 +0100)]
+Softcore configuration and memories desctiption.
Added modified opneMSP430 configuration file. Softcore configured as 4kB ROM, 1kB RAM, HW multiplier and no debug interface.
Added .bmm file descibing future instances of memories connected to MCU.
Vladimir Burian [Sat, 8 Jan 2011 23:15:28 +0000 (00:15 +0100)]
+Coregen with memories used by softcore
Vladimir Burian [Sat, 8 Jan 2011 23:12:17 +0000 (00:12 +0100)]
+ OpenMSP430 submodule.
projects / fpga / virtex2 / blink.git / log