+Coregen with memories used by softcore

[fpga/virtex2/blink.git] / coregen / coregen.cgp

diff --git a/coregen/coregen.cgp b/coregen/coregen.cgp
new file mode 100644 (file)
index 0000000..010dcf3
--- /dev/null
+++ b/coregen/coregen.cgp
@@ -0,0 +1,20 @@
+# Date: Sat Jan  8 21:37:24 2011
+SET addpads = False
+SET asysymbol = True
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = False
+SET designentry = VHDL
+SET device = xc2v1000
+SET devicefamily = virtex2
+SET flowvendor = Foundation_iSE
+SET formalverification = False
+SET foundationsym = False
+SET implementationfiletype = Ngc
+SET package = fg456
+SET removerpms = False
+SET simulationfiles = Behavioral
+SET speedgrade = -6
+SET verilogsim = False
+SET vhdlsim = True
+SET workingdirectory = /home/vladimir/xilinx/leds_v/coregen/tmp/
+