Resets changed from asynchronous to synchronous.

[fpga/uart.git] / tx.vhd

diff --git a/tx.vhd b/tx.vhd
index 278d6b811761f543c6e3b1247e7ae1ec6a2f2185..9d777c78219d28a5414ab14841c130d8a9c08413 100644 (file)
--- a/tx.vhd
+++ b/tx.vhd
@@ -45,25 +45,27 @@ begin
 
   process (clk, reset)
   begin
-    if (reset = '1') then
-      tx_shift_reg <= "1111111111";
-      tx_flag <= "0000000000";
-      tx_ready <= '1';
+    if (rising_edge(clk)) then
+      if (reset = '1') then
+        tx_shift_reg <= "1111111111";
+        tx_flag <= "0000000000";
+        tx_ready <= '1';
       
-    elsif (rising_edge(clk)) then
-      if (we = '1') then
-        tx_shift_reg <= '1' & data & '0';
-        tx_flag <= "1000000000";
-        tx_ready <= '0';
-        
-      else
-        tx_shift_reg <= '1' & tx_shift_reg(9 downto 1);
-        tx_flag <= '0' & tx_flag(9 downto 1);
-        
-        if (tx_flag(1) = '1') then
-          tx_ready <= '1';
+      else  
+        if (we = '1') then
+          tx_shift_reg <= '1' & data & '0';
+          tx_flag <= "1000000000";
+          tx_ready <= '0';
+          
+        else
+          tx_shift_reg <= '1' & tx_shift_reg(9 downto 1);
+          tx_flag <= '0' & tx_flag(9 downto 1);
+          
+          if (tx_flag(1) = '1') then
+            tx_ready <= '1';
+          end if;
+          
         end if;
-        
       end if;
     end if;
   end process;