Resets changed from asynchronous to synchronous.

[fpga/uart.git] / fifo.vhd

diff --git a/fifo.vhd b/fifo.vhd
index f59a43826c466a01176fe8b0d6be39d0c3158d27..84370e5d5fb6af33d6d7ba807d4c8d733c102d42 100644 (file)
--- a/fifo.vhd
+++ b/fifo.vhd
@@ -61,23 +61,25 @@ begin
   --   the number of occupied memory positions.
   process (clk, reset)
   begin
-    if (reset = '1') then
-      length <= (others => '0');
-      overflow <= '0';
-      
-    elsif (rising_edge(clk)) then
-      if ((re = '1') and (we = '0')) then
-        length <= length - 1;
-      elsif ((re = '0') and (we = '1')) then
-        if (full_s = '1') then
-          overflow <= '1';
-        else
-          length <= length + 1;
-        end if;
-      end if;
-      
-      if (clear_ow = '1') then
+    if (rising_edge(clk)) then
+      if (reset = '1') then
+        length <= (others => '0');
         overflow <= '0';
+
+      else
+        if ((re = '1') and (we = '0')) then
+          length <= length - 1;
+        elsif ((re = '0') and (we = '1')) then
+          if (full_s = '1') then
+            overflow <= '1';
+          else
+            length <= length + 1;
+          end if;
+        end if;
+        
+        if (clear_ow = '1') then
+          overflow <= '0';
+        end if;
       end if;
     end if;
   end process;