Receiving capability added to the top component.

[fpga/uart.git] / tx.vhd

diff --git a/tx.vhd b/tx.vhd
index aca961aedef674f265b2abf6db7da1d952ac8758..ccf9a86e3f6468204607b510df53a7ffbb6cb287 100644 (file)
--- a/tx.vhd
+++ b/tx.vhd
@@ -3,6 +3,19 @@ use ieee.std_logic_1164.all;
 use ieee.std_logic_arith.all;
 use ieee.std_logic_unsigned.all;
 
+--------------------------------------------------------------------------------
+-- Output shift register
+--
+-- This entity can be used for generating of RS232 like output. Configuration is
+-- hard wired as 8N1 (8 bits of data, no parity, 1 stop bit).
+--
+-- All operations (except for 'reset') are synchronous to 'clk' rising edges.
+-- This clock signal also determines baud rate.
+--
+-- When 'ready' signal is high, next data vector can be written in by setting
+-- 'we' signal.
+--------------------------------------------------------------------------------
+
 entity transmitter is
   port (
     clk    : in  std_logic;
@@ -16,14 +29,14 @@ end transmitter;
 
 --------------------------------------------------------------------------------
 
-architecture dataflow of transmitter is
+architecture behavioral of transmitter is
   
   -- Output shift register (containing also start and stop bit).
   signal tx_shift_reg : std_logic_vector (9 downto 0);
   -- Register parallel to the output shift register where '1' shows the last
   -- bit of the frame ('1' is in the place of stop bit).
   signal tx_flag      : std_logic_vector (9 downto 0);
-  -- Transmitting of new frame could be started with next tx_clk.
+  -- Transmitting of new frame could be started with next clk.
   signal tx_ready     : std_logic;
 
 --------------------------------------------------------------------------------
@@ -61,5 +74,5 @@ begin
   
   tx <= tx_shift_reg(0);
   
-end dataflow;
+end behavioral;