2 use ieee.std_logic_1164.all;
3 use ieee.std_logic_arith.all;
4 use ieee.std_logic_unsigned.all;
6 --------------------------------------------------------------------------------
7 -- Transmitter control FSM
9 -- Finite state machine controlling interconnection of FIFO buffer and output
11 --------------------------------------------------------------------------------
17 tx_ready : in std_logic;
18 fifo_empty : in std_logic;
19 tx_we : out std_logic;
20 fifo_pop : out std_logic
24 --------------------------------------------------------------------------------
26 architecture behavioral of tx_control is
28 type state_t is (waiting, next_frame, transmitting);
30 signal state : state_t := waiting;
32 --------------------------------------------------------------------------------
38 if (rising_edge(clk)) then
45 if (fifo_empty = '0') then
50 if (tx_ready = '0') then
51 state <= transmitting;
55 if (tx_ready = '1') then
56 if (fifo_empty = '0') then
68 process (state, tx_ready)
77 if (tx_ready = '0') then
89 --------------------------------------------------------------------------------