2 use ieee.std_logic_1164.all;
3 use ieee.std_logic_arith.all;
4 use ieee.std_logic_unsigned.all;
6 --------------------------------------------------------------------------------
7 -- Input shift register
9 -- It is used to receive a serial asynchronous frame. In the steady state, the
10 -- signal 'ready' is set, the 'data' output vector and signals 'bad_start_bit'
11 -- and 'bad_stop_bit' contains valid values of the last received frame.
13 -- Receiving is done by the following procedure:
14 -- - wait until 'ready' = 1
15 -- - set 'en' and raise 'clk' positive edge (1st bit is sampled)
16 -- - 'ready' goes to 0
17 -- - continue generating clock signal until 'ready' = 1 again
18 -- - frame is received
20 -- All operations, 'rx' sampling, etc. (except for reset) are synchronous to
21 -- 'clk' rising egdes.
23 -- Invalid start bit is signalized at the begining of the frame, so the
24 -- receiving can be immediately stopped by receiver reset.
25 --------------------------------------------------------------------------------
33 ready : out std_logic;
34 bad_start_bit : out std_logic;
35 bad_stop_bit : out std_logic;
36 data : out std_logic_vector (7 downto 0));
39 --------------------------------------------------------------------------------
41 architecture behavioral of receiver is
43 signal rx_shift_reg : std_logic_vector (9 downto 0);
44 signal rx_flag : std_logic_vector (9 downto 0);
45 signal rx_ready : std_logic;
46 signal rx_running : std_logic;
48 --------------------------------------------------------------------------------
52 process (clk, reset) is
61 elsif clk'event and clk = '1' then
62 -- Start receiving a new frame
63 if rx_ready = '1' and en = '1' then
64 rx_shift_reg <= rx & rx_shift_reg (9 downto 1);
65 rx_flag <= "0100000000";
72 -- Receiving of the 1st data bit and all its consequents
73 elsif rx_running = '1' then
74 rx_shift_reg <= rx & rx_shift_reg (9 downto 1);
75 rx_flag <= '0' & rx_flag (9 downto 1);
77 -- End of the frame is comming
78 if rx_flag (0) = '1' then
82 bad_stop_bit <= not rx;
89 --------------------------------------------------------------------------------
91 data <= rx_shift_reg (8 downto 1);
94 end architecture behavioral;