architecture behavioral of top_counter is
- component div_20 is
- port (
- clk : in std_logic;
- clk_2k : out std_logic);
- end component;
-
- component hex2lcd is
- port (
- hex : in std_logic_vector (3 downto 0);
- lcd : out std_logic_vector (6 downto 0));
- end component;
-
- component lcd_mux is
- port (
- clk : in std_logic;
- cnt : in std_logic;
- data_in : in std_logic_vector (6 downto 0);
- lcd_seg : out std_logic_vector (6 downto 0);
- lcd_com : out std_logic;
- lcd_dp : out std_logic);
- end component;
-
- component qcounter is
- port (
- clock : in std_logic;
- reset : in std_logic;
- a0, b0 : in std_logic;
- qcount : out std_logic_vector (31 downto 0);
- a_rise : out std_logic;
- a_fall : out std_logic;
- b_rise : out std_logic;
- b_fall : out std_logic;
- ab_event : out std_logic;
- ab_error : out std_logic);
- end component;
-
-
signal lcd_clk : std_logic;
signal lcd1_out : std_logic_vector (6 downto 0);
signal lcd2_out : std_logic_vector (6 downto 0);
begin
- div_20_1 : div_20
+ div_20_1 : entity work.div_20
port map (
clk => clk,
clk_2k => lcd_clk);
- hex2lcd_1 : hex2lcd
+ hex2lcd_1 : entity work.hex2lcd
port map (
hex => qcount_data(5 downto 2),
lcd => lcd1_out);
- hex2lcd_2 : hex2lcd
+ hex2lcd_2 : entity work.hex2lcd
port map (
hex => qcount_data(9 downto 6),
lcd => lcd2_out);
- lcd_mux_1 : lcd_mux
+ lcd_mux_1 : entity work.lcd_mux
port map (
clk => clk,
cnt => lcd_clk,
lcd_com => lcd_com,
lcd_dp => lcd1_dp);
- lcd_mux_2 : lcd_mux
+ lcd_mux_2 : entity work.lcd_mux
port map (
clk => clk,
cnt => lcd_clk,
lcd_com => open,
lcd_dp => lcd2_dp);
- qcounter_1 : qcounter
+ qcounter_1 : entity work.qcounter
port map (
clock => clk,
reset => qcount_reset,