PWM selection signal added.

[fpga/pwm.git] / pwm.vhd

diff --git a/pwm.vhd b/pwm.vhd
index 4ac8765f48e1ece55a00f0b2bb3c7d2262d29b9d..a0a9673e8fa84af494f3729f3e657ab19349dd7d 100644 (file)
--- a/pwm.vhd
+++ b/pwm.vhd
@@ -30,6 +30,7 @@ entity pwm is
     clk     : in  std_logic;
     reset   : in  std_logic;
     din     : in  std_logic_vector (PWM_WIDTH-1 downto 0);
+    sel     : in  std_logic;
     we      : in  std_logic;
     -- PWM interface
     pwm_cnt : in  std_logic_vector (PWM_WIDTH-1 downto 0);
@@ -57,7 +58,7 @@ begin
       if reset = '1' then
         reg <= (others => '0');
       else
-        if we = '1' then
+        if we = '1' and sel = '1' then
           reg <= din;
         end if;
       end if;