Wave_table initialization data format modified.

[fpga/pwm.git] / mcc.vhd

diff --git a/mcc.vhd b/mcc.vhd
index 156a84041bc65d2ba2185776ee5d0f146b231b4a..01ef9c4459616194a0c1f98d3a17101aaf76943f 100644 (file)
--- a/mcc.vhd
+++ b/mcc.vhd
@@ -28,7 +28,7 @@ entity mcc is
     PWM3_STB_O : out std_logic;
     -- Shared memory interface
     IRF_ACK_I  : in  std_logic;
-    IRF_ADR_O  : out std_logic_vector (IRF_ADR_W-1 downto 0);
+    IRF_ADR_O  : out std_logic_vector (4 downto 0);
     IRF_DAT_I  : in  std_logic_vector (15 downto 0);
     IRF_DAT_O  : out std_logic_vector (15 downto 0);
     IRF_STB_O  : out std_logic;
@@ -74,9 +74,13 @@ architecture behavioral of mcc is
   signal SCALE_SL_ACK_O     : std_logic;
   signal SCALE_SL_IRF_ADR_O : std_logic_vector (IRF_ADR_W-1 downto 0);
   signal SCALE_SL_STB_I     : std_logic;
+
+  signal PMIN_IRF_ADR_O : std_logic_vector (IRF_ADR_W-1 downto 0);
+  signal PMIN_IRF_DAT_O : std_logic_vector (15 downto 0);
+  signal PMIN_IRF_STB_O : std_logic;
+  signal PMIN_IRF_WE_O  : std_logic;
   
   signal PWM_IRF_ADR_O    : std_logic_vector (IRF_ADR_W-1 downto 0);
-  signal PWM_IRF_DAT_O    : std_logic_vector (15 downto 0);
   signal PWM_IRF_STB_O    : std_logic;
   --signal PWM_DAT_O        : std_logic_vector (LUT_DAT_W-1 downto 0);
   signal PWM_STB_O        : std_logic;
@@ -115,22 +119,24 @@ begin
                BASE_IRF_ADR_O   when MCC_MUX_CODE = 1 else
                VECTOR_IRF_ADR_O when MCC_MUX_CODE = 2 else
                SCALE_IRF_ADR_O  when MCC_MUX_CODE = 3 else
+               PMIN_IRF_ADR_O   when MCC_MUX_CODE = 4 else
                PWM_IRF_ADR_O    when MCC_MUX_CODE = 5 else
-               (others => '-');
+               (others => 'X');
 
   IRF_DAT_O <= MASTER_IRF_DAT_O when MCC_MUX_EN = '0' else
                IRC_IRF_DAT_O    when MCC_MUX_CODE = 0 else
                BASE_IRF_DAT_O   when MCC_MUX_CODE = 1 else
                VECTOR_IRF_DAT_O when MCC_MUX_CODE = 2 else
                SCALE_IRF_DAT_O  when MCC_MUX_CODE = 3 else
-               PWM_IRF_DAT_O    when MCC_MUX_CODE = 5 else
-               (others => '-');
+               PMIN_IRF_DAT_O   when MCC_MUX_CODE = 4 else
+               (others => 'X');
 
   IRF_STB_O <= MASTER_IRF_STB_O when MCC_MUX_EN = '0' else
                IRC_IRF_STB_O    when MCC_MUX_CODE = 0 else
                BASE_IRF_STB_O   when MCC_MUX_CODE = 1 else
                VECTOR_IRF_STB_O when MCC_MUX_CODE = 2 else
                SCALE_IRF_STB_O  when MCC_MUX_CODE = 3 else
+               PMIN_IRF_STB_O   when MCC_MUX_CODE = 4 else
                PWM_IRF_STB_O    when MCC_MUX_CODE = 5 else
                '0';
 
@@ -139,6 +145,7 @@ begin
               BASE_IRF_WE_O   when MCC_MUX_CODE = 1 else
               VECTOR_IRF_WE_O when MCC_MUX_CODE = 2 else
               SCALE_IRF_WE_O  when MCC_MUX_CODE = 3 else
+              PMIN_IRF_WE_O   when MCC_MUX_CODE = 4 else
               '0';
 
 
@@ -146,6 +153,7 @@ begin
   PWM2_STB_O <= PWM_STB_O when PWM_SL_MUX_CODE = 1 else '0';
   PWM3_STB_O <= PWM_STB_O when PWM_SL_MUX_CODE = 2 else '0';
 
+
   
   mcc_master_1 : entity work.mcc_master
     generic map (
@@ -213,8 +221,8 @@ begin
   
   vector_gen_1 : entity work.vector_gen
     generic map (
-      LUT_DAT_W => 10,
-      LUT_ADR_W => 11,
+      LUT_DAT_W => LUT_DAT_W,
+      LUT_ADR_W => LUT_ADR_W,
       LUT_P1_OFF => 0,
       LUT_P2_OFF => 333,
       LUT_P3_OFF => 667,
@@ -280,6 +288,26 @@ begin
       IRF_STB_O => SCALE_IRF_STB_O,
       IRF_WE_O  => SCALE_IRF_WE_O);
 
+  pwm_min_1 : entity work.pwm_min
+    generic map (
+      IRF_ADR_W  => IRF_ADR_W,
+      PWM_W      => LUT_DAT_W,
+      BASE       => 0,
+      PWMMIN_OFF => 6,
+      P_BASE     => P_BASE,
+      P_SIZE     => P_SIZE,
+      PWM_OFF    => 1)
+    port map (
+      ACK_O     => MCC_ACK (4),
+      CLK_I     => CLK_I,
+      RST_I     => RST_I,
+      STB_I     => MCC_STB (4),
+      IRF_ACK_I => IRF_ACK_I,
+      IRF_ADR_O => PMIN_IRF_ADR_O,
+      IRF_DAT_I => IRF_DAT_I,
+      IRF_DAT_O => PMIN_IRF_DAT_O,
+      IRF_STB_O => PMIN_IRF_STB_O,
+      IRF_WE_O  => PMIN_IRF_WE_O);
   
   pwm_dump_sequencer : entity work.sequencer
     generic map (
@@ -297,12 +325,14 @@ begin
       SL_STB_O     => PWM_SL_STB_I,
       SL_MUX_CODE  => PWM_SL_MUX_CODE);
 
-  pwm_dump_1 : entity work.pwm_dump
+  pwm_min_dump_1 : entity work.pwm_min_dump
     generic map (
-      IRF_ADR_W => IRF_ADR_W,
-      P_BASE    => P_BASE,
-      PWM_OFF   => 1,
-      PWM_W     => LUT_DAT_W)
+      IRF_ADR_W  => IRF_ADR_W,
+      BASE       => 0,
+      PWMMIN_OFF => 6,
+      P_BASE     => P_BASE,
+      PWM_OFF    => 1,
+      PWM_W      => LUT_DAT_W)
     port map (
       ACK_O     => PWM_SL_ACK_O,
       CLK_I     => CLK_I,