Wave_table initialization data format modified.

[fpga/pwm.git] / irc_base.vhd

diff --git a/irc_base.vhd b/irc_base.vhd
index c99625a5d78a505418590926c9924feae8fcabd4..4af41937599d4384393f75ad84668abba543a2a9 100644 (file)
--- a/irc_base.vhd
+++ b/irc_base.vhd
@@ -15,7 +15,7 @@ entity irc_base is
     A_OFF     : integer := 4);
   port (
     -- Primary slave interface
-    ACK_O     : out std_logic;
+    ACK_O     : out std_logic := '0';
     CLK_I     : in  std_logic;
     RST_I     : in  std_logic;
     STB_I     : in  std_logic;
@@ -24,8 +24,8 @@ entity irc_base is
     IRF_ADR_O : out std_logic_vector (IRF_ADR_W-1 downto 0);
     IRF_DAT_I : in  std_logic_vector (15 downto 0);
     IRF_DAT_O : out std_logic_vector (15 downto 0);
-    IRF_STB_O : out std_logic;
-    IRF_WE_O  : out std_logic;
+    IRF_STB_O : out std_logic := '0';
+    IRF_WE_O  : out std_logic := '0';
     -- Error flag
     BAD_BASE : out std_logic);
 end entity irc_base;
@@ -43,7 +43,7 @@ architecture behavioral of irc_base is
   constant ANG_ADR  : irf_adr_t := conv_std_logic_vector(BASE+A_OFF, IRF_ADR_W);
 
   
-  signal state    : state_t;
+  signal state    : state_t := ready;
   signal irc      : std_logic_vector (15 downto 0);
   signal irc_base : std_logic_vector (15 downto 0);
   signal irc_per  : std_logic_vector (15 downto 0);