+ vector_scale_sequencer : entity work.sequencer
+ generic map (
+ IRF_ADR_W => IRF_ADR_W,
+ P_BASE => P_BASE,
+ P_SIZE => P_SIZE)
+ port map (
+ ACK_O => MCC_ACK (3),
+ CLK_I => CLK_I,
+ RST_I => RST_I,
+ STB_I => MCC_STB (3),
+ IRF_ADR_O => SCALE_IRF_ADR_O,
+ SL_ACK_I => SCALE_SL_ACK_O,
+ SL_IRF_ADR_I => SCALE_SL_IRF_ADR_O,
+ SL_STB_O => SCALE_SL_STB_I,
+ SL_MUX_CODE => open);
+
+ vector_scale_1 : entity work.vector_scale
+ generic map (
+ IRF_ADR_W => IRF_ADR_W,
+ BASE => 0,
+ SCALE_OFF => 5,
+ PHASE_BASE => P_BASE,
+ VECTOR_OFF => 0,
+ SCALED_OFF => 1,
+ VECTOR_W => LUT_DAT_W)
+ port map (
+ ACK_O => SCALE_SL_ACK_O,
+ CLK_I => CLK_I,
+ RST_I => RST_I,
+ STB_I => SCALE_SL_STB_I,
+ MUL_A => MUL_A,
+ MUL_B => MUL_B,
+ MUL_PROD => MUL_PROD,
+ IRF_ACK_I => IRF_ACK_I,
+ IRF_ADR_O => SCALE_SL_IRF_ADR_O,
+ IRF_DAT_I => IRF_DAT_I,
+ IRF_DAT_O => SCALE_IRF_DAT_O,
+ IRF_STB_O => SCALE_IRF_STB_O,
+ IRF_WE_O => SCALE_IRF_WE_O);
+
+ pwm_min_1 : entity work.pwm_min
+ generic map (
+ IRF_ADR_W => IRF_ADR_W,
+ PWM_W => LUT_DAT_W,
+ BASE => 0,
+ PWMMIN_OFF => 6,
+ P_BASE => P_BASE,
+ P_SIZE => P_SIZE,
+ PWM_OFF => 1)
+ port map (
+ ACK_O => MCC_ACK (4),
+ CLK_I => CLK_I,
+ RST_I => RST_I,
+ STB_I => MCC_STB (4),
+ IRF_ACK_I => IRF_ACK_I,
+ IRF_ADR_O => PMIN_IRF_ADR_O,
+ IRF_DAT_I => IRF_DAT_I,
+ IRF_DAT_O => PMIN_IRF_DAT_O,
+ IRF_STB_O => PMIN_IRF_STB_O,
+ IRF_WE_O => PMIN_IRF_WE_O);
+