entity mcc is
generic (
LUT_ADR_W : integer := 10;
- LUT_DAT_W : integer := 9;
- IRF_ADR_W : integer := 5);
+ LUT_DAT_W : integer := 9);
port (
-- Primary slave intefrace
ACK_O : out std_logic;
PWM3_STB_O : out std_logic;
-- Shared memory interface
IRF_ACK_I : in std_logic;
- IRF_ADR_O : out std_logic_vector (IRF_ADR_W-1 downto 0);
+ IRF_ADR_O : out std_logic_vector (4 downto 0);
IRF_DAT_I : in std_logic_vector (15 downto 0);
IRF_DAT_O : out std_logic_vector (15 downto 0);
IRF_STB_O : out std_logic;
architecture behavioral of mcc is
- constant MCC_W : integer := 5;
- constant MUX_W : integer := 2;
+ constant IRF_ADR_W : integer := 5;
+ constant MCC_W : integer := 6;
+ constant MUX_W : integer := 3;
+
+ constant P_BASE : integer := 16;
+ constant P_SIZE : integer := 4;
+
signal MCC_ACK : std_logic_vector (MCC_W-1 downto 0);
signal MCC_STB : std_logic_vector (MCC_W-1 downto 0);
signal MCC_MUX_CODE : std_logic_vector (MUX_W-1 downto 0);
signal MCC_MUX_EN : std_logic;
+ signal MUL_A : std_logic_vector (15 downto 0);
+ signal MUL_B : std_logic_vector (15 downto 0);
+ signal MUL_PROD : std_logic_vector (31 downto 0);
+
signal MASTER_IRF_ADR_O : std_logic_vector (IRF_ADR_W-1 downto 0);
signal MASTER_IRF_DAT_O : std_logic_vector (15 downto 0);
signal MASTER_IRF_STB_O : std_logic;
signal VECTOR_IRF_STB_O : std_logic;
signal VECTOR_IRF_WE_O : std_logic;
+ signal SCALE_IRF_ADR_O : std_logic_vector (IRF_ADR_W-1 downto 0);
+ signal SCALE_IRF_DAT_O : std_logic_vector (15 downto 0);
+ signal SCALE_IRF_STB_O : std_logic;
+ signal SCALE_IRF_WE_O : std_logic;
+ signal SCALE_SL_ACK_O : std_logic;
+ signal SCALE_SL_IRF_ADR_O : std_logic_vector (IRF_ADR_W-1 downto 0);
+ signal SCALE_SL_STB_I : std_logic;
+
+ signal PMIN_IRF_ADR_O : std_logic_vector (IRF_ADR_W-1 downto 0);
+ signal PMIN_IRF_DAT_O : std_logic_vector (15 downto 0);
+ signal PMIN_IRF_STB_O : std_logic;
+ signal PMIN_IRF_WE_O : std_logic;
+
+ signal PWM_IRF_ADR_O : std_logic_vector (IRF_ADR_W-1 downto 0);
+ signal PWM_IRF_STB_O : std_logic;
+ --signal PWM_DAT_O : std_logic_vector (LUT_DAT_W-1 downto 0);
+ signal PWM_STB_O : std_logic;
+ signal PWM_SL_ACK_O : std_logic;
+ signal PWM_SL_IRF_ADR_O : std_logic_vector (IRF_ADR_W-1 downto 0);
+ signal PWM_SL_STB_I : std_logic;
+ signal PWM_SL_MUX_CODE : std_logic_vector (1 downto 0);
+
+ signal IRC_IRF_ADR_O : std_logic_vector (IRF_ADR_W-1 downto 0);
+ signal IRC_IRF_DAT_O : std_logic_vector (15 downto 0);
+ signal IRC_IRF_STB_O : std_logic;
+ signal IRC_IRF_WE_O : std_logic;
+
+ signal BASE_IRF_ADR_O : std_logic_vector (IRF_ADR_W-1 downto 0);
+ signal BASE_IRF_DAT_O : std_logic_vector (15 downto 0);
+ signal BASE_IRF_STB_O : std_logic;
+ signal BASE_IRF_WE_O : std_logic;
+
type state_t is (ready, read_mask, do_mcc, done);
begin
IRF_ADR_O <= MASTER_IRF_ADR_O when MCC_MUX_EN = '0' else
- VECTOR_IRF_ADR_O when MCC_MUX_CODE = 1 else
- (others => '-');
+ IRC_IRF_ADR_O when MCC_MUX_CODE = 0 else
+ BASE_IRF_ADR_O when MCC_MUX_CODE = 1 else
+ VECTOR_IRF_ADR_O when MCC_MUX_CODE = 2 else
+ SCALE_IRF_ADR_O when MCC_MUX_CODE = 3 else
+ PMIN_IRF_ADR_O when MCC_MUX_CODE = 4 else
+ PWM_IRF_ADR_O when MCC_MUX_CODE = 5 else
+ (others => 'X');
IRF_DAT_O <= MASTER_IRF_DAT_O when MCC_MUX_EN = '0' else
- VECTOR_IRF_DAT_O when MCC_MUX_CODE = 1 else
- (others => '-');
+ IRC_IRF_DAT_O when MCC_MUX_CODE = 0 else
+ BASE_IRF_DAT_O when MCC_MUX_CODE = 1 else
+ VECTOR_IRF_DAT_O when MCC_MUX_CODE = 2 else
+ SCALE_IRF_DAT_O when MCC_MUX_CODE = 3 else
+ PMIN_IRF_DAT_O when MCC_MUX_CODE = 4 else
+ (others => 'X');
IRF_STB_O <= MASTER_IRF_STB_O when MCC_MUX_EN = '0' else
- VECTOR_IRF_STB_O when MCC_MUX_CODE = 1 else
+ IRC_IRF_STB_O when MCC_MUX_CODE = 0 else
+ BASE_IRF_STB_O when MCC_MUX_CODE = 1 else
+ VECTOR_IRF_STB_O when MCC_MUX_CODE = 2 else
+ SCALE_IRF_STB_O when MCC_MUX_CODE = 3 else
+ PMIN_IRF_STB_O when MCC_MUX_CODE = 4 else
+ PWM_IRF_STB_O when MCC_MUX_CODE = 5 else
'0';
IRF_WE_O <= MASTER_IRF_WE_O when MCC_MUX_EN = '0' else
- VECTOR_IRF_WE_O when MCC_MUX_CODE = 1 else
+ IRC_IRF_WE_O when MCC_MUX_CODE = 0 else
+ BASE_IRF_WE_O when MCC_MUX_CODE = 1 else
+ VECTOR_IRF_WE_O when MCC_MUX_CODE = 2 else
+ SCALE_IRF_WE_O when MCC_MUX_CODE = 3 else
+ PMIN_IRF_WE_O when MCC_MUX_CODE = 4 else
'0';
+
+ PWM1_STB_O <= PWM_STB_O when PWM_SL_MUX_CODE = 0 else '0';
+ PWM2_STB_O <= PWM_STB_O when PWM_SL_MUX_CODE = 1 else '0';
+ PWM3_STB_O <= PWM_STB_O when PWM_SL_MUX_CODE = 2 else '0';
+
+
mcc_master_1 : entity work.mcc_master
generic map (
IRF_STB_O => MASTER_IRF_STB_O,
IRF_WE_O => MASTER_IRF_WE_O);
- vector_gen_1 : entity work.vector_gen
+ multiplier_1 : entity work.multiplier
+ port map (
+ A => MUL_A,
+ B => MUL_B,
+ prod => MUL_PROD);
+
+ irc_dump_1 : entity work.irc_dump
+ generic map (
+ IRF_ADR_W => IRF_ADR_W,
+ IRC_BASE => 16#01#)
+ port map (
+ ACK_O => MCC_ACK (0),
+ CLK_I => CLK_I,
+ RST_I => RST_I,
+ STB_I => MCC_STB (0),
+ IRC_DAT_I => IRC_DAT_I,
+ IRF_ACK_I => IRF_ACK_I,
+ IRF_ADR_O => IRC_IRF_ADR_O,
+ IRF_DAT_O => IRC_IRF_DAT_O,
+ IRF_STB_O => IRC_IRF_STB_O,
+ IRF_WE_O => IRC_IRF_WE_O);
+
+ irc_base_1 : entity work.irc_base
generic map (
- A_BASE => 1,
- P_BASE => 2)
+ IRF_ADR_W => IRF_ADR_W,
+ BASE => 16#00#,
+ IRC_OFF => 16#01#,
+ ABASE_OFF => 16#02#,
+ APER_OFF => 16#03#,
+ A_OFF => 16#04#)
port map (
ACK_O => MCC_ACK (1),
CLK_I => CLK_I,
RST_I => RST_I,
STB_I => MCC_STB (1),
IRF_ACK_I => IRF_ACK_I,
+ IRF_ADR_O => BASE_IRF_ADR_O,
+ IRF_DAT_I => IRF_DAT_I,
+ IRF_DAT_O => BASE_IRF_DAT_O,
+ IRF_STB_O => BASE_IRF_STB_O,
+ IRF_WE_O => BASE_IRF_WE_O,
+ BAD_BASE => open);
+
+ vector_gen_1 : entity work.vector_gen
+ generic map (
+ LUT_DAT_W => LUT_DAT_W,
+ LUT_ADR_W => LUT_ADR_W,
+ LUT_P1_OFF => 0,
+ LUT_P2_OFF => 333,
+ LUT_P3_OFF => 667,
+ IRF_ADR_W => 5,
+ A_BASE => 16#04#,
+ P_BASE => 16#10#,
+ P1_OFF => 16#00#,
+ P2_OFF => 16#04#,
+ P3_OFF => 16#08#)
+ port map (
+ ACK_O => MCC_ACK (2),
+ CLK_I => CLK_I,
+ RST_I => RST_I,
+ STB_I => MCC_STB (2),
+ IRF_ACK_I => IRF_ACK_I,
IRF_ADR_O => VECTOR_IRF_ADR_O,
IRF_CYC_O => open,
IRF_DAT_I => IRF_DAT_I,
LUT_DAT_I => LUT_DAT_I,
LUT_STB_O => LUT_STB_O);
+ vector_scale_sequencer : entity work.sequencer
+ generic map (
+ IRF_ADR_W => IRF_ADR_W,
+ P_BASE => P_BASE,
+ P_SIZE => P_SIZE)
+ port map (
+ ACK_O => MCC_ACK (3),
+ CLK_I => CLK_I,
+ RST_I => RST_I,
+ STB_I => MCC_STB (3),
+ IRF_ADR_O => SCALE_IRF_ADR_O,
+ SL_ACK_I => SCALE_SL_ACK_O,
+ SL_IRF_ADR_I => SCALE_SL_IRF_ADR_O,
+ SL_STB_O => SCALE_SL_STB_I,
+ SL_MUX_CODE => open);
+
+ vector_scale_1 : entity work.vector_scale
+ generic map (
+ IRF_ADR_W => IRF_ADR_W,
+ BASE => 0,
+ SCALE_OFF => 5,
+ PHASE_BASE => P_BASE,
+ VECTOR_OFF => 0,
+ SCALED_OFF => 1,
+ VECTOR_W => LUT_DAT_W)
+ port map (
+ ACK_O => SCALE_SL_ACK_O,
+ CLK_I => CLK_I,
+ RST_I => RST_I,
+ STB_I => SCALE_SL_STB_I,
+ MUL_A => MUL_A,
+ MUL_B => MUL_B,
+ MUL_PROD => MUL_PROD,
+ IRF_ACK_I => IRF_ACK_I,
+ IRF_ADR_O => SCALE_SL_IRF_ADR_O,
+ IRF_DAT_I => IRF_DAT_I,
+ IRF_DAT_O => SCALE_IRF_DAT_O,
+ IRF_STB_O => SCALE_IRF_STB_O,
+ IRF_WE_O => SCALE_IRF_WE_O);
+
+ pwm_min_1 : entity work.pwm_min
+ generic map (
+ IRF_ADR_W => IRF_ADR_W,
+ PWM_W => LUT_DAT_W,
+ BASE => 0,
+ PWMMIN_OFF => 6,
+ P_BASE => P_BASE,
+ P_SIZE => P_SIZE,
+ PWM_OFF => 1)
+ port map (
+ ACK_O => MCC_ACK (4),
+ CLK_I => CLK_I,
+ RST_I => RST_I,
+ STB_I => MCC_STB (4),
+ IRF_ACK_I => IRF_ACK_I,
+ IRF_ADR_O => PMIN_IRF_ADR_O,
+ IRF_DAT_I => IRF_DAT_I,
+ IRF_DAT_O => PMIN_IRF_DAT_O,
+ IRF_STB_O => PMIN_IRF_STB_O,
+ IRF_WE_O => PMIN_IRF_WE_O);
+
+ pwm_dump_sequencer : entity work.sequencer
+ generic map (
+ IRF_ADR_W => IRF_ADR_W,
+ P_BASE => P_BASE,
+ P_SIZE => P_SIZE)
+ port map (
+ ACK_O => MCC_ACK (5),
+ CLK_I => CLK_I,
+ RST_I => RST_I,
+ STB_I => MCC_STB (5),
+ IRF_ADR_O => PWM_IRF_ADR_O,
+ SL_ACK_I => PWM_SL_ACK_O,
+ SL_IRF_ADR_I => PWM_SL_IRF_ADR_O,
+ SL_STB_O => PWM_SL_STB_I,
+ SL_MUX_CODE => PWM_SL_MUX_CODE);
+
+ pwm_min_dump_1 : entity work.pwm_min_dump
+ generic map (
+ IRF_ADR_W => IRF_ADR_W,
+ BASE => 0,
+ PWMMIN_OFF => 6,
+ P_BASE => P_BASE,
+ PWM_OFF => 1,
+ PWM_W => LUT_DAT_W)
+ port map (
+ ACK_O => PWM_SL_ACK_O,
+ CLK_I => CLK_I,
+ RST_I => RST_I,
+ STB_I => PWM_SL_STB_I,
+ PWM_DAT_O => PWM_DAT_O,
+ PWM_STB_O => PWM_STB_O,
+ IRF_ACK_I => IRF_ACK_I,
+ IRF_ADR_O => PWM_SL_IRF_ADR_O,
+ IRF_DAT_I => IRF_DAT_I,
+ IRF_STB_O => PWM_IRF_STB_O);
+
end architecture behavioral;
projects / fpga / pwm.git / blobdiff