Wave_table initialization data format modified.

[fpga/pwm.git] / pwm_dump.vhd

diff --git a/pwm_dump.vhd b/pwm_dump.vhd
index bf6b8c632bfd96b63ffa30e6be284013f3613494..adcf7326c1c14e38a97436555cc0713f2e59565c 100644 (file)
--- a/pwm_dump.vhd
+++ b/pwm_dump.vhd
@@ -19,7 +19,7 @@ entity pwm_dump is
     STB_I     : in  std_logic;
     -- PWM interface
     PWM_DAT_O : out std_logic_vector (PWM_W-1 downto 0);
-    PWM_STB_O : out std_logic;
+    PWM_STB_O : out std_logic := '0';
     -- Shared dual-port memory
     IRF_ACK_I : in  std_logic;
     IRF_ADR_O : out std_logic_vector (IRF_ADR_W-1 downto 0);
@@ -36,9 +36,9 @@ architecture behavioral of pwm_dump is
 
   constant PWM_ADR : irf_adr_t :=  conv_std_logic_vector(P_BASE + PWM_OFF, IRF_ADR_W);
   
-  signal state : state_t;
+  signal state : state_t := ready;
 
-  signal INNER_ACK : std_logic;
+  signal INNER_ACK : std_logic := '0';
   
 --------------------------------------------------------------------------------
 
@@ -54,27 +54,29 @@ begin
   
   FSM : process (CLK_I, RST_I) is
   begin
-    if RST_I = '1' then
-      state     <= ready;
-      INNER_ACK <= '0';
-      PWM_STB_O <= '0';
+    if rising_edge(CLK_I) then
+      if RST_I = '1' then
+        state     <= ready;
+        INNER_ACK <= '0';
+        PWM_STB_O <= '0';
       
-    elsif rising_edge(CLK_I) then
-      case state is
-        when ready =>
-          if STB_I = '1' then
-            state     <= done;
-            INNER_ACK <= '1';
-            PWM_STB_O <= '1';
-          end if;
+      else  
+        case state is
+          when ready =>
+            if STB_I = '1' then
+              state     <= done;
+              INNER_ACK <= '1';
+              PWM_STB_O <= '1';
+            end if;
 
-        when done =>
-          PWM_STB_O <= '0';
-          if STB_I = '0' then
-            state     <= ready;
-            INNER_ACK <= '0';
-          end if;
-      end case;
+          when done =>
+            PWM_STB_O <= '0';
+            if STB_I = '0' then
+              state     <= ready;
+              INNER_ACK <= '0';
+            end if;
+        end case;
+      end if;
     end if;
   end process;