-- Peripheral register
PWM_REGISTER : process (clk, reset)
begin
- if reset = '1' then
- reg <= (others => '0');
-
- elsif rising_edge(clk) then
- if we = '1' then
- reg <= din;
+ if rising_edge(clk) then
+ if reset = '1' then
+ reg <= (others => '0');
+ else
+ if we = '1' then
+ reg <= din;
+ end if;
end if;
end if;
end process;
-- with next clk edge. Pwm output is delayed by one clock.
PWM_GEN : process (clk, reset)
begin
- if reset = '1' then
- pwm <= '0';
-
- elsif rising_edge(clk) then
- if pwm_cyc = '1' then
- cmp <= reg;
- end if;
-
- if pwm_cnt < cmp then
- pwm <= '1';
- else
+ if rising_edge(clk) then
+ if reset = '1' then
pwm <= '0';
+
+ else
+ if pwm_cyc = '1' then
+ cmp <= reg;
+ end if;
+
+ if pwm_cnt < cmp then
+ pwm <= '1';
+ else
+ pwm <= '0';
+ end if;
end if;
end if;
end process;