PWM selection signal added.

[fpga/pwm.git] / pwm.vhd

diff --git a/pwm.vhd b/pwm.vhd
index 3590d5423041628c317a966c69c3bf6069edae3d..a0a9673e8fa84af494f3729f3e657ab19349dd7d 100644 (file)
--- a/pwm.vhd
+++ b/pwm.vhd
@@ -30,6 +30,7 @@ entity pwm is
     clk     : in  std_logic;
     reset   : in  std_logic;
     din     : in  std_logic_vector (PWM_WIDTH-1 downto 0);
+    sel     : in  std_logic;
     we      : in  std_logic;
     -- PWM interface
     pwm_cnt : in  std_logic_vector (PWM_WIDTH-1 downto 0);
@@ -53,12 +54,13 @@ begin
   -- Peripheral register
   PWM_REGISTER : process (clk, reset)
   begin
-    if reset = '1' then
-      reg <= (others => '0');
-
-    elsif rising_edge(clk) then
-      if we = '1' then
-        reg <= din;
+    if rising_edge(clk) then
+      if reset = '1' then
+        reg <= (others => '0');
+      else
+        if we = '1' and sel = '1' then
+          reg <= din;
+        end if;
       end if;
     end if;
   end process;
@@ -69,18 +71,20 @@ begin
   -- with next clk edge. Pwm output is delayed by one clock.
   PWM_GEN : process (clk, reset)
   begin
-    if reset = '1' then
-      pwm <= '0';
-      
-    elsif rising_edge(clk) then
-      if pwm_cyc = '1' then
-        cmp <= reg;
-      end if;
-      
-      if pwm_cnt < cmp then
-        pwm <= '1';
-      else
+    if rising_edge(clk) then
+      if reset = '1' then
         pwm <= '0';
+
+      else  
+        if pwm_cyc = '1' then
+          cmp <= reg;
+        end if;
+        
+        if pwm_cnt < cmp then
+          pwm <= '1';
+        else
+          pwm <= '0';
+        end if;
       end if;
     end if;
   end process;