Multiplier and vector scaling components added

[fpga/pwm.git] / mcc.vhd

diff --git a/mcc.vhd b/mcc.vhd
index 47b9879a6b5747fd9fd85c5178bf20babe424655..5513069a9c38935fad0e25290660065a00950097 100644 (file)
--- a/mcc.vhd
+++ b/mcc.vhd
@@ -52,6 +52,10 @@ architecture behavioral of mcc is
   signal MCC_MUX_CODE : std_logic_vector (MUX_W-1 downto 0);
   signal MCC_MUX_EN   : std_logic;
 
+  signal MUL_A    : std_logic_vector (15 downto 0);
+  signal MUL_B    : std_logic_vector (15 downto 0);
+  signal MUL_PROD : std_logic_vector (31 downto 0);
+  
   signal MASTER_IRF_ADR_O : std_logic_vector (IRF_ADR_W-1 downto 0);
   signal MASTER_IRF_DAT_O : std_logic_vector (15 downto 0);
   signal MASTER_IRF_STB_O : std_logic;
@@ -62,6 +66,14 @@ architecture behavioral of mcc is
   signal VECTOR_IRF_STB_O : std_logic;
   signal VECTOR_IRF_WE_O  : std_logic;
 
+  signal SCALE_IRF_ADR_O    : std_logic_vector (IRF_ADR_W-1 downto 0);
+  signal SCALE_IRF_DAT_O    : std_logic_vector (15 downto 0);
+  signal SCALE_IRF_STB_O    : std_logic;
+  signal SCALE_IRF_WE_O     : std_logic;
+  signal SCALE_SL_ACK_O     : std_logic;
+  signal SCALE_SL_IRF_ADR_O : std_logic_vector (IRF_ADR_W-1 downto 0);
+  signal SCALE_SL_STB_I     : std_logic;
+  
   signal PWM_IRF_ADR_O    : std_logic_vector (IRF_ADR_W-1 downto 0);
   signal PWM_IRF_DAT_O    : std_logic_vector (15 downto 0);
   signal PWM_IRF_STB_O    : std_logic;
@@ -101,6 +113,7 @@ begin
                IRC_IRF_ADR_O    when MCC_MUX_CODE = 0 else
                BASE_IRF_ADR_O   when MCC_MUX_CODE = 1 else
                VECTOR_IRF_ADR_O when MCC_MUX_CODE = 2 else
+               SCALE_IRF_ADR_O  when MCC_MUX_CODE = 3 else
                PWM_IRF_ADR_O    when MCC_MUX_CODE = 5 else
                (others => '-');
 
@@ -108,6 +121,7 @@ begin
                IRC_IRF_DAT_O    when MCC_MUX_CODE = 0 else
                BASE_IRF_DAT_O   when MCC_MUX_CODE = 1 else
                VECTOR_IRF_DAT_O when MCC_MUX_CODE = 2 else
+               SCALE_IRF_DAT_O  when MCC_MUX_CODE = 3 else
                PWM_IRF_DAT_O    when MCC_MUX_CODE = 5 else
                (others => '-');
 
@@ -115,6 +129,7 @@ begin
                IRC_IRF_STB_O    when MCC_MUX_CODE = 0 else
                BASE_IRF_STB_O   when MCC_MUX_CODE = 1 else
                VECTOR_IRF_STB_O when MCC_MUX_CODE = 2 else
+               SCALE_IRF_STB_O  when MCC_MUX_CODE = 3 else
                PWM_IRF_STB_O    when MCC_MUX_CODE = 5 else
                '0';
 
@@ -122,6 +137,7 @@ begin
               IRC_IRF_WE_O    when MCC_MUX_CODE = 0 else
               BASE_IRF_WE_O   when MCC_MUX_CODE = 1 else
               VECTOR_IRF_WE_O when MCC_MUX_CODE = 2 else
+              SCALE_IRF_WE_O  when MCC_MUX_CODE = 3 else
               '0';
 
 
@@ -151,6 +167,12 @@ begin
       IRF_STB_O    => MASTER_IRF_STB_O,
       IRF_WE_O     => MASTER_IRF_WE_O);
 
+  multiplier_1 : entity work.multiplier
+    port map (
+      A    => MUL_A,
+      B    => MUL_B,
+      prod => MUL_PROD);
+
   irc_dump_1 : entity work.irc_dump
     generic map (
       IRF_ADR_W => IRF_ADR_W,
@@ -198,9 +220,9 @@ begin
       IRF_ADR_W => 5,
       A_BASE => 16#04#,
       P_BASE => 16#10#,
-      P1_OFF => 16#01#,
-      P2_OFF => 16#05#,
-      P3_OFF => 16#09#)
+      P1_OFF => 16#00#,
+      P2_OFF => 16#04#,
+      P3_OFF => 16#08#)
     port map (
       ACK_O     => MCC_ACK (2),
       CLK_I     => CLK_I,
@@ -217,6 +239,47 @@ begin
       LUT_DAT_I => LUT_DAT_I,
       LUT_STB_O => LUT_STB_O);
 
+  vector_scale_sequencer : entity work.sequencer
+    generic map (
+      IRF_ADR_W => IRF_ADR_W,
+      P_BASE    => P_BASE,
+      P_SIZE    => P_SIZE)
+    port map (
+      ACK_O        => MCC_ACK (3),
+      CLK_I        => CLK_I,
+      RST_I        => RST_I,
+      STB_I        => MCC_STB (3),
+      IRF_ADR_O    => SCALE_IRF_ADR_O,
+      SL_ACK_I     => SCALE_SL_ACK_O,
+      SL_IRF_ADR_I => SCALE_SL_IRF_ADR_O,
+      SL_STB_O     => SCALE_SL_STB_I,
+      SL_MUX_CODE  => open);
+  
+  vector_scale_1 : entity work.vector_scale
+    generic map (
+      IRF_ADR_W  => IRF_ADR_W,
+      BASE       => 0,
+      SCALE_OFF  => 5,
+      PHASE_BASE => P_BASE,
+      VECTOR_OFF => 0,
+      SCALED_OFF => 1,
+      VECTOR_W   => LUT_DAT_W)
+    port map (
+      ACK_O     => SCALE_SL_ACK_O,
+      CLK_I     => CLK_I,
+      RST_I     => RST_I,
+      STB_I     => SCALE_SL_STB_I,
+      MUL_A     => MUL_A,
+      MUL_B     => MUL_B,
+      MUL_PROD  => MUL_PROD,
+      IRF_ACK_I => IRF_ACK_I,
+      IRF_ADR_O => SCALE_SL_IRF_ADR_O,
+      IRF_DAT_I => IRF_DAT_I,
+      IRF_DAT_O => SCALE_IRF_DAT_O,
+      IRF_STB_O => SCALE_IRF_STB_O,
+      IRF_WE_O  => SCALE_IRF_WE_O);
+
+  
   pwm_dump_sequencer : entity work.sequencer
     generic map (
       IRF_ADR_W => IRF_ADR_W,