Early initialization of all relevant signals.

[fpga/pwm.git] / pwm_dump.vhd

diff --git a/pwm_dump.vhd b/pwm_dump.vhd
index bf6b8c632bfd96b63ffa30e6be284013f3613494..8d942a1faa48618f8a7d32644950200a7455282f 100644 (file)
--- a/pwm_dump.vhd
+++ b/pwm_dump.vhd
@@ -19,7 +19,7 @@ entity pwm_dump is
     STB_I     : in  std_logic;
     -- PWM interface
     PWM_DAT_O : out std_logic_vector (PWM_W-1 downto 0);
-    PWM_STB_O : out std_logic;
+    PWM_STB_O : out std_logic := '0';
     -- Shared dual-port memory
     IRF_ACK_I : in  std_logic;
     IRF_ADR_O : out std_logic_vector (IRF_ADR_W-1 downto 0);
@@ -36,9 +36,9 @@ architecture behavioral of pwm_dump is
 
   constant PWM_ADR : irf_adr_t :=  conv_std_logic_vector(P_BASE + PWM_OFF, IRF_ADR_W);
   
-  signal state : state_t;
+  signal state : state_t := ready;
 
-  signal INNER_ACK : std_logic;
+  signal INNER_ACK : std_logic := '0';
   
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