Early initialization of all relevant signals.

[fpga/pwm.git] / vector_scale.vhd

diff --git a/vector_scale.vhd b/vector_scale.vhd
index 05fb7694a115736ad044470899122440db7435d9..d1c6306c34e731cf115cf379aeae805f03931e3e 100644 (file)
--- a/vector_scale.vhd
+++ b/vector_scale.vhd
@@ -29,8 +29,8 @@ entity vector_scale is
     IRF_ADR_O : out std_logic_vector (IRF_ADR_W-1 downto 0);
     IRF_DAT_I : in  std_logic_vector (15 downto 0);
     IRF_DAT_O : out std_logic_vector (15 downto 0);
-    IRF_STB_O : out std_logic;
-    IRF_WE_O  : out std_logic);
+    IRF_STB_O : out std_logic := '0';
+    IRF_WE_O  : out std_logic := '0');
 end entity vector_scale;
 
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@@ -46,9 +46,9 @@ architecture behavioral of vector_scale is
   constant VECTOR_ADR : irf_adr_t := conv_std_logic_vector(PHASE_BASE + VECTOR_OFF, IRF_ADR_W);
   constant SCALED_ADR : irf_adr_t := conv_std_logic_vector(PHASE_BASE + SCALED_OFF, IRF_ADR_W);
   
-  signal state : state_t;
+  signal state : state_t := ready;
 
-  signal INNER_ACK : std_logic;
+  signal INNER_ACK : std_logic := '0';
 
 
   function twos_to_biased (twos : std_logic_vector) return std_logic_vector is