UART baud-rate constant moved to generics parameters.

diff --git a/vhdl/mlite_pack.vhd b/vhdl/mlite_pack.vhd
index f6e37a60b5dc057679e63e44749a89f9a882f850..b10ede0f24067daf3789378ead3cb19b3287717d 100644 (file)
--- a/vhdl/mlite_pack.vhd
+++ b/vhdl/mlite_pack.vhd
@@ -393,7 +393,8 @@ package mlite_pack is
    end component; --ram
    
    component uart
-      generic(log_file : string := "UNUSED");
+      generic(log_file  : string := "UNUSED";
+              prescaler : integer := 434);
       port(clk          : in std_logic;
            reset        : in std_logic;
            enable_read  : in std_logic;

diff --git a/vhdl/plasma.vhd b/vhdl/plasma.vhd
index 130576ba62a33a7aeef6b0ff4aff2ab0782c465b..83e6459ec4bc63f5a98b95724396ae3a23e5c61a 100644 (file)
--- a/vhdl/plasma.vhd
+++ b/vhdl/plasma.vhd
@@ -40,7 +40,8 @@ entity plasma is
    generic(memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM";
            log_file    : string := "UNUSED";
            ethernet    : std_logic := '0';
-           use_cache   : std_logic := '0');
+           use_cache   : std_logic := '0';
+           uart_prescaler : integer := 434);
    port(clk          : in std_logic;
         reset        : in std_logic;
 
@@ -264,7 +265,9 @@ begin  --architecture
          data_read         => ram_data_r);
 
    u3_uart: uart
-      generic map (log_file => log_file)
+      generic map (
+        log_file => log_file,
+        prescaler => uart_prescaler)
       port map(
          clk          => clk,
          reset        => reset,

diff --git a/vhdl/uart.vhd b/vhdl/uart.vhd
index 5f576feceac0130ed46d34455faec26297aeb4a5..f9f15d01fcadac61652d3979b3ab13e6fa8b0b73 100644 (file)
--- a/vhdl/uart.vhd
+++ b/vhdl/uart.vhd
@@ -8,6 +8,10 @@
 --    Software 'as is' without warranty.  Author liable for nothing.
 -- DESCRIPTION:
 --    Implements the UART.
+--
+---------------------------------------------------------------------
+-- Baud-rate is determined by the "prescaler" generic parameter.
+--  <prescaler> = (<clk_freq> / <baud-rate>) - 1
 ---------------------------------------------------------------------
 library ieee;
 use ieee.std_logic_1164.all;
@@ -19,7 +23,9 @@ use std.textio.all;
 use work.mlite_pack.all;
 
 entity uart is
-   generic(log_file : string := "UNUSED");
+   generic(
+     log_file  : string := "UNUSED";
+     prescaler : integer := 434);
    port(clk          : in std_logic;
         reset        : in std_logic;
         enable_read  : in std_logic;
@@ -46,17 +52,20 @@ architecture logic of uart is
 
 begin
 
+  assert prescaler < 1024 
+    report "Prescale value must be lower then 1024." 
+    severity failure;
+  
+  
 uart_proc: process(clk, reset, enable_read, enable_write, data_in,
                    data_write_reg, bits_write_reg, delay_write_reg, 
                    data_read_reg, bits_read_reg, delay_read_reg,
                    data_save_reg, read_value_reg, uart_read2,
                    busy_write_sig, uart_read)
-   constant COUNT_VALUE : std_logic_vector(9 downto 0) :=
---      "0100011110";  --33MHz/2/57600Hz = 0x11e
---      "1101100100";  --50MHz/57600Hz = 0x364
-      "0110110010";  --25MHz/57600Hz = 0x1b2 -- Plasma IF uses div2
---      "0011011001";  --12.5MHz/57600Hz = 0xd9
---      "0000000100";  --for debug (shorten read_value_reg)
+
+   constant COUNT_VALUE : std_logic_vector(9 downto 0) := 
+     CONV_STD_LOGIC_VECTOR(prescaler, 10);
+
 begin
    uart_read2 <= read_value_reg(read_value_reg'length - 1);