]> rtime.felk.cvut.cz Git - fpga/openmsp430.git/tree - top/top_8_32_mul/
New top module with external data bus
[fpga/openmsp430.git] / top / top_8_32_mul /
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-rw-r--r-- 779 README
-rw-r--r-- 1500 openMSP430_8_32_mul.bmm
-rw-r--r-- 1139 openMSP430_8_32_mul.prj
-rw-r--r-- 8242 openMSP430_8_32_mul.vhd
-rw-r--r-- 11926 openMSP430_defines.v