--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+
+entity openMSP430_8_32_mul is
+ port (
+ -- Clocks and reset (low active)
+ dco_clk : in std_logic;
+ lfxt_clk : in std_logic;
+ reset_n : in std_logic;
+ -- RS232 interface
+ rxd : in std_logic;
+ txd : out std_logic;
+ -- Periphery interface
+ per_addr : out std_logic_vector (7 downto 0);
+ per_din : out std_logic_vector (15 downto 0);
+ per_dout : in std_logic_vector (15 downto 0);
+ per_wen : out std_logic_vector (1 downto 0);
+ per_en : out std_logic;
+ nmi : in std_logic;
+ irq : in std_logic_vector (13 downto 0);
+ irq_acc : out std_logic_vector (13 downto 0);
+ aclk_en : out std_logic;
+ smclk_en : out std_logic;
+ mclk : out std_logic;
+ puc : out std_logic);
+end entity openMSP430_8_32_mul;
+
+--------------------------------------------------------------------------------
+
+architecture rtl of openMSP430_8_32_mul is
+
+ component openMSP430 is
+ port(
+ aclk_en : out std_logic; -- ACLK enable
+ dbg_freeze : out std_logic; -- Freeze peripherals
+ dbg_uart_txd : out std_logic; -- Debug interface: UART TXD
+ dmem_addr : out std_logic_vector; -- Data Memory address
+ dmem_cen : out std_logic; -- Data Memory chip enable (low active)
+ dmem_din : out std_logic_vector (15 downto 0); -- Data Memory data input
+ dmem_wen : out std_logic_vector (1 downto 0); -- Data Memory write enable (low active)
+ irq_acc : out std_logic_vector (13 downto 0); -- Interrupt request accepted (one-hot signal)
+ mclk : out std_logic; -- Main system clock
+ per_addr : out std_logic_vector (7 downto 0); -- Peripheral address
+ per_din : out std_logic_vector (15 downto 0); -- Peripheral data input
+ per_wen : out std_logic_vector (1 downto 0); -- Peripheral write enable (high active)
+ per_en : out std_logic; -- Peripheral enable (high active)
+ pmem_addr : out std_logic_vector; -- Program Memory address
+ pmem_cen : out std_logic; -- Program Memory chip enable (low active)
+ pmem_din : out std_logic_vector (15 downto 0); -- Program Memory data input (optional)
+ pmem_wen : out std_logic_vector (1 downto 0); -- Program Memory write enable (low active) (optional)
+ puc : out std_logic; -- Main system reset
+ smclk_en : out std_logic; -- SMCLK enable
+
+ dbg_uart_rxd : in std_logic; -- Debug interface: UART RXD
+ dco_clk : in std_logic; -- Fast oscillator (fast clock)
+ dmem_dout : in std_logic_vector (15 downto 0); -- Data Memory data output
+ irq : in std_logic_vector (13 downto 0); -- Maskable interrupts
+ lfxt_clk : in std_logic; -- Low frequency oscillator (typ 32kHz)
+ nmi : in std_logic; -- Non-maskable interrupt (asynchronous)
+ per_dout : in std_logic_vector (15 downto 0); -- Peripheral data output
+ pmem_dout : in std_logic_vector (15 downto 0); -- Program Memory data output
+ reset_n : in std_logic -- Reset Pin (low active)
+ );
+ end component;
+
+
+
+ signal dmem_addr : std_logic_vector (11 downto 0);
+ signal dmem_cen : std_logic;
+ signal dmem_din : std_logic_vector (15 downto 0);
+ signal dmem_dout : std_logic_vector (15 downto 0);
+ signal dmem_wen : std_logic_vector (1 downto 0);
+
+ signal pmem_addr : std_logic_vector (13 downto 0);
+ signal pmem_cen : std_logic;
+ signal pmem_din : std_logic_vector (15 downto 0);
+ signal pmem_dout : std_logic_vector (15 downto 0);
+ signal pmem_wen : std_logic_vector (1 downto 0);
+
+ -- Inner signals used to connect built in components
+ signal inner_mclk : std_logic;
+ signal inner_puc : std_logic;
+
+ signal inner_per_addr : std_logic_vector (7 downto 0);
+ signal inner_per_din : std_logic_vector (15 downto 0);
+ signal inner_per_dout : std_logic_vector (15 downto 0);
+ signal inner_per_wen : std_logic_vector (1 downto 0);
+ signal inner_per_en : std_logic;
+
+ signal inner_irq_acc : std_logic_vector (13 downto 0);
+ signal inner_irq : std_logic_vector (13 downto 0);
+
+ -- RS232 interface
+ signal uart_dout : std_logic_vector (15 downto 0);
+ signal uart_irq : std_logic;
+
+--------------------------------------------------------------------------------
+
+begin
+
+ -- Soft core
+ openMSP430_0 : openMSP430
+ port map (
+ aclk_en => aclk_en,
+ dbg_freeze => open,
+ dbg_uart_txd => open,
+ dmem_addr => dmem_addr,
+ dmem_cen => dmem_cen,
+ dmem_din => dmem_din,
+ dmem_wen => dmem_wen,
+ irq_acc => inner_irq_acc,
+ mclk => inner_mclk,
+ per_addr => inner_per_addr,
+ per_din => inner_per_din,
+ per_wen => inner_per_wen,
+ per_en => inner_per_en,
+ pmem_addr => pmem_addr,
+ pmem_cen => pmem_cen,
+ pmem_din => open,
+ pmem_wen => open,
+ puc => inner_puc,
+ smclk_en => smclk_en,
+
+ dbg_uart_rxd => '0',
+ dco_clk => dco_clk,
+ dmem_dout => dmem_dout,
+ irq => inner_irq,
+ lfxt_clk => lfxt_clk,
+ nmi => nmi,
+ per_dout => inner_per_dout,
+ pmem_dout => pmem_dout,
+ reset_n => reset_n);
+
+
+ -- Data memories
+ d_ram_hi : entity work.ram_generic
+ generic map (
+ BRAM_TYPE => "RAMB16_S4",
+ SIZE => 4*1024,
+ ADDR_WIDTH => 12,
+ DATA_WIDTH => 8,
+ NEG_EN => true,
+ NEG_WE => true)
+ port map (
+ clk => inner_mclk,
+ addr => dmem_addr,
+ en => dmem_cen,
+ we => dmem_wen (1),
+ din => dmem_din (15 downto 8),
+ dout => dmem_dout (15 downto 8));
+
+ d_ram_lo : entity work.ram_generic
+ generic map (
+ BRAM_TYPE => "RAMB16_S4",
+ SIZE => 4*1024,
+ ADDR_WIDTH => 12,
+ DATA_WIDTH => 8,
+ NEG_EN => true,
+ NEG_WE => true)
+ port map (
+ clk => inner_mclk,
+ addr => dmem_addr,
+ en => dmem_cen,
+ we => dmem_wen (0),
+ din => dmem_din (7 downto 0),
+ dout => dmem_dout (7 downto 0));
+
+ -- Program memories
+ p_ram_hi : entity work.ram_generic
+ generic map (
+ BRAM_TYPE => "RAMB16_S2",
+ SIZE => 16*1024,
+ ADDR_WIDTH => 14,
+ DATA_WIDTH => 8,
+ NEG_EN => true)
+ port map (
+ clk => inner_mclk,
+ addr => pmem_addr,
+ en => pmem_cen,
+ we => pmem_wen (1),
+ din => pmem_din (15 downto 8),
+ dout => pmem_dout (15 downto 8));
+
+ p_ram_lo : entity work.ram_generic
+ generic map (
+ BRAM_TYPE => "RAMB16_S2",
+ SIZE => 16*1024,
+ ADDR_WIDTH => 14,
+ NEG_EN => true)
+ port map (
+ clk => inner_mclk,
+ addr => pmem_addr,
+ en => pmem_cen,
+ we => pmem_wen (0),
+ din => pmem_din (7 downto 0),
+ dout => pmem_dout (7 downto 0));
+
+
+ -- RS232 periphery
+ uart_o : entity work.uart
+ port map (
+ mclk => inner_mclk,
+ per_addr => inner_per_addr,
+ per_din => inner_per_din,
+ per_en => inner_per_en,
+ per_wen => inner_per_wen,
+ puc => inner_puc,
+ per_irq_acc => '0',
+ per_irq => uart_irq,
+ per_dout => uart_dout,
+ rxd => rxd,
+ txd => txd);
+
+--------------------------------------------------------------------------------
+
+ inner_per_dout <= uart_dout or per_dout;
+
+ inner_irq <= irq;
+ --inner_irq (6) <= uart_irq;
+
+ irq_acc <= inner_irq_acc;
+ mclk <= inner_mclk;
+ per_addr <= inner_per_addr;
+ per_din <= inner_per_din;
+ per_wen <= inner_per_wen;
+ per_en <= inner_per_en;
+
+ puc <= inner_puc;
+
+end rtl;
+
projects / fpga / openmsp430.git / blobdiff