]> rtime.felk.cvut.cz Git - fpga/openmsp430.git/blobdiff - top/top_8_32_mul/openMSP430_8_32_mul.bmm
Added ready to use openMSP430 entity.
[fpga/openmsp430.git] / top / top_8_32_mul / openMSP430_8_32_mul.bmm
diff --git a/top/top_8_32_mul/openMSP430_8_32_mul.bmm b/top/top_8_32_mul/openMSP430_8_32_mul.bmm
new file mode 100644 (file)
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+// ram_generic: 2x16kB, BRAM_TYPE=RAMB16_S2
+ADDRESS_SPACE blockrom RAMB16 [0x8000:0xffff]
+  BUS_BLOCK
+      <path>/p_ram_lo/BLOCKS[0].RAMB16_S2.B[3].BRAM [7:6];
+      <path>/p_ram_lo/BLOCKS[0].RAMB16_S2.B[2].BRAM [5:4];
+      <path>/p_ram_lo/BLOCKS[0].RAMB16_S2.B[1].BRAM [3:2];
+      <path>/p_ram_lo/BLOCKS[0].RAMB16_S2.B[0].BRAM [1:0];
+      <path>/p_ram_hi/BLOCKS[0].RAMB16_S2.B[3].BRAM [15:14];
+      <path>/p_ram_hi/BLOCKS[0].RAMB16_S2.B[2].BRAM [13:12];
+      <path>/p_ram_hi/BLOCKS[0].RAMB16_S2.B[1].BRAM [11:10];
+      <path>/p_ram_hi/BLOCKS[0].RAMB16_S2.B[0].BRAM [9:8];
+  END_BUS_BLOCK;
+  BUS_BLOCK
+      <path>/p_ram_lo/BLOCKS[1].RAMB16_S2.B[3].BRAM [7:6];
+      <path>/p_ram_lo/BLOCKS[1].RAMB16_S2.B[2].BRAM [5:4];
+      <path>/p_ram_lo/BLOCKS[1].RAMB16_S2.B[1].BRAM [3:2];
+      <path>/p_ram_lo/BLOCKS[1].RAMB16_S2.B[0].BRAM [1:0];
+      <path>/p_ram_hi/BLOCKS[1].RAMB16_S2.B[3].BRAM [15:14];
+      <path>/p_ram_hi/BLOCKS[1].RAMB16_S2.B[2].BRAM [13:12];
+      <path>/p_ram_hi/BLOCKS[1].RAMB16_S2.B[1].BRAM [11:10];
+      <path>/p_ram_hi/BLOCKS[1].RAMB16_S2.B[0].BRAM [9:8];
+  END_BUS_BLOCK;
+END_ADDRESS_SPACE;
+
+
+// ram_generic: 2x4kB, BRAM_TYPE=RAMB_S4
+ADDRESS_SPACE blockram RAMB16 [0x0200:0x21ff]
+  BUS_BLOCK
+      <path>/d_ram_lo/BLOCKS[0].RAMB16_S4.B[1].BRAM [7:4];
+      <path>/d_ram_lo/BLOCKS[0].RAMB16_S4.B[0].BRAM [3:0];
+      <path>/d_ram_hi/BLOCKS[0].RAMB16_S4.B[1].BRAM [15:12];
+      <path>/d_ram_hi/BLOCKS[0].RAMB16_S4.B[0].BRAM [11:8];
+  END_BUS_BLOCK;
+END_ADDRESS_SPACE;
+