-- mem pipeline register
MEM_REG_i : IN MEM_REG_Type;
MEM_REG_o : OUT MEM_REG_Type;
- -- FSL to mem data delay register(s)
- FSL_S2MEM_REG_i : IN FSL_S2MEM_Type;
- FSL_S2MEM_REG_o : OUT FSL_S2MEM_Type;
-- decode control i/o
ID2CTRL_i : IN ID2CTRL_Type;
INT_CTRL_o : OUT INT_CTRL_Type;
MSR_o : OUT MSR_Type;
-- miscellaneous
MEM2CTRL_i : IN MEM2CTRL_Type;
- FSL_nStall_i : IN STD_LOGIC;
done_o : OUT STD_LOGIC
);
END ENTITY core_ctrl;
SIGNAL setup_int_r : STD_LOGIC;
SIGNAL int_busy_r : STD_LOGIC;
- SIGNAL S_Data_r : STD_LOGIC_VECTOR (31 DOWNTO 0);
- SIGNAL S_Data_2r : STD_LOGIC_VECTOR (31 DOWNTO 0);
-
BEGIN
pc_ctrl_o <= NOT rst_r;
imem_addr_o <= IF2ID_REG_i.program_counter;
-- clock/wait control lines
- clken_s <= (MEM2CTRL_i.clken AND FSL_nStall_i) OR rst_i;
+ clken_s <= MEM2CTRL_i.clken OR rst_i;
clken_pipe_s <= clken_s AND (NOT HAZARD_WRB_i.hazard);
imem_clken_o <= clken_pipe_s;
gprf_clken_o <= clken_s;
INT_CTRL_o.setup_int <= setup_int_r;
INT_CTRL_o.rti_target <= ID2EX_REG_r.program_counter;
INT_CTRL_o.int_busy <= int_busy_r;
- --
- FSL_S2MEM_REG_o.S_Data <= S_Data_2r;
regd_proc:
PROCESS ( clk_i, rst_i, halt_i,
flush_ID2EX_s, flush_EX2MEM_s, HAZARD_WRB_i,
MEM_REG_i, ID2CTRL_i, int_i, MSR_i,
int_busy_r, delayBit_r, IMM_LOCK_i, ID2EX_REG_i, ID2EX_REG_r,
- EX2IF_REG_i, EX_WRB_i, S_Data_r, FSL_S2MEM_REG_i, EX2MEM_REG_i )
+ EX2IF_REG_i, EX_WRB_i, EX2MEM_REG_i )
-- some local procedures
PROCEDURE lp_rst_IF2ID_REG IS
ID2EX_REG_r.mem_Action <= NO_MEM;
ID2EX_REG_r.transfer_Size <= WORD;
ID2EX_REG_r.wrb_Action <= NO_WRB;
- ID2EX_REG_r.FSL_Test <= '1';
- ID2EX_REG_r.FSL_Non_blocking <= '1';
- ID2EX_REG_r.FSL_Control <= '0';
- ID2EX_REG_r.FSL_Atomic <= '0';
END PROCEDURE;
PROCEDURE lp_rst_EX2IF_REG IS
EX2MEM_REG_o.wrix_rD <= (OTHERS => '0');
END PROCEDURE;
- PROCEDURE lp_rst_FSL2MEM_REG IS
- BEGIN
- S_Data_r <= (OTHERS => '0');
- S_Data_2r <= (OTHERS => '0');
- END PROCEDURE;
-
PROCEDURE lp_rst_IMM_LOCK IS
BEGIN
IMM_LOCK_r.locked <= '0';
BEGIN
MSR_o.IE <= '0';
MSR_o.C <= '0';
- MSR_o.FSL <= '0';
END PROCEDURE;
PROCEDURE lp_rst_EX_WRB IS
lp_rst_MSR;
lp_rst_HAZARD_WRB;
lp_rst_MEM_REG;
- lp_rst_FSL2MEM_REG;
delayBit_r <= '0';
flush_ID2EX_r <= '0';
setup_int_r <= '0';
EX2IF_REG_r <= EX2IF_REG_i;
delayBit_2r <= delayBit_r;
EX_WRB_o <= EX_WRB_i;
- S_Data_2r <= S_Data_r;
- S_Data_r <= FSL_S2MEM_REG_i.S_Data;
END IF;
IF (clken_s = '1') THEN
-- next test to prevent a flush from disrupting
INT_CTRL_i : IN INT_CTRL_Type;
ID2CTRL_o : OUT ID2CTRL_Type;
--
- noLiteOpc_s : OUT STD_LOGIC
+ noLiteOpc_o : OUT STD_LOGIC
);
END ENTITY decode;
VARIABLE rA_v : STD_LOGIC_VECTOR ( 4 DOWNTO 0);
VARIABLE rB_v : STD_LOGIC_VECTOR ( 4 DOWNTO 0);
VARIABLE IMM16_v : STD_LOGIC_VECTOR (15 DOWNTO 0);
- VARIABLE FSL_Mode_v : STD_LOGIC_VECTOR ( 4 DOWNTO 0);
VARIABLE code_x26_v : STD_LOGIC_VECTOR ( 2 DOWNTO 0);
VARIABLE IMM_Lock_v : STD_LOGIC;
VARIABLE alu_Action_v : ALU_ACTION_Type;
mem_Action_v := NO_MEM;
transfer_Size_v := WORD;
wrb_Action_v := WRB_EX;
- FSL_Mode_v := "01010";
-- for decoding SEXT16, SEXT8, SRC, SRC or SRL
code_x26_v := instruction_v(6) & instruction_v(5) & instruction_v(0);
int_busy_v := INT_CTRL_i.int_busy;
-- for debugging purposes
- noLiteOpc_s <= '0';
+ noLiteOpc_o <= '0';
IF (INT_CTRL_i.setup_int = '1') THEN
END IF;
END IF;
- WHEN "01" => -- MUL / BS / FSL
+ WHEN "01" => -- MUL / BS
CASE opcIx_v (2 DOWNTO 0) IS
WHEN "000" => -- MUL
IF (USE_HW_MUL_g = TRUE) THEN
alu_Action_v := A_MUL;
ELSE
- noLiteOpc_s <= '1';
+ noLiteOpc_o <= '1';
END IF;
WHEN "001" => -- BS
IF (USE_BARREL_g = TRUE) THEN
END IF;
END IF;
ELSE
- noLiteOpc_s <= '1';
+ noLiteOpc_o <= '1';
END IF;
- WHEN "011" => -- FSL
- IF (opcIx_v(3) = '0') THEN
- FSL_Mode_v := instruction_v(10 DOWNTO 6);
- ELSE
- FSL_Mode_v := instruction_v(15 DOWNTO 11);
- END IF;
- IF (FSL_Mode_v(4) = '0') THEN
- alu_Action_v := A_FSL_GET;
- wrb_Action_v := WRB_FSL;
- ELSE
- alu_Action_v := A_FSL_PUT;
- wrb_Action_v := NO_WRB;
- END IF;
- msr_Action_v := UPDATE_CARRY;
WHEN OTHERS =>
- noLiteOpc_s <= '1';
+ noLiteOpc_o <= '1';
END CASE;
WHEN "10" =>
WHEN "10" => -- SRL
alu_Cin_v := CIN_ZERO;
WHEN OTHERS =>
- noLiteOpc_s <= '1';
+ noLiteOpc_o <= '1';
END CASE;
alu_Action_v := A_SHIFT;
msr_Action_v := UPDATE_CARRY;
WHEN "111" => -- SEXT16
alu_Action_v := A_SEXT16;
WHEN OTHERS =>
- noLiteOpc_s <= '1';
+ noLiteOpc_o <= '1';
END CASE;
ELSIF (opcIx_v (3 DOWNTO 0) = "1100") THEN -- IMM
IMM_Lock_v := '1';
-- WHEN "10010" => -- RTBD
-- WHEN "10100" => -- RTED
WHEN OTHERS =>
- noLiteOpc_s <= '1';
+ noLiteOpc_o <= '1';
END CASE;
alu_Action_v := A_ADD;
branch_Action_v := BR;
alu_Action_v := A_MTS;
wrb_Action_v := NO_WRB;
WHEN OTHERS =>
- noLiteOpc_s <= '1';
+ noLiteOpc_o <= '1';
END CASE;
rB_v := (OTHERS => '0'); -- in order to prevent occasional hazards (r16, r24)
ELSE
WHEN "0101" => -- BGE
branch_Action_v := BGE;
WHEN OTHERS =>
- noLiteOpc_s <= '1';
+ noLiteOpc_o <= '1';
END CASE;
alu_Action_v := A_ADD;
alu_Op1_v := ALU_IN_PC;
delayBit_v := rD_v(4);
wrb_Action_v := NO_WRB; -- evaluate and update/overwrite in exeq
WHEN OTHERS =>
- noLiteOpc_s <= '1';
+ noLiteOpc_o <= '1';
END CASE;
END IF;
WHEN "01" => transfer_Size_v := HALFWORD;
WHEN "10" => transfer_Size_v := WORD;
WHEN OTHERS =>
- noLiteOpc_s <= '1';
+ noLiteOpc_o <= '1';
END CASE;
IF (opcIx_v(2) = '0') THEN
mem_Action_v := RD_MEM;
END IF;
WHEN OTHERS =>
- noLiteOpc_s <= '1';
+ noLiteOpc_o <= '1';
END CASE;
ID2EX_o.mem_Action <= mem_Action_v;
ID2EX_o.transfer_Size <= transfer_Size_v;
ID2EX_o.wrb_Action <= wrb_Action_v;
- ID2EX_o.FSL_Non_blocking <= FSL_Mode_v(3);
- ID2EX_o.FSL_Control <= FSL_Mode_v(2);
- ID2EX_o.FSL_Test <= FSL_Mode_v(1);
- ID2EX_o.FSL_Atomic <= FSL_Mode_v(0);
--
ID2CTRL_o.delayBit <= delayBit_v;
ID2CTRL_o.int_busy <= int_busy_v;
-- Faculty EEMCS, Department ME&CE, Circuits and Systems
-- Date: September, 2010
--
--- Modified: December, 2010: FSL added (Huib)
+-- Modified: Septemper, 2013: FSL scratched (Meloun)
+-- December, 2010: FSL added (Huib)
-- June, 2011: added code for MUL and BARREL (Huib)
-- Adapted to work with separate fsl_M-
-- and fsl_S selectors and automatic
MSR_i : IN MSR_Type;
MSR_o : OUT MSR_Type;
--
- EX2MEM_o : OUT EX2MEM_Type;
- --
- exq_branch_i : IN STD_LOGIC;
- --
- FSL_M2EX_i : IN FSL_M2EX_Type;
- EX2FSL_M_o : OUT EX2FSL_M_Type;
- --
- FSL_S2EX_i : IN FSL_S2EX_Type;
- EX2FSL_S_o : OUT EX2FSL_S_Type;
- --
- FSL_nStall_o : OUT STD_LOGIC
+ EX2MEM_o : OUT EX2MEM_Type
);
END ENTITY exeq;
p_exeq:
PROCESS (ID2EX_i, GPRF2EX_i, EX_WRB_i, MEM_WRB_i,
- IMM_LOCK_i, MSR_i, exq_branch_i, FSL_M2EX_i, FSL_S2EX_i, HAZARD_WRB_i)
+ IMM_LOCK_i, MSR_i, HAZARD_WRB_i)
-- function needed by BSLL (only if USE_BARREL_g = TRUE)
FUNCTION reverse_bits ( word32 : STD_LOGIC_VECTOR (31 DOWNTO 0) )
VARIABLE data_rX_v : STD_LOGIC_VECTOR (31 DOWNTO 0);
VARIABLE do_branch_v : STD_LOGIC;
VARIABLE byte_Enable_v : STD_LOGIC_VECTOR ( 3 DOWNTO 0);
- VARIABLE FSLx_M_v : STD_LOGIC_VECTOR ( 3 DOWNTO 0);
- VARIABLE FSLx_S_v : STD_LOGIC_VECTOR ( 3 DOWNTO 0);
- VARIABLE FSL_Read_v : STD_LOGIC;
- VARIABLE FSL_Write_v : STD_LOGIC;
- VARIABLE FSL_nStall_v : STD_LOGIC;
- VARIABLE FSL_Atomic_v : STD_LOGIC;
- VARIABLE FSL_Error_v : STD_LOGIC;
VARIABLE tmp64_v : STD_LOGIC_VECTOR (63 DOWNTO 0);
VARIABLE padVec_v : STD_LOGIC_VECTOR (15 DOWNTO 0);
carry_o_v := '0';
do_branch_v := '0';
byte_Enable_v := "0000";
- FSLx_M_v := (OTHERS => '0');
- FSLx_S_v := (OTHERS => '0');
- FSL_Read_v := '0';
- FSL_Write_v := '0';
- FSL_nStall_v := '1';
- FSL_Atomic_v := '0';
- FSL_Error_v := MSR_i.FSL;
-- create some helper variables
IF (ID2EX_i.rdix_rA = EX_WRB_i.wrix_rD) THEN
result_v := C_16_ONES & in1_v(15 DOWNTO 0);
END IF;
WHEN A_MFS =>
- result_v := MSR_i.C & C_24_ZEROS & "00" & MSR_i.FSL & '0' & MSR_i.C & MSR_i.IE & '0';
+ result_v := MSR_i.C & C_24_ZEROS & "0000" & MSR_i.C & MSR_i.IE & '0';
WHEN A_MTS =>
MSR_o.IE <= data_Ra_v(1);
MSR_o.C <= data_Ra_v(2);
- MSR_o.FSL <= data_Ra_v(4);
WHEN A_MUL =>
IF (USE_HW_MUL_g = TRUE) THEN
tmp64_v := STD_LOGIC_VECTOR( UNSIGNED(in1_v) * UNSIGNED(in2_v) );
result_v := reverse_bits (result_v);
END IF;
END IF; -- (USE_BARREL_g = TRUE)
- WHEN A_FSL_GET =>
- -- to be examined here, since FSL instruction treated differently than
- -- e.g. memory read/writes, i.e. MSR-C and -FSL_E bit have to be set
- -- depending on input values (exq_branch_i equals EX2IF_r.take_branch, i.e.
- -- a one clock cycle delayed EX2IF_o.take_branch).
- IF (exq_branch_i = '0') THEN
- FSLx_S_v := in2_v(3 DOWNTO 0);
- FSL_Read_v := FSL_S2EX_i.S_Exists AND (NOT hazard_v);
- FSL_Atomic_v := ID2EX_i.FSL_Atomic;
- IF (ID2EX_i.FSL_Non_blocking = '0') THEN
- FSL_nStall_v := FSL_Read_v;
- ELSE
- carry_o_v := NOT FSL_Read_v;
- IF ((FSL_Read_v = '1') AND
- (ID2EX_i.FSL_Control /= FSL_S2EX_i.S_Control)) THEN
- FSL_Error_v := '1';
- ELSE
- FSL_Error_v := '0';
- END IF;
- END IF;
- END IF;
- WHEN A_FSL_PUT =>
- FSLx_M_v := in2_v(3 DOWNTO 0);
- FSL_Write_v := NOT (FSL_M2EX_i.M_Full OR hazard_v);
- FSL_Atomic_v := ID2EX_i.FSL_Atomic;
- IF (ID2EX_i.FSL_Non_blocking = '0') THEN
- FSL_nStall_v := FSL_Write_v;
- ELSE
- carry_o_v := FSL_M2EX_i.M_Full;
- END IF;
WHEN OTHERS =>
NULL;
END CASE;
-- update MSR[IE], MSR[C] and/or MSR[FSL_Error] if needed
IF (ID2EX_i.alu_Action /= A_MTS) THEN
- MSR_o.FSL <= FSL_Error_v;
- MSR_o.IE <= MSR_i.IE AND (NOT FSL_Atomic_v);
+ MSR_o.IE <= MSR_i.IE;
IF (ID2EX_i.msr_Action = UPDATE_CARRY) THEN
MSR_o.C <= carry_o_v;
ELSE
EX_WRB_o.wrix_rD <= ID2EX_i.curr_rD;
EX_WRB_o.data_rD <= result_v;
--
- EX2FSL_M_o.FSLx_M <= FSLx_M_v;
- EX2FSL_M_o.M_Write <= FSL_Write_v;
- EX2FSL_M_o.M_Data <= data_rA_v;
- EX2FSL_M_o.M_Control <= ID2EX_i.FSL_Control;
- --
- EX2FSL_S_o.FSLx_S <= FSLx_S_v;
- EX2FSL_S_o.S_Read <= FSL_Read_v;
- --
- FSL_nStall_o <= FSL_nStall_v;
- --
HAZARD_WRB_o.hazard <= hazard_v;
HAZARD_WRB_o.save_rX <= save_rX_v;
HAZARD_WRB_o.data_rX <= data_rX_v;
-- Faculty EEMCS, Department ME&CE, Circuits and Systems
-- Date: September, 2010
--
--- Modified: June, 2011: ALU_ACTION_Type extended to incorporate
+-- Modified: September, 2013: Removed FSL
+-- June, 2011: ALU_ACTION_Type extended to incorporate
-- MUL and BS instructions (Huib)
-- Adapted to work with separate fsl_M-
-- and fsl_S selectors and automatic
TYPE ALU_ACTION_Type IS (A_NOP, A_ADD, A_CMP, A_CMPU, A_OR, A_AND, A_XOR,
A_SHIFT, A_SEXT8, A_SEXT16, A_MFS, A_MTS,
- A_MUL, A_BSLL, A_BSRL, A_BSRA,
- A_FSL_GET, A_FSL_PUT);
+ A_MUL, A_BSLL, A_BSRL, A_BSRA);
TYPE ALU_IN1_Type IS (ALU_IN_REGA, ALU_IN_NOT_REGA, ALU_IN_PC, ALU_IN_ZERO);
TYPE ALU_IN2_Type IS (ALU_IN_REGB, ALU_IN_NOT_REGB, ALU_IN_IMM, ALU_IN_NOT_IMM);
TYPE ALU_CIN_Type IS (CIN_ZERO, CIN_ONE, FROM_MSR, FROM_IN1);
TYPE MSR_ACTION_Type IS (UPDATE_CARRY, KEEP_CARRY);
TYPE BRANCH_ACTION_Type IS (NO_BR, BR, BRL, BEQ, BNE, BLT, BLE, BGT, BGE);
- TYPE WRB_ACTION_Type IS (NO_WRB, WRB_EX, WRB_MEM, WRB_FSL);
+ TYPE WRB_ACTION_Type IS (NO_WRB, WRB_EX, WRB_MEM);
TYPE MEM_ACTION_Type IS (NO_MEM, WR_MEM, RD_MEM);
TYPE TRANSFER_SIZE_Type IS (WORD, HALFWORD, BYTE);
TYPE SAVE_REG_Type IS (NO_SAVE, SAVE_RA, SAVE_RB);
mem_Action : MEM_ACTION_Type; -- rd_mem implies writeback
transfer_Size : TRANSFER_SIZE_Type;
wrb_Action : WRB_ACTION_Type;
- FSL_Non_blocking : STD_LOGIC; -- ncta
- FSL_Control : STD_LOGIC;
- FSL_Test : STD_LOGIC;
- FSL_Atomic : STD_LOGIC;
END RECORD;
TYPE ID2GPRF_Type IS RECORD
TYPE MSR_Type IS RECORD
IE : STD_LOGIC; -- MSR[VHDL b1] = [MicroBlaze b30]
C : STD_LOGIC; -- MSR[VHDL b2 and b31] = [MicroBlaze b29 and b0]
- FSL : STD_LOGIC; -- MSR[VHDL b4] = [MicroBlaze b27]
END RECORD;
TYPE EX2IF_Type IS RECORD
data_rD : STD_LOGIC_VECTOR (31 DOWNTO 0);
END RECORD;
- TYPE EX2FSL_M_Type IS RECORD
- FSLx_M : STD_LOGIC_VECTOR ( 3 DOWNTO 0);
- M_Write : STD_LOGIC;
- M_Data : STD_LOGIC_VECTOR (31 DOWNTO 0);
- M_Control : STD_LOGIC;
- END RECORD;
-
- TYPE FSL_M2EX_Type IS RECORD
- M_Full : STD_LOGIC;
- END RECORD;
-
- TYPE EX2FSL_S_Type IS RECORD
- FSLx_S : STD_LOGIC_VECTOR ( 3 DOWNTO 0);
- S_Read : STD_LOGIC;
- END RECORD;
-
- TYPE FSL_S2EX_Type IS RECORD
- S_Control : STD_LOGIC;
- S_Exists : STD_LOGIC;
- END RECORD;
-
- TYPE FSL_S2MEM_Type IS RECORD
- S_Data : STD_LOGIC_VECTOR (31 DOWNTO 0);
- END RECORD;
-
TYPE MEM_REG_Type IS RECORD
wrb_Action : WRB_ACTION_Type;
exeq_result : STD_LOGIC_VECTOR (31 DOWNTO 0);
-- NOTE: Use the named association format xxxx := ( 0 => X"A0010000" );
-- in case the array has to contain only one element !!
- TYPE CORE2FSL_M_Type IS RECORD
- -- connect M_Clk directly to highest level clock
- M_Write : STD_LOGIC;
- M_Data : STD_LOGIC_VECTOR (31 DOWNTO 0);
- M_Control : STD_LOGIC;
- END RECORD;
-
- TYPE FSL_M2CORE_Type IS RECORD
- M_Full : STD_LOGIC;
- END RECORD;
-
- TYPE CORE2FSL_S_Type IS RECORD
- -- connect S_Clk directly to highest level clock
- S_Read : STD_LOGIC;
- END RECORD;
-
- TYPE FSL_S2CORE_Type IS RECORD
- S_Exists : STD_LOGIC;
- S_Data : STD_LOGIC_VECTOR (31 DOWNTO 0);
- S_Control : STD_LOGIC;
- END RECORD;
-
- TYPE CORE2FSL_M_ARRAY_Type IS ARRAY(NATURAL RANGE <>) OF CORE2FSL_M_Type;
- TYPE FSL_M2CORE_ARRAY_Type IS ARRAY(NATURAL RANGE <>) OF FSL_M2CORE_Type;
- TYPE CORE2FSL_S_ARRAY_Type IS ARRAY(NATURAL RANGE <>) OF CORE2FSL_S_Type;
- TYPE FSL_S2CORE_ARRAY_Type IS ARRAY(NATURAL RANGE <>) OF FSL_S2CORE_Type;
-
-
----------------------------------------------------------------------------------------------
-- COMPONENTS
----------------------------------------------------------------------------------------------
INT_CTRL_i : IN INT_CTRL_Type;
ID2CTRL_o : OUT ID2CTRL_Type;
--
- noLiteOpc_s : OUT STD_LOGIC
+ noLiteOpc_o : OUT STD_LOGIC
);
END COMPONENT;
MSR_i : IN MSR_Type;
MSR_o : OUT MSR_Type;
--
- EX2MEM_o : OUT EX2MEM_Type;
- --
- exq_branch_i : IN STD_LOGIC;
- --
- FSL_M2EX_i : IN FSL_M2EX_Type;
- EX2FSL_M_o : OUT EX2FSL_M_Type;
- --
- FSL_S2EX_i : IN FSL_S2EX_Type;
- EX2FSL_S_o : OUT EX2FSL_S_Type;
- --
- FSL_nStall_o : OUT STD_LOGIC
+ EX2MEM_o : OUT EX2MEM_Type
);
END COMPONENT;
DMEMB_i : IN DMEMB2CORE_Type;
DMEMB_o : OUT CORE2DMEMB_Type;
--
- FSL_S2MEM_i : IN FSL_S2MEM_Type;
- --
MEM_REG_i : IN MEM_REG_Type;
MEM_REG_o : OUT MEM_REG_Type;
--
-- decode control i/o
ID2CTRL_i : IN ID2CTRL_Type;
INT_CTRL_o : OUT INT_CTRL_Type;
- -- FSL to mem data delay register(s)
- FSL_S2MEM_REG_i : IN FSL_S2MEM_Type;
- FSL_S2MEM_REG_o : OUT FSL_S2MEM_Type;
-- exeq control i/o
EX_WRB_i : IN WRB_Type;
EX_WRB_o : OUT WRB_Type;
MSR_o : OUT MSR_Type;
-- miscellaneous
MEM2CTRL_i : IN MEM2CTRL_Type;
- FSL_nStall_i : IN STD_LOGIC;
done_o : OUT STD_LOGIC
);
END COMPONENT;
- COMPONENT fsl_M_selector IS
- GENERIC (
- N_FSL_M_g : POSITIVE RANGE 1 TO 16 := 1 -- 1 upto 16
- );
- PORT (
- EX2FSL_M_i : IN EX2FSL_M_Type;
- FSL_M2EX_o : OUT FSL_M2EX_Type;
- --
- FSL_M_ARRAY_i : IN FSL_M2CORE_ARRAY_Type (0 TO N_FSL_M_g -1);
- FSL_M_ARRAY_o : OUT CORE2FSL_M_ARRAY_Type (0 TO N_FSL_M_g -1)
- );
- END COMPONENT;
-
- COMPONENT fsl_S_selector IS
- GENERIC (
- N_FSL_S_g : POSITIVE RANGE 1 TO 16 := 1 -- 1 upto 16
- );
- PORT (
- EX2FSL_S_i : IN EX2FSL_S_Type;
- FSL_S2EX_o : OUT FSL_S2EX_Type;
- FSL_S2MEM_o : OUT FSL_S2MEM_Type;
- --
- FSL_S_ARRAY_i : IN FSL_S2CORE_ARRAY_Type (0 TO N_FSL_S_g -1);
- FSL_S_ARRAY_o : OUT CORE2FSL_S_ARRAY_Type (0 TO N_FSL_S_g -1)
- );
- END COMPONENT;
-
----------------------------------------------------------------------------------------------
-- FUNCTION, PROCEDURE DECLARATIONS
----------------------------------------------------------------------------------------------
DMEMB_i : IN DMEMB2CORE_Type;
DMEMB_o : OUT CORE2DMEMB_Type;
--
- FSL_S2MEM_i : IN FSL_S2MEM_Type;
- --
MEM_REG_i : IN MEM_REG_Type;
MEM_REG_o : OUT MEM_REG_Type;
--
DMEMB_o.bSel <= EX2MEM_i.byte_Enable;
p_mem:
- PROCESS (EX2MEM_i, DMEMB_i, MEM_REG_i, FSL_S2MEM_i)
+ PROCESS (EX2MEM_i, DMEMB_i, MEM_REG_i)
VARIABLE exeq_data_v : STD_LOGIC_VECTOR (31 DOWNTO 0);
VARIABLE dmem_data_v : STD_LOGIC_VECTOR (31 DOWNTO 0);
WHEN WRB_EX =>
-- forward exeq output, to handle e.g. add rD,rA,xx; sw rD,mem[y]; ...
exeq_data_v := MEM_REG_i.exeq_result;
- WHEN WRB_FSL =>
- -- forward FSL_S input, to handle e.g. nget rD,rFSLx; swi rD,mem[x],xx; ...
- exeq_data_v := FSL_S2MEM_i.S_Data;
WHEN OTHERS =>
-- forward mem_data just read, to handle e.g. lhu rD,mem[x]; sh rD,mem[y]; ...
exeq_data_v := dmem_data_v;
-- additional wrb signals
CASE MEM_REG_i.wrb_Action IS
WHEN WRB_MEM => MEM_WRB_o.data_rD <= dmem_data_v;
- WHEN WRB_FSL => MEM_WRB_o.data_rD <= FSL_S2MEM_i.S_Data;
WHEN OTHERS => MEM_WRB_o.data_rD <= MEM_REG_i.exeq_result;
END CASE;
projects / fpga / lx-cpu1 / tumbl.git / commitdiff