-- mem pipeline register
MEM_REG_i : IN MEM_REG_Type;
MEM_REG_o : OUT MEM_REG_Type;
- -- FSL to mem data delay register(s)
- FSL_S2MEM_REG_i : IN FSL_S2MEM_Type;
- FSL_S2MEM_REG_o : OUT FSL_S2MEM_Type;
-- decode control i/o
ID2CTRL_i : IN ID2CTRL_Type;
INT_CTRL_o : OUT INT_CTRL_Type;
MSR_o : OUT MSR_Type;
-- miscellaneous
MEM2CTRL_i : IN MEM2CTRL_Type;
- FSL_nStall_i : IN STD_LOGIC;
done_o : OUT STD_LOGIC
);
END ENTITY core_ctrl;
SIGNAL setup_int_r : STD_LOGIC;
SIGNAL int_busy_r : STD_LOGIC;
- SIGNAL S_Data_r : STD_LOGIC_VECTOR (31 DOWNTO 0);
- SIGNAL S_Data_2r : STD_LOGIC_VECTOR (31 DOWNTO 0);
-
BEGIN
pc_ctrl_o <= NOT rst_r;
imem_addr_o <= IF2ID_REG_i.program_counter;
-- clock/wait control lines
- clken_s <= (MEM2CTRL_i.clken AND FSL_nStall_i) OR rst_i;
+ clken_s <= MEM2CTRL_i.clken OR rst_i;
clken_pipe_s <= clken_s AND (NOT HAZARD_WRB_i.hazard);
imem_clken_o <= clken_pipe_s;
gprf_clken_o <= clken_s;
INT_CTRL_o.setup_int <= setup_int_r;
INT_CTRL_o.rti_target <= ID2EX_REG_r.program_counter;
INT_CTRL_o.int_busy <= int_busy_r;
- --
- FSL_S2MEM_REG_o.S_Data <= S_Data_2r;
regd_proc:
PROCESS ( clk_i, rst_i, halt_i,
flush_ID2EX_s, flush_EX2MEM_s, HAZARD_WRB_i,
MEM_REG_i, ID2CTRL_i, int_i, MSR_i,
int_busy_r, delayBit_r, IMM_LOCK_i, ID2EX_REG_i, ID2EX_REG_r,
- EX2IF_REG_i, EX_WRB_i, S_Data_r, FSL_S2MEM_REG_i, EX2MEM_REG_i )
+ EX2IF_REG_i, EX_WRB_i, EX2MEM_REG_i )
-- some local procedures
PROCEDURE lp_rst_IF2ID_REG IS
ID2EX_REG_r.mem_Action <= NO_MEM;
ID2EX_REG_r.transfer_Size <= WORD;
ID2EX_REG_r.wrb_Action <= NO_WRB;
- ID2EX_REG_r.FSL_Test <= '1';
- ID2EX_REG_r.FSL_Non_blocking <= '1';
- ID2EX_REG_r.FSL_Control <= '0';
- ID2EX_REG_r.FSL_Atomic <= '0';
END PROCEDURE;
PROCEDURE lp_rst_EX2IF_REG IS
EX2MEM_REG_o.wrix_rD <= (OTHERS => '0');
END PROCEDURE;
- PROCEDURE lp_rst_FSL2MEM_REG IS
- BEGIN
- S_Data_r <= (OTHERS => '0');
- S_Data_2r <= (OTHERS => '0');
- END PROCEDURE;
-
PROCEDURE lp_rst_IMM_LOCK IS
BEGIN
IMM_LOCK_r.locked <= '0';
BEGIN
MSR_o.IE <= '0';
MSR_o.C <= '0';
- MSR_o.FSL <= '0';
END PROCEDURE;
PROCEDURE lp_rst_EX_WRB IS
lp_rst_MSR;
lp_rst_HAZARD_WRB;
lp_rst_MEM_REG;
- lp_rst_FSL2MEM_REG;
delayBit_r <= '0';
flush_ID2EX_r <= '0';
setup_int_r <= '0';
EX2IF_REG_r <= EX2IF_REG_i;
delayBit_2r <= delayBit_r;
EX_WRB_o <= EX_WRB_i;
- S_Data_2r <= S_Data_r;
- S_Data_r <= FSL_S2MEM_REG_i.S_Data;
END IF;
IF (clken_s = '1') THEN
-- next test to prevent a flush from disrupting