hw/fetch.vhd

   1 ---------------------------------------------------------------------------------
   2 --
   3 --  Entity:       fetch
   4 --  Filename:     fetch.vhd
   5 --  Description:  the Instruction Fetch (IF) unit for
   6 --                the TUD MB-Lite implementation
   7 --
   8 --  Author:       Huib Lincklaen Arriens
   9 --                Delft University of Technology
  10 --                Faculty EEMCS, Department ME&CE, Circuits and Systems
  11 --  Date:         September, 2010
  12 --  Modified:
  13 --  Remarks:
  14 --
  15 --------------------------------------------------------------------------------
  16
  17 LIBRARY IEEE;
  18 USE IEEE.std_logic_1164.all;
  19 USE WORK.mbl_pkg.all;
  20
  21 --------------------------------------------------------------------------------
  22 ENTITY fetch IS
  23 --------------------------------------------------------------------------------
  24         PORT
  25         (
  26                 prog_cntr_i :  IN STD_LOGIC_VECTOR (31 DOWNTO 0);
  27                 inc_pc_i    :  IN STD_LOGIC;
  28                 EX2IF_i     :  IN EX2IF_Type;
  29                 IF2ID_o     : OUT IF2ID_Type
  30         );
  31 END ENTITY fetch;
  32
  33 --------------------------------------------------------------------------------
  34 ARCHITECTURE rtl OF fetch IS
  35 --------------------------------------------------------------------------------
  36
  37 BEGIN
  38
  39 p_fetch:
  40         PROCESS ( prog_cntr_i, inc_pc_i, EX2IF_i )
  41                 VARIABLE next_pc_v : STD_LOGIC_VECTOR (31 DOWNTO 0);
  42                 VARIABLE incVal_v  : STD_LOGIC_VECTOR (31 DOWNTO 0);
  43         BEGIN
  44                 incVal_v := X"0000000" & '0' & inc_pc_i & "00";
  45                 ep_add32nc ( prog_cntr_i, incVal_v, '0', next_pc_v );
  46                 IF (EX2IF_i.take_branch = '0') THEN
  47                         IF2ID_o.program_counter <= next_pc_v;
  48                 ELSE
  49                         IF2ID_o.program_counter <= EX2IF_i.branch_target;
  50                 END IF;
  51         END PROCESS;
  52
  53 END ARCHITECTURE rtl;