1 ---------------------------------------------------------------------------------
5 -- Description: the Execution (EX) unit for the TUD MB-Lite implementation
7 -- Author: Huib Lincklaen Arriens
8 -- Delft University of Technology
9 -- Faculty EEMCS, Department ME&CE, Circuits and Systems
10 -- Date: September, 2010
12 -- Modified: Septemper, 2013: FSL scratched, core customized (Meloun)
13 -- December, 2010: FSL added (Huib)
14 -- June, 2011: added code for MUL and BARREL (Huib)
15 -- Adapted to work with separate fsl_M-
16 -- and fsl_S selectors and automatic
17 -- tumbl<_jtag><_fsl>.vhd generation (Huib)
20 --------------------------------------------------------------------------------
24 USE IEEE.std_logic_1164.all;
25 USE IEEE.numeric_std.all;
28 ----------------------------------------------------------
30 ----------------------------------------------------------
33 USE_HW_MUL_g : BOOLEAN := TRUE;
34 USE_BARREL_g : BOOLEAN := TRUE;
35 COMPATIBILITY_MODE_g : BOOLEAN := FALSE
39 IF2ID_i : IN IF2ID_Type;
41 ID2EX_i : IN ID2EX_Type;
42 delayBit_i : IN STD_LOGIC;
43 GPRF2EX_i : IN GPRF2EX_Type;
44 EX2IF_o : OUT EX2IF_Type;
45 EX2CTRL_o : OUT EX2CTRL_Type;
46 HALT_o : OUT HALT_Type;
48 EX_WRB_i : IN WRB_Type;
49 EX_WRB_o : OUT WRB_Type;
50 MEM_WRB_i : IN WRB_Type;
52 HAZARD_WRB_i : IN HAZARD_WRB_Type;
53 HAZARD_WRB_o : OUT HAZARD_WRB_Type;
55 IMM_LOCK_i : IN IMM_LOCK_Type;
56 IMM_LOCK_o : OUT IMM_LOCK_Type;
61 EX2MEM_o : OUT EX2MEM_Type
65 ----------------------------------------------------------
66 ARCHITECTURE rtl OF exeq IS
67 ----------------------------------------------------------
72 PROCESS (ID2EX_i, GPRF2EX_i, EX_WRB_i, MEM_WRB_i,
73 IF2ID_i, delayBit_i, IMM_LOCK_i, MSR_i, HAZARD_WRB_i)
75 -- function needed by BSLL (only if USE_BARREL_g = TRUE)
76 FUNCTION reverse_bits ( word32 : STD_LOGIC_VECTOR (31 DOWNTO 0) )
77 RETURN STD_LOGIC_VECTOR IS
78 VARIABLE reversed_v : STD_LOGIC_VECTOR (31 DOWNTO 0);
82 reversed_v(31-i) := word32(i);
87 VARIABLE data_rA_v : STD_LOGIC_VECTOR (31 DOWNTO 0);
88 VARIABLE data_rB_v : STD_LOGIC_VECTOR (31 DOWNTO 0);
89 VARIABLE data_rD_v : STD_LOGIC_VECTOR (31 DOWNTO 0);
90 VARIABLE in1_v : STD_LOGIC_VECTOR (31 DOWNTO 0);
91 VARIABLE in2_v : STD_LOGIC_VECTOR (31 DOWNTO 0);
92 VARIABLE hi16_v : STD_LOGIC_VECTOR (15 DOWNTO 0);
93 VARIABLE IMM32_v : STD_LOGIC_VECTOR (31 DOWNTO 0);
94 VARIABLE carry_i_v : STD_LOGIC;
95 VARIABLE result_v : STD_LOGIC_VECTOR (31 DOWNTO 0);
96 VARIABLE carry_o_v : STD_LOGIC;
97 VARIABLE isZero_v : STD_LOGIC;
98 VARIABLE signBit_in1_v : STD_LOGIC;
99 VARIABLE signBit_in2_v : STD_LOGIC;
100 VARIABLE signBit_r_v : STD_LOGIC;
101 VARIABLE rA_eq_ex_rD_v : STD_LOGIC;
102 VARIABLE rB_eq_ex_rD_v : STD_LOGIC;
103 VARIABLE hazard_v : STD_LOGIC;
104 VARIABLE save_rX_v : SAVE_REG_Type;
105 VARIABLE data_rX_v : STD_LOGIC_VECTOR (31 DOWNTO 0);
106 VARIABLE do_branch_v : STD_LOGIC;
107 VARIABLE byte_Enable_v : STD_LOGIC_VECTOR ( 3 DOWNTO 0);
108 VARIABLE tmp64_v : STD_LOGIC_VECTOR (63 DOWNTO 0);
109 VARIABLE padVec_v : STD_LOGIC_VECTOR (15 DOWNTO 0);
110 VARIABLE do_cond_v : STD_LOGIC;
114 rA_eq_ex_rD_v := '0';
115 rB_eq_ex_rD_v := '0';
117 save_rX_v := NO_SAVE;
118 data_rX_v := data_rB_v; -- default value for data_rX_v
119 result_v := (OTHERS => '0');
122 byte_Enable_v := (OTHERS => '0');
125 MSR_o <= MSR_i; -- pass MSR by default
127 -- create some helper variables
128 IF (ID2EX_i.rdix_rA = EX_WRB_i.wrix_rD) THEN
129 rA_eq_ex_rD_v := '1';
131 IF (ID2EX_i.rdix_rB = EX_WRB_i.wrix_rD) THEN
132 rB_eq_ex_rD_v := '1';
134 -- test where to obtain data_rA from
135 IF ((EX_WRB_i.wrb_Action = WRB_EX) AND (rA_eq_ex_rD_v = '1')) THEN
136 data_rA_v := EX_WRB_i.data_rD;
137 ELSIF ((MEM_WRB_i.wrb_Action /= NO_WRB) AND (ID2EX_i.rdix_rA = MEM_WRB_i.wrix_rD)) THEN
138 data_rA_v := MEM_WRB_i.data_rD;
139 ELSIF ((HAZARD_WRB_i.hazard = '1') AND (HAZARD_WRB_i.save_rX = SAVE_RA)) THEN
140 data_rA_v := HAZARD_WRB_i.data_rX;
142 data_rA_v := GPRF2EX_i.data_rA;
144 -- test where to obtain data_rB from
145 IF ((EX_WRB_i.wrb_Action = WRB_EX) AND (rB_eq_ex_rD_v = '1')) THEN
146 data_rB_v := EX_WRB_i.data_rD;
147 ELSIF ((MEM_WRB_i.wrb_Action /= NO_WRB) AND (ID2EX_i.rdix_rB = MEM_WRB_i.wrix_rD)) THEN
148 data_rB_v := MEM_WRB_i.data_rD;
149 ELSIF ((HAZARD_WRB_i.hazard = '1') AND (HAZARD_WRB_i.save_rX = SAVE_RB)) THEN
150 data_rB_v := HAZARD_WRB_i.data_rX;
152 data_rB_v := GPRF2EX_i.data_rB;
154 -- .... or, isn't all necessary data available yet being still in the pipeline ?
155 data_rX_v := data_rB_v; -- default value for data_rX_v
156 IF (EX_WRB_i.wrb_Action = WRB_MEM) THEN
157 IF ((rA_eq_ex_rD_v = '1') OR (rB_eq_ex_rD_v = '1')) THEN
159 IF (rA_eq_ex_rD_v = '1') THEN
160 save_rX_v := SAVE_RB; -- already by default data_rX_v = data_rB_v
162 save_rX_v := SAVE_RA;
163 data_rX_v := data_rA_v;
168 IF (IMM_LOCK_i.locked = '1') THEN
169 hi16_v := IMM_LOCK_i.IMM_hi16;
170 ELSIF (ID2EX_i.IMM16(15) = '0') THEN
171 hi16_v := C_16_ZEROS;
175 IMM32_v := hi16_v & ID2EX_i.IMM16;
177 CASE ID2EX_i.alu_Op1 IS
178 WHEN ALU_IN_REGA => in1_v := data_rA_v;
179 WHEN ALU_IN_NOT_REGA => in1_v := NOT data_rA_v;
180 WHEN ALU_IN_PC => in1_v := ID2EX_i.program_counter;
181 WHEN ALU_IN_ZERO => in1_v := C_32_ZEROS;
185 CASE ID2EX_i.alu_Op2 IS
186 WHEN ALU_IN_REGB => in2_v := data_rB_v;
187 WHEN ALU_IN_NOT_REGB => in2_v := NOT data_rB_v;
188 WHEN ALU_IN_IMM => in2_v := IMM32_v;
189 WHEN ALU_IN_NOT_IMM => in2_v := NOT IMM32_v;
193 signBit_in1_v := in1_v(31);
194 signBit_in2_v := in2_v(31);
195 signBit_r_v := data_rA_v(31); -- Init with Op1, then possibly override
197 CASE ID2EX_i.alu_Cin IS
198 WHEN CIN_ZERO => carry_i_v := '0';
199 WHEN CIN_ONE => carry_i_v := '1';
200 WHEN FROM_MSR => carry_i_v := MSR_i.C;
201 WHEN FROM_IN1 => carry_i_v := in1_v(31);
202 WHEN OTHERS => carry_i_v := '0';
205 IF (data_rA_v = C_32_ZEROS) THEN
211 CASE ID2EX_i.alu_Action IS
213 WHEN A_ADD | A_CMP | A_CMPU =>
214 ep_add32 ( in1_v, in2_v, carry_i_v, result_v, carry_o_v);
215 CASE ID2EX_i.alu_Action IS
218 IF (signBit_in1_v = signBit_in2_v) THEN
219 signBit_r_v := NOT signBit_in1_v;
221 IF (COMPATIBILITY_MODE_g = FALSE) AND (ID2EX_i.it_Action /= NO_IT) THEN
222 -- have to update zero flag with current result
223 IF (result_v = C_32_ZEROS) THEN
231 IF (signBit_in1_v = signBit_in2_v) THEN
232 signBit_r_v := signBit_in1_v;
234 IF (COMPATIBILITY_MODE_g = FALSE) AND (ID2EX_i.it_Action /= NO_IT) THEN
235 -- have to update zero flag with current result
236 IF (result_v = C_32_ZEROS) THEN
249 result_v := in1_v OR in2_v;
252 result_v := in1_v AND in2_v;
255 result_v := in1_v XOR in2_v;
258 result_v := carry_i_v & in1_v(31 DOWNTO 1);
259 carry_o_v := in1_v(0);
262 IF (in1_v(7) = '0') THEN
263 result_v := C_24_ZEROS & in1_v( 7 DOWNTO 0);
265 result_v := C_24_ONES & in1_v( 7 DOWNTO 0);
269 IF (in1_v(15) = '0') THEN
270 result_v := C_16_ZEROS & in1_v(15 DOWNTO 0);
272 result_v := C_16_ONES & in1_v(15 DOWNTO 0);
276 if (COMPATIBILITY_MODE_g = FALSE) THEN
277 result_v := C_24_ZEROS & "00000" & MSR_i.C & MSR_i.IE & '0';
279 result_v := MSR_i.C & C_24_ZEROS & "0000" & MSR_i.C & MSR_i.IE & '0';
283 MSR_o.IE <= data_Ra_v(1);
284 MSR_o.C <= data_Ra_v(2);
287 IF (USE_HW_MUL_g = TRUE) THEN
288 tmp64_v := STD_LOGIC_VECTOR( UNSIGNED(in1_v) * UNSIGNED(in2_v) );
289 result_v := tmp64_v(31 DOWNTO 0);
292 WHEN A_BSLL | A_BSRL | A_BSRA =>
293 IF (USE_BARREL_g = TRUE) THEN
294 IF (ID2EX_i.alu_Action = A_BSLL) THEN
295 result_v := reverse_bits (in1_v);
299 IF (ID2EX_i.alu_Action = A_BSRA) THEN
300 padVec_v := (OTHERS => in1_v(31));
302 padVec_v := (OTHERS => '0');
304 IF (in2_v(4) = '1') THEN
305 result_v := padVec_v (15 DOWNTO 0) & result_v (31 DOWNTO 16);
307 IF (in2_v(3) = '1') THEN
308 result_v := padVec_v ( 7 DOWNTO 0) & result_v (31 DOWNTO 8);
310 IF (in2_v(2) = '1') THEN
311 result_v := padVec_v ( 3 DOWNTO 0) & result_v (31 DOWNTO 4);
313 IF (in2_v(1) = '1') THEN
314 result_v := padVec_v ( 1 DOWNTO 0) & result_v (31 DOWNTO 2);
316 IF (in2_v(0) = '1') THEN
317 result_v := padVec_v ( 0 DOWNTO 0) & result_v (31 DOWNTO 1);
319 IF (ID2EX_i.alu_Action = A_BSLL) THEN
320 result_v := reverse_bits (result_v);
322 END IF; -- (USE_BARREL_g = TRUE)
325 tmp64_v := (OTHERS => '0');
326 leading_zeroes32 ( in1_v, UNSIGNED(tmp64_v(31 DOWNTO 0)), result_v );
333 CASE ID2EX_i.condition IS
334 WHEN COND_EQ => do_cond_v := isZero_v;
335 WHEN COND_NE => do_cond_v := NOT isZero_v;
336 WHEN COND_LT => do_cond_v := signBit_r_v;
337 WHEN COND_LE => do_cond_v := signBit_r_v OR isZero_v;
338 WHEN COND_GT => do_cond_v := NOT (signBit_r_v OR isZero_v);
339 WHEN COND_GE => do_cond_v := NOT signBit_r_v;
340 WHEN COND_ALL => do_cond_v := '1';
344 CASE ID2EX_i.branch_Action IS
345 WHEN BR => do_branch_v := do_cond_v;
346 WHEN BRL => do_branch_v := '1';
350 IF (do_branch_v = '1') THEN
351 EX2IF_o.take_branch <= '1';
352 EX2IF_o.branch_target <= result_v;
354 EX2IF_o.take_branch <= '0';
355 EX2IF_o.branch_target <= C_32_ZEROS;
358 -- IT / ITE / ITT conditioning
359 IF (COMPATIBILITY_MODE_g = FALSE) THEN
360 CASE ID2EX_i.it_Action IS
362 EX2CTRL_o.flush_first <= not do_cond_v;
363 EX2CTRL_o.flush_second <= '0';
364 EX2CTRL_o.ignore_state <= '1';
366 EX2CTRL_o.flush_first <= not do_cond_v;
367 EX2CTRL_o.flush_second <= not do_cond_v;
368 EX2CTRL_o.ignore_state <= '1';
370 EX2CTRL_o.flush_first <= not do_cond_v;
371 EX2CTRL_o.flush_second <= do_cond_v;
372 EX2CTRL_o.ignore_state <= '1';
374 EX2CTRL_o.flush_first <= '0';
375 EX2CTRL_o.flush_second <= '0';
376 EX2CTRL_o.ignore_state <= '0';
380 -- Halting, the instruction parsing is separate
381 HALT_o.halt <= ID2EX_i.halt;
382 IF (ID2EX_i.halt = '1') THEN
383 HALT_o.halt_code <= ID2EX_i.IMM16(4 DOWNTO 0);
385 HALT_o.halt_code <= (others => '0');
388 -- WR_MEM/RD_MEM: result_v --> exeq_result --> mem_address,
389 -- WR_MEM: data_rD --> data_out_to_mem
390 -- BRL: prog_counter --> exeq_result
391 -- else result_v --> exeq_result (data_rD not used)
392 EX2MEM_o.wrix_rD <= ID2EX_i.curr_rD;
393 IF (ID2EX_i.branch_Action = BRL) THEN
394 EX2MEM_o.wrb_Action <= WRB_EX;
395 IF (COMPATIBILITY_MODE_g = TRUE) OR (delayBit_i = '0') THEN
396 EX2MEM_o.exeq_result <= ID2EX_i.program_counter;
397 EX2MEM_o.data_rD <= ID2EX_i.program_counter;
399 EX2MEM_o.exeq_result <= IF2ID_i.program_counter;
400 EX2MEM_o.data_rD <= IF2ID_i.program_counter;
402 -- set data_rD_v, although unused, to prevent an inferred latch
403 data_rD_v := GPRF2EX_i.data_rD;
405 EX2MEM_o.wrb_Action <= ID2EX_i.wrb_Action;
406 EX2MEM_o.exeq_result <= result_v;
407 -- test where to obtain data_rD from
408 IF (HAZARD_WRB_i.hazard = '1') THEN
409 data_rD_v := HAZARD_WRB_i.data_rD;
410 ELSIF ((EX_WRB_i.wrb_Action = WRB_EX) AND (ID2EX_i.curr_rD = EX_WRB_i.wrix_rD)) THEN
411 -- forward rD_data just calculated, to handle e.g. addi rD,rA,Imm; sw rD,mem[y]; ...
412 data_rD_v := EX_WRB_i.data_rD;
413 ELSIF ((MEM_WRB_i.wrb_Action /= NO_WRB) AND (ID2EX_i.curr_rD = MEM_WRB_i.wrix_rD)) THEN
414 data_rD_v := MEM_WRB_i.data_rD;
416 data_rD_v := GPRF2EX_i.data_rD;
420 IF (ID2EX_i.mem_Action /= NO_MEM) THEN
421 CASE ID2EX_i.transfer_Size IS
424 CASE result_v( 1 DOWNTO 0) IS
425 WHEN "00" => byte_Enable_v := "1000";
426 WHEN "01" => byte_Enable_v := "0100";
427 WHEN "10" => byte_Enable_v := "0010";
428 WHEN "11" => byte_Enable_v := "0001";
433 CASE result_v( 1 DOWNTO 0) IS
434 WHEN "00" => byte_Enable_v := "1100";
435 WHEN "10" => byte_Enable_v := "0011";
439 WHEN OTHERS => byte_Enable_v := "1111";
444 -- update MSR[C] if needed
445 IF (ID2EX_i.msr_Action = UPDATE_CARRY) THEN
446 MSR_o.C <= carry_o_v;
449 -- pass remaining data to mem
450 EX2MEM_o.mem_Action <= ID2EX_i.mem_Action;
451 EX2MEM_o.data_rD <= data_rD_v;
452 EX2MEM_o.byte_Enable <= byte_Enable_v;
453 EX2MEM_o.wrix_rD <= ID2EX_i.curr_rD;
455 IMM_LOCK_o.locked <= ID2EX_i.IMM_Lock;
456 IMM_LOCK_o.IMM_hi16 <= ID2EX_i.IMM16;
458 EX_WRB_o.wrb_Action <= ID2EX_i.wrb_Action;
459 EX_WRB_o.wrix_rD <= ID2EX_i.curr_rD;
460 EX_WRB_o.data_rD <= result_v;
462 HAZARD_WRB_o.hazard <= hazard_v;
463 HAZARD_WRB_o.save_rX <= save_rX_v;
464 HAZARD_WRB_o.data_rX <= data_rX_v;
465 HAZARD_WRB_o.data_rD <= data_rD_v;
469 END ARCHITECTURE rtl;