hw/core_ctrl.vhd

   1 ---------------------------------------------------------------------------------
   2 --
   3 --  Entity:       core_ctrl
   4 --  Filename:     core_ctrl.vhd
   5 --  Description:  the control unit for the TUD MB-Lite implementation
   6 --
   7 --  Author:       Huib Lincklaen Arriens
   8 --                Delft University of Technology
   9 --                Faculty EEMCS, Department ME&CE, Circuits and Systems
  10 --  Date:         December, 2010
  11 --  Modified:     September, 2013: Core customization (Meloun)
  12 --                September, 2012: interrupt handling corrected to let
  13 --                                 a pending branch be taken first
  14 --                                 (with thanks to Matthis Meier, TU Dortmund,
  15 --                                  for detecting this errror).
  16 --  Remarks:
  17 --
  18 --------------------------------------------------------------------------------
  19
  20 LIBRARY IEEE;
  21
  22 USE IEEE.std_logic_1164.all;
  23 USE WORK.mbl_pkg.all;
  24
  25 --------------------------------------------------------------------------------
  26 ENTITY core_ctrl IS
  27 --------------------------------------------------------------------------------
  28         GENERIC
  29         (
  30                 IMEM_ABITS_g         : positive := 9;
  31                 COMPATIBILITY_MODE_g : BOOLEAN := FALSE
  32         );
  33         PORT
  34         (
  35                 clk_i           :  IN STD_LOGIC;
  36                 rst_i           :  IN STD_LOGIC;
  37                 halt_i          :  IN STD_LOGIC;
  38                 int_i           :  IN STD_LOGIC;
  39                 trace_i         :  IN STD_LOGIC;
  40                 trace_kick_i    :  IN STD_LOGIC;
  41                 core_clken_o    : OUT STD_LOGIC;
  42                 -- specific fetch i/o
  43                 imem_addr_o     : OUT STD_LOGIC_VECTOR ((IMEM_ABITS_g-1) DOWNTO 0);
  44                 imem_clken_o    : OUT STD_LOGIC;
  45                 pc_ctrl_o       : OUT STD_LOGIC;
  46                 -- fetch to decode pipeline registers
  47                 IF2ID_REG_i     :  IN IF2ID_Type;
  48                 IF2ID_REG_o     : OUT IF2ID_Type;
  49                 -- decode to exeq pipeline registers
  50                 ID2EX_REG_i     :  IN ID2EX_Type;
  51                 ID2EX_REG_o     : OUT ID2EX_Type;
  52                 delay_bit_o     : OUT STD_LOGIC;
  53                 -- GPRF control
  54                 gprf_clken_o    : OUT STD_LOGIC;
  55                 -- exeq to fetch feedback registers
  56                 EX2IF_REG_i     :  IN EX2IF_Type;
  57                 EX2IF_REG_o     : OUT EX2IF_Type;
  58                 EX2CTRL_REG_i   :  IN EX2CTRL_Type;
  59                 -- exeq to core (halting)
  60                 exeq_halt_i     :  IN STD_LOGIC;
  61                 -- exeq to mem pipeline registers
  62                 EX2MEM_REG_i    :  IN EX2MEM_Type;
  63                 EX2MEM_REG_o    : OUT EX2MEM_Type;
  64                 -- mem pipeline register
  65                 MEM_REG_i       :  IN MEM_REG_Type;
  66                 MEM_REG_o       : OUT MEM_REG_Type;
  67                 -- decode control i/o
  68                 ID2CTRL_i       :  IN ID2CTRL_Type;
  69                 INT_CTRL_o      : OUT INT_CTRL_Type;
  70                 -- exeq control i/o
  71                 EX_WRB_i        :  IN WRB_Type;
  72                 EX_WRB_o        : OUT WRB_Type;
  73                 -- data hazard i/o
  74                 HAZARD_WRB_i    :  IN HAZARD_WRB_Type;
  75                 HAZARD_WRB_o    : OUT HAZARD_WRB_Type;
  76                 -- for handling the 'IMM' instruction
  77                 IMM_LOCK_i      :  IN IMM_LOCK_Type;
  78                 IMM_LOCK_o      : OUT IMM_LOCK_Type;
  79                 -- for handling the Machine Status Register
  80                 MSR_i           :  IN MSR_Type;
  81                 MSR_o           : OUT MSR_Type;
  82                 -- miscellaneous
  83                 MEM2CTRL_i      :  IN MEM2CTRL_Type
  84         );
  85 END ENTITY core_ctrl;
  86
  87 --------------------------------------------------------------------------------
  88 ARCHITECTURE rtl OF core_ctrl IS
  89 --------------------------------------------------------------------------------
  90
  91         SIGNAL rst_r           : STD_LOGIC;
  92         SIGNAL reset_s         : STD_LOGIC;
  93         SIGNAL core_clken_s    : STD_LOGIC;
  94
  95         SIGNAL ID2EX_REG_r     : ID2EX_Type;
  96         SIGNAL EX2IF_REG_r     : EX2IF_Type;
  97         SIGNAL IMM_LOCK_r      : IMM_LOCK_Type;
  98         SIGNAL HAZARD_WRB_r    : HAZARD_WRB_Type;
  99         SIGNAL flush_first_r   : STD_LOGIC;
 100         SIGNAL flush_second_r  : STD_LOGIC;
 101         SIGNAL flush_second_2r : STD_LOGIC;
 102         SIGNAL ignore_state_r  : STD_LOGIC; -- Please note: Flushing first is considered immediate!
 103         SIGNAL delayBit_r      : STD_LOGIC;
 104         SIGNAL clken_s         : STD_LOGIC;
 105         SIGNAL clken_pipe_s    : STD_LOGIC;
 106         SIGNAL flush_ID2EX_s   : STD_LOGIC;
 107         SIGNAL flush_ID2EX_r   : STD_LOGIC;
 108         SIGNAL flush_EX2MEM_s  : STD_LOGIC;
 109
 110         SIGNAL setup_int_r     : STD_LOGIC;
 111         SIGNAL int_busy_r      : STD_LOGIC;
 112         SIGNAL repeat_mem_r    : STD_LOGIC;
 113
 114         SIGNAL wait_for_mem_s  : STD_LOGIC;
 115
 116 BEGIN
 117
 118         -- static connections
 119         reset_s        <= rst_i OR rst_r;
 120         pc_ctrl_o      <= NOT rst_r;
 121         -- Addressing is 32-bit, so omit two lowest bytes from PC
 122         imem_addr_o    <= IF2ID_REG_i.program_counter((IMEM_ABITS_g+1) DOWNTO 2);
 123         -- Tracing
 124         -- Reset_s is 1 when rst_i is one and then gets deactivated
 125         core_clken_s  <= reset_s OR (((NOT trace_i) AND (NOT exeq_halt_i)) OR trace_kick_i);
 126         core_clken_o  <= core_clken_s;
 127         -- clock/wait control lines
 128         clken_s        <= (NOT MEM2CTRL_i.bus_wait AND NOT MEM2CTRL_i.bus_taken) OR rst_i;
 129         clken_pipe_s   <= clken_s AND (NOT HAZARD_WRB_i.hazard);
 130         imem_clken_o   <= clken_pipe_s;
 131         gprf_clken_o   <= clken_s;
 132         -- signals for clearing the ID2EX and EX2MEM registers during branches
 133         flush_ID2EX_s  <= ((EX2IF_REG_i.take_branch AND (NOT delayBit_r)) OR EX2IF_REG_r.take_branch) WHEN COMPATIBILITY_MODE_g = TRUE
 134                                                                                 ELSE ((EX2IF_REG_i.take_branch AND (NOT delayBit_r)) OR EX2IF_REG_r.take_branch OR EX2CTRL_REG_i.flush_first OR
 135                                                                                                 flush_first_r OR ((NOT EX2CTRL_REG_i.ignore_state) AND (NOT ignore_state_r) AND flush_second_2r));
 136         flush_EX2MEM_s <= HAZARD_WRB_i.hazard;
 137         -- outputs that need to be readable too, so needing shadowing signals
 138         ID2EX_REG_o    <= ID2EX_REG_r;
 139         delay_bit_o    <= delayBit_r;
 140         EX2IF_REG_o    <= EX2IF_REG_r;
 141         IMM_LOCK_o     <= IMM_LOCK_r;
 142         HAZARD_WRB_o   <= HAZARD_WRB_r;
 143         --
 144         INT_CTRL_o.setup_int   <= setup_int_r;
 145         INT_CTRL_o.rti_target  <= ID2EX_REG_r.program_counter;
 146         INT_CTRL_o.int_busy    <= int_busy_r;
 147
 148         wait_for_mem_s <= MEM2CTRL_i.bus_wait OR MEM2CTRL_i.bus_taken;
 149
 150 regd_proc:
 151         PROCESS
 152
 153         -- some local procedures
 154         PROCEDURE lp_rst_IF2ID_REG IS
 155         BEGIN
 156                 IF2ID_REG_o.program_counter <= (OTHERS => '0');
 157         END PROCEDURE;
 158
 159         PROCEDURE lp_rst_ID2EX_REG IS
 160         BEGIN
 161                 -- reset and handle ID2EX_REG_r.program_counter separately,
 162                 -- since it will be needed during interrupt setup
 163                 ID2EX_REG_r.rdix_rA          <= (OTHERS => '0');
 164                 ID2EX_REG_r.rdix_rB          <= (OTHERS => '0');
 165                 ID2EX_REG_r.curr_rD          <= (OTHERS => '0');
 166                 ID2EX_REG_r.alu_Action       <= A_NOP;
 167                 ID2EX_REG_r.alu_Op1          <= ALU_IN_ZERO;
 168                 ID2EX_REG_r.alu_Op2          <= ALU_IN_IMM;
 169                 ID2EX_REG_r.alu_Cin          <= CIN_ZERO;
 170                 ID2EX_REG_r.IMM16            <= (OTHERS => '0');
 171                 ID2EX_REG_r.IMM_Lock         <= '0';
 172                 ID2EX_REG_r.msr_Action       <= KEEP_CARRY;
 173                 ID2EX_REG_r.branch_Action    <= NO_BR;
 174                 ID2EX_REG_r.mem_Action       <= NO_MEM;
 175                 ID2EX_REG_r.transfer_Size    <= WORD;
 176                 ID2EX_REG_r.wrb_Action       <= NO_WRB;
 177                 ID2EX_REG_r.condition        <= COND_ALL;
 178                 ID2EX_REG_r.halt             <= '0';
 179                 IF (COMPATIBILITY_MODE_g = FALSE) THEN
 180                         ID2EX_REG_r.it_Action      <= NO_IT;
 181                 ELSE
 182                 END IF;
 183         END PROCEDURE;
 184
 185         PROCEDURE lp_rst_EX2IF_REG IS
 186         BEGIN
 187                 EX2IF_REG_r.take_branch   <= '0';
 188                 EX2IF_REG_r.branch_target <= (OTHERS => '0');
 189         END PROCEDURE;
 190
 191         PROCEDURE lp_rst_EX2MEM_REG IS
 192         BEGIN
 193                 EX2MEM_REG_o.mem_Action  <= NO_MEM;
 194                 EX2MEM_REG_o.wrb_Action  <= NO_WRB;
 195                 EX2MEM_REG_o.exeq_result <= (OTHERS => '0');
 196                 EX2MEM_REG_o.data_rD     <= (OTHERS => '0');
 197                 EX2MEM_REG_o.byte_Enable <= (OTHERS => '0');
 198                 EX2MEM_REG_o.wrix_rD     <= (OTHERS => '0');
 199         END PROCEDURE;
 200
 201         PROCEDURE lp_rst_IMM_LOCK IS
 202         BEGIN
 203                 IMM_LOCK_r.locked   <= '0';
 204                 IMM_LOCK_r.IMM_hi16 <= (OTHERS => '0');
 205         END PROCEDURE;
 206
 207         PROCEDURE lp_rst_MSR IS
 208         BEGIN
 209                 MSR_o.IE  <= '0';
 210                 MSR_o.C   <= '0';
 211         END PROCEDURE;
 212
 213         PROCEDURE lp_rst_EX_WRB IS
 214         BEGIN
 215                 EX_WRB_o.wrb_Action <= NO_WRB;
 216                 EX_WRB_o.wrix_rD    <= (OTHERS => '0');
 217                 EX_WRB_o.data_rD    <= (OTHERS => '0');
 218         END PROCEDURE;
 219
 220         PROCEDURE lp_rst_HAZARD_WRB IS
 221         BEGIN
 222                 HAZARD_WRB_r.hazard  <= '0';
 223                 HAZARD_WRB_r.save_rX <= NO_SAVE;
 224                 HAZARD_WRB_r.data_rX <= (OTHERS => '0');
 225                 HAZARD_WRB_r.data_rD <= (OTHERS => '0');
 226         END PROCEDURE;
 227
 228         PROCEDURE lp_rst_MEM_REG IS
 229         BEGIN
 230                 MEM_REG_o.wrb_Action  <= NO_WRB;
 231                 MEM_REG_o.exeq_result <= (OTHERS => '0');
 232                 MEM_REG_o.byte_Enable <= (OTHERS => '0');
 233                 MEM_REG_o.wrix_rD     <= (OTHERS => '0');
 234         END PROCEDURE;
 235
 236         BEGIN
 237
 238         WAIT UNTIL clk_i'event AND clk_i = '1';
 239
 240         IF wait_for_mem_s = '0' AND  halt_i = '0' AND core_clken_s = '1' AND repeat_mem_r = '0' THEN
 241                         rst_r <= rst_i;
 242
 243                 repeat_mem_r  <= '0';
 244                 IF (reset_s = '1') THEN     -- synchronous reset ...
 245                         lp_rst_IF2ID_REG;       -- ... so lasts at least one clock_cycle
 246                         lp_rst_MSR;
 247                         lp_rst_HAZARD_WRB;
 248                         lp_rst_MEM_REG;
 249                         delayBit_r        <= '0';
 250
 251                         IF (COMPATIBILITY_MODE_g = FALSE) THEN
 252                                 flush_first_r   <= '0';
 253                                 flush_second_r  <= '0';
 254                                 flush_second_2r <= '0';
 255                                 ignore_state_r  <= '0';
 256                         END IF;
 257
 258                         flush_ID2EX_r <= '0';
 259                         setup_int_r   <= '0';
 260                         int_busy_r    <= '0';
 261                         ID2EX_REG_r.program_counter <= (OTHERS => '0');
 262                 ELSE
 263                         IF (clken_pipe_s = '1') THEN
 264                                 IF2ID_REG_o <= IF2ID_REG_i;
 265                         END IF;
 266                         flush_ID2EX_r <= flush_ID2EX_s;
 267                         IF (COMPATIBILITY_MODE_g = FALSE) THEN
 268                                 -- Flushing based on IT / ITE / ITT along with IMM locking
 269                                 IF (ID2EX_REG_i.IMM_Lock = '1') THEN
 270                                         IF (flush_second_2r = '0') THEN
 271                                                 flush_second_2r <= flush_second_r;
 272                                         END IF;
 273                                         flush_first_r   <= EX2CTRL_REG_i.flush_first;
 274                                         flush_second_r  <= EX2CTRL_REG_i.flush_second;
 275                                         ignore_state_r  <= EX2CTRL_REG_i.ignore_state;
 276                                 ELSE
 277                                         flush_first_r   <= '0';
 278                                         -- Directly to 2r (flushing the following instruction)
 279                                         flush_second_2r <= flush_second_r OR EX2CTRL_REG_i.flush_second;
 280                                         flush_second_r  <= '0';
 281                                         ignore_state_r  <= '0';
 282                                 END IF;
 283                         END IF;
 284                         HAZARD_WRB_r  <= HAZARD_WRB_i;
 285                         MEM_REG_o     <= MEM_REG_i;
 286                         int_busy_r    <= ID2CTRL_i.int_busy;
 287                 END IF;
 288                 -- decode-to-exeq unit registers
 289                 IF ((reset_s = '1') OR (flush_ID2EX_s = '1')) THEN
 290                         setup_int_r <= '0';
 291                         lp_rst_ID2EX_REG;
 292                         delayBit_r <= '0';
 293                 -- check for the need and possibility to handle active interrupt requests
 294                 ELSIF (((int_i = '1') OR (MEM2CTRL_i.int = '1')) AND (MSR_i.IE = '1') AND
 295                                         (ID2CTRL_i.int_busy = '0') AND (int_busy_r = '0') AND
 296                                         -- pending branch should be taken before interrupt can be executed
 297                                         -- dectected by Matthis Meier, TU Dortmund (Sept 2012)
 298                                         --
 299                                         -- Same goes for pending flushing - should be taken before interrupt can be executed
 300                                         (EX2IF_REG_i.take_branch = '0') AND (EX2IF_REG_r.take_branch = '0') AND ((COMPATIBILITY_MODE_g = TRUE)
 301                                         OR ((flush_first_r = '0') AND (flush_second_r = '0') AND (flush_second_2r = '0'))) AND
 302                                         (IMM_LOCK_i.locked = '0') AND (HAZARD_WRB_i.hazard = '0')) THEN
 303                         setup_int_r <= '1';
 304                         ID2EX_REG_r.program_counter <= ID2EX_REG_i.program_counter;
 305                         lp_rst_ID2EX_REG;
 306                 ELSIF (clken_pipe_s = '1') THEN
 307                         setup_int_r <= '0';
 308                         ID2EX_REG_r <= ID2EX_REG_i;
 309                         delayBit_r  <= ID2CTRL_i.delayBit;
 310                 END IF;
 311                 -- exeq-to-mem unit registers
 312                 IF ((reset_s = '1') OR (flush_EX2MEM_s = '1')) THEN
 313                         lp_rst_EX2IF_REG;
 314                         lp_rst_EX2MEM_REG;
 315                         lp_rst_EX_WRB;
 316                         lp_rst_IMM_LOCK;
 317                 ELSE
 318                         IF (clken_pipe_s = '1') THEN
 319                                 EX2IF_REG_r   <= EX2IF_REG_i;
 320                                 EX_WRB_o      <= EX_WRB_i;
 321                         END IF;
 322                         IF (clken_s = '1') THEN
 323                                 -- next test to prevent a flush from disrupting
 324                                 -- the write-back pipeline
 325                                 IF (flush_ID2EX_r = '0') THEN
 326                                         EX2MEM_REG_o <= EX2MEM_REG_i;
 327                                 END IF;
 328                                 IMM_LOCK_r <= IMM_LOCK_i;
 329                                 MSR_o      <= MSR_i;
 330                         END IF;
 331                 END IF;
 332         ELSE
 333                 IF MEM_REG_i.wrb_Action = WRB_MEM THEN
 334                         IF MEM2CTRL_i.bus_wait = '0' THEN
 335                                 MEM_REG_o.wrb_Action  <= NO_WRB;
 336                                 MEM_REG_o.wrix_rD     <= (OTHERS => '0');
 337                         ELSIF MEM2CTRL_i.bus_taken = '1' THEN
 338                                 repeat_mem_r  <= '1';
 339                         ELSE
 340                                 repeat_mem_r  <= '0';
 341                         END IF;
 342                 ELSE
 343                         repeat_mem_r  <= '0';
 344                 END IF;
 345         END IF;     -- rising edge clk_i ...
 346         END PROCESS regd_proc;
 347
 348 END ARCHITECTURE rtl;