TUMBL testbed updated to be closer to concurrent extmem access situation.

Signed-off-by: Pavel Pisa <ppisa@pikron.com>

diff --git a/hw/tb/Makefile b/hw/tb/Makefile
index 84e51f87c213787c4b2bd3102460a58ab69d1ba5..b1c93a4829f5adb5a48c5614c40161abc7d0eabe 100644 (file)
--- a/hw/tb/Makefile
+++ b/hw/tb/Makefile
@@ -38,11 +38,11 @@ imem.bits : imem.bin convert_bin2bits
 
 test-tumbl: analyze-all imem.bits
        $(GHDL) $(GHDLFLAGS) -m $(ANALYZEFLAGS) lx_tumbl_tb
-       $(GHDL) $(GHDLFLAGS) -r  lx_tumbl_tb --stop-time=10000ns --vcd=$@.vcd
+       $(GHDL) $(GHDLFLAGS) -r  lx_tumbl_tb --stop-time=10000ns --vcd=$@.vcd --wave=$@.ghw
 
 test-rocon: analyze-all
        $(GHDL) $(GHDLFLAGS) -m $(ANALYZEFLAGS) lx_rocon_top_tb
-       $(GHDL) $(GHDLFLAGS) -r lx_rocon_top_tb --stop-time=10000ns --vcd=$@.vcd
+       $(GHDL) $(GHDLFLAGS) -r lx_rocon_top_tb --stop-time=10000ns --vcd=$@.vcd --wave=$@.ghw
 
 analyze-all: $(SRC)
        $(GHDL) $(GHDLFLAGS) -a $(ANALYZEFLAGS) $(SRC)

diff --git a/hw/tb/lx_tumbl_tb.vhd b/hw/tb/lx_tumbl_tb.vhd
index f816fa8f1fb523075810c422867180fbf47f8758..66a1652a24d2c338d8ec9a9f7d23a900912aa0af 100644 (file)
--- a/hw/tb/lx_tumbl_tb.vhd
+++ b/hw/tb/lx_tumbl_tb.vhd
@@ -49,6 +49,9 @@ ARCHITECTURE behavior OF lx_tumbl_tb IS
        signal imem_ready_s   : std_logic := '0';
        signal imem_fill_addr_s : natural range 0 to 2**8-1 := 0;
 
+       -- Simulate special events and interactions
+       signal delay_access_s : std_logic := '0';
+
 BEGIN
        -- Instantiate the Unit Under Test (UUT)
    uut: lx_rocon_tumbl
@@ -141,28 +144,30 @@ BEGIN
 
        end process;
 
-       xmemb_process :process
-               variable xmemb_addr_v : std_logic_vector(14 downto 0);
-               variable my_line : LINE;
-               variable delay_access_v : std_logic;
+       events_process: process(cycle_cnt)
        begin
-               wait until clk_cpu'event and clk_cpu = '1';
-
                -- Enable clken only when available for Tumbl
                if cycle_cnt >= 34 and cycle_cnt <= 34 then
-                       delay_access_v := '1';
+                       delay_access_s <= '1';
                else
-                       delay_access_v := '0';
+                       delay_access_s <= '0';
                end if;
+       end process;
 
-               xmemb_i_s.clken <= not delay_access_v;
+       xmemb_i_s.clken <= not delay_access_s;
+
+       xmemb_process :process
+               variable xmemb_addr_v : std_logic_vector(14 downto 0);
+               variable my_line : LINE;
+       begin
+               wait until clk_cpu'event and clk_cpu = '1';
 
                xmemb_i_s.data  <= (others => 'X');
 
                xmemb_addr_v := xmemb_o_s.addr;
 
                if xmemb_o_s.rd = '1' then
-                       if delay_access_v = '1' then
+                       if delay_access_s = '1' then
                                xmemb_i_s.data(31 downto 16) <= x"F0F0";
                        else
                                xmemb_i_s.data(31 downto 16) <= x"ACCE";