RoCoN: Select higher interrupt priority for LXPWM master receiver interrupt.

The current data acquisition/read from FPGA has to be finished
in less than 50 usec and other interrupts can can delay
this processing. The receiver interrupt LXPWR_RX_IRQn
is mapped to interrupt TIMER2_IRQn and its priority
is increased.

Signed-off-by: Pavel Pisa <ppisa@pikron.com>

diff --git a/sw/app/rocon/appl_main.c b/sw/app/rocon/appl_main.c
index e6b2cf43efdceb046a9ef53386f25f223dbfa078..b5775ece756c3839abd8bbf2f1ef8d539981c62e 100644 (file)
--- a/sw/app/rocon/appl_main.c
+++ b/sw/app/rocon/appl_main.c
@@ -281,6 +281,9 @@ int main()
   /* Higher priority for SPI to gradient valves */
   NVIC->IP[SSP1_IRQn] = 0x40;
 
+  /* LXPWR master receive interrupt (deadline under 50 usec) */
+  NVIC->IP[TIMER2_IRQn] = 0x30;
+
   /* Start of the cam period */
   NVIC->IP[MCPWM_IRQn] = 0x20;