RoCoN: Extend read cycle to ensure that even data from concurrently changed register...

Signed-off-by: Pavel Pisa <ppisa@pikron.com>

diff --git a/sw/app/rocon/appl_fpga.c b/sw/app/rocon/appl_fpga.c
index 51385d0e18f0e385d860fcc3e702b84b5b4ba978..0a65e9fe71634869281ea886b13f7d5b6177b96b 100644 (file)
--- a/sw/app/rocon/appl_fpga.c
+++ b/sw/app/rocon/appl_fpga.c
@@ -92,7 +92,7 @@ void fpga_init()
   LPC_EMC->StaticConfig0 = 0x00000002;
 
   /* Delays - not measured at this point
-   * We're running on 72 MHz, FPGA bus is running on 100 MHz async.
+   * We're running on 72 MHz, FPGA bus is running on 50 MHz async.
    * Read: 32 cycles
    * Write: 33 cycles
    * Turnaround: 2 cycles (cca. 28 ns)
@@ -446,7 +446,7 @@ int fpga_configure()
   /* Use EMC delays obtained through measurement */
   LPC_EMC->StaticWaitWr0 =   0x02;
   LPC_EMC->StaticWaitWen0 =  0x01;
-  LPC_EMC->StaticWaitRd0 =   0x06;
+  LPC_EMC->StaticWaitRd0 =   0x08;
   LPC_EMC->StaticWaitPage0 = 0x07;
   LPC_EMC->StaticWaitOen0 =  0x01;
   LPC_EMC->StaticWaitTurn0 = 0x01;