- -- Simulate externall access to xmem bus shared with Tumbl
- if cycle_cnt >= 33 and cycle_cnt <= 33 then
- -- if xmemb_sel_s = '1' and (delay_access_r = '0' or delay_access_r2 = '0') then
- delay_access_s <= '1';
- else
- delay_access_s <= '0';
- end if;
+
+ wait until clk_cpu'event and clk_cpu = '1' and imem_ready_s = '1';
+
+ -- Simulate external master accesses to Tumbl shared xmem bus
+ xmem_loop: loop
+ wait until clk_cpu'event and clk_cpu = '1';
+ wait until clk_cpu'event and clk_cpu = '1';
+ wait until clk_cpu'event and clk_cpu = '1';
+ wait until clk_cpu'event and clk_cpu = '1';
+ wait until clk_cpu'event and clk_cpu = '1';
+ delay_access_s <= transport '1' after 2 ns;
+ wait until clk_cpu'event and clk_cpu = '1';
+ wait until clk_cpu'event and clk_cpu = '1';
+ delay_access_s <= transport '0' after 2 ns;
+ end loop xmem_loop;
+