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Set of VHDL design workaround to allow whole design compile by GHDL.
authorPavel Pisa <ppisa@pikron.com>
Tue, 30 Dec 2014 08:45:15 +0000 (09:45 +0100)
committerPavel Pisa <ppisa@pikron.com>
Tue, 30 Dec 2014 08:45:15 +0000 (09:45 +0100)
commit4b513bd3c8bee6d484243ca69b0c7eedc2b8cfa3
tree0f82a1e3ad9cee578a9ae977d1748a6fd12a6d4ctree | snapshot
parentb41d0db766da8c95205a756595c1d254572ba07ccommit | diff
Set of VHDL design workaround to allow whole design compile by GHDL.

IRC subsystem is removed from lx_rocon_top.vhd because its inclusion
causes exception in GHDL.

Signed-off-by: Pavel Pisa <ppisa@pikron.com>
hw/bus_irc.vhd diff | blob | history
hw/irc_proc_main.vhd diff | blob | history
hw/lx_rocon_pkg.vhd diff | blob | history
hw/lx_rocon_top.vhd diff | blob | history
hw/tb/Makefile diff | blob | history
hw/xilinx_dualport_bram.vhd diff | blob | history
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