--
type IRC_STATE_OUTPUT_Type is record
ab_error : std_logic;
+ index : std_logic;
index_event : std_logic;
mark : std_logic;
end record;
-- Outputs
qcount_o : out std_logic_vector(7 downto 0);
qcount_index_o : out std_logic_vector(7 downto 0);
+ index_o : out std_logic;
index_event_o : out std_logic;
index_event2_o : out std_logic;
a_rise_o, a_fall_o : out std_logic;
);
end component;
- -- D sampler
- component dff
+ -- D sampler (filtered, 2 cycles)
+ component dff2
port
(
clk_i : in std_logic;
- reset_i : in std_logic;
d_i : in std_logic;
q_o : out std_logic
);
end component;
- -- D sampler (filtered)
- component dff2
+ -- D sampler (filtered, 3 cycles)
+ component dff3
port
(
clk_i : in std_logic;
- reset_i : in std_logic;
d_i : in std_logic;
q_o : out std_logic
);
end component;
+ -- CRC8
component crc
port
(
);
end component;
- -- LX Master
+ -- Counter - divider
+ component cnt_div
+ generic (
+ cnt_width_g : natural := 8
+ );
+ port
+ (
+ clk_i : in std_logic;
+ en_i : in std_logic;
+ reset_i : in std_logic;
+ ratio_i : in std_logic_vector(cnt_width_g-1 downto 0);
+ q_out_o : out std_logic
+ );
+ end component;
+
+ -- LX Master transmitter
component lxmaster_transmitter
+ generic (
+ cycle_cnt_width_g : natural := 12
+ );
port
(
clk_i : in std_logic;
sync_o : out std_logic;
-- Register
register_i : in std_logic;
- register_o : out std_logic;
+ register_o : out std_logic_vector(1 downto 0);
register_we_i : in std_logic;
+ -- Cycle period
+ cycle_reg_i : in std_logic_vector(cycle_cnt_width_g-1 downto 0);
+ cycle_reg_o : out std_logic_vector(cycle_cnt_width_g-1 downto 0);
+ cycle_reg_we_i : in std_logic;
+ -- Watchdog
+ wdog_i : in std_logic;
+ wdog_we_i : in std_logic;
-- BRAM access
mem_clk_i : in std_logic;
mem_en_i : in std_logic;
);
end component;
+ -- LX Master receiver
+ component lxmaster_receiver
+ port
+ (
+ clk_i : in std_logic;
+ reset_i : in std_logic;
+ -- Transmision
+ clock_i : in std_logic;
+ miso_i : in std_logic;
+ sync_i : in std_logic;
+ -- Receive done pulse
+ rx_done_o : out std_logic;
+ -- Register
+ register_i : in std_logic;
+ register_o : out std_logic_vector(1 downto 0);
+ register_we_i : in std_logic;
+ -- BRAM access
+ mem_clk_i : in std_logic;
+ mem_en_i : in std_logic;
+ mem_we_i : in std_logic_vector(1 downto 0);
+ mem_addr_i : in std_logic_vector(8 downto 0);
+ mem_data_i : in std_logic_vector(15 downto 0);
+ mem_data_o : out std_logic_vector(15 downto 0)
+ );
+ end component;
+
+ -- LX math functions approximation
+
+ component lx_fncapprox
+ port
+ (
+ clk_i : in std_logic;
+ reset_i : in std_logic;
+ -- Data bus
+ address_i : in std_logic_vector(4 downto 0);
+ next_ce_i : in std_logic;
+ data_i : in std_logic_vector(31 downto 0);
+ data_o : out std_logic_vector(31 downto 0);
+ --
+ bls_i : in std_logic_vector(3 downto 0)
+ );
+ end component;
+
+ -- Clock Cross Domain Synchronization Elastic Buffer/FIFO
+ component lx_crosdom_ser_fifo
+ generic
+ (
+ fifo_len_g : positive := 8;
+ sync_adj_g : integer := 0
+ );
+ port
+ (
+ -- Asynchronous clock domain interface
+ acd_clock_i : in std_logic;
+ acd_miso_i : in std_logic;
+ acd_sync_i : in std_logic;
+ -- Clock
+ clk_i : in std_logic;
+ reset_i : in std_logic;
+ -- Output synchronous with clk_i
+ miso_o : out std_logic;
+ sync_o : out std_logic;
+ data_ready_o : out std_logic
+ );
+ end component;
+
--------------------------------------------------------------------------------
-- TUMBL
--------------------------------------------------------------------------------
clk_i : in std_logic;
rst_i : in std_logic;
clken_i : in std_logic;
+ gprf_finish_wrb_mem_i : in std_logic;
--
ID2GPRF_i : in ID2GPRF_Type;
MEM_WRB_i : in WRB_Type;
clk_i : in std_logic;
reset_i : in std_logic;
-- Data bus
- address_i : in std_logic_vector(9 downto 0);
+ address_i : in std_logic_vector(10 downto 0);
next_ce_i : in std_logic;
data_i : in std_logic_vector(15 downto 0);
data_o : out std_logic_vector(15 downto 0);
--
bls_i : in std_logic_vector(1 downto 0);
+ --
+ rx_done_o : out std_logic;
-- Signals for LX Master
- mosi_o : out std_logic;
+ clock_i : in std_logic;
+ miso_i : in std_logic;
+ sync_i : in std_logic;
+ --
clock_o : out std_logic;
+ mosi_o : out std_logic;
sync_o : out std_logic
);
end component;
--------------------------------------------------------------------------------
-- BRAM
--------------------------------------------------------------------------------
+ type BRAM_type is (READ_FIRST, WRITE_FIRST, NO_CHANGE);
- component xilinx_dualport_bram_write_first
- generic
- (
- byte_width : positive := 8;
- address_width : positive := 8;
- we_width : positive := 4
- );
- port
- (
- clka : in std_logic;
- rsta : in std_logic;
- ena : in std_logic;
- wea : in std_logic_vector((we_width-1) downto 0);
- addra : in std_logic_vector((address_width-1) downto 0);
- dina : in std_logic_vector(((byte_width*we_width)-1) downto 0);
- douta : out std_logic_vector(((byte_width*we_width)-1) downto 0);
- clkb : in std_logic;
- rstb : in std_logic;
- enb : in std_logic;
- web : in std_logic_vector((we_width-1) downto 0);
- addrb : in std_logic_vector((address_width-1) downto 0);
- dinb : in std_logic_vector(((byte_width*we_width)-1) downto 0);
- doutb : out std_logic_vector(((byte_width*we_width)-1) downto 0)
- );
- end component;
-
- component xilinx_dualport_bram_no_change
+ component xilinx_dualport_bram
generic
(
byte_width : positive := 8;
address_width : positive := 8;
- we_width : positive := 4
+ we_width : positive := 4;
+ port_a_type : BRAM_type := READ_FIRST;
+ port_b_type : BRAM_type := READ_FIRST
);
port
(
projects / fpga / lx-cpu1 / lx-rocon.git / blobdiff