#include <LPC17xx.h>
#include <lpcTIM.h>
#include <spi_drv.h>
+#include <pxmc.h>
+#include <inttypes.h>
#include <ul_log.h>
#include <ul_logreg.h>
#include "appl_defs.h"
#include "appl_fpga.h"
+#include "pxmcc_types.h"
+#include "pxmcc_interface.h"
int cmd_do_test_memusage(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
{
int cmd_do_testlxpwrrx(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
{
+ char *ps = param[1];
+ long mode = 0;
+ uint32_t *ptr;
+
+ if (ps != NULL) {
+ si_skspace(&ps);
+ if (*ps) {
+ if (si_ulong(&ps, &mode, 0) < 0)
+ return -CMDERR_BADPAR;
+ }
+ }
pxmc_rocon_rx_data_hist_buff = NULL;
+ pxmc_rocon_rx_data_hist_mode = mode;
+
#ifndef PXMC_ROCON_TIMED_BY_RX_DONE
pxmc_rocon_rx_done_isr_setup(pxmc_rocon_rx_done_isr);
#endif /*PXMC_ROCON_TIMED_BY_RX_DONE*/
pxmc_rocon_rx_data_hist_buff_end = (void *)(FPGA_CONFIGURATION_FILE_ADDRESS +
0x80000);
- pxmc_rocon_rx_data_hist_buff = (void *)FPGA_CONFIGURATION_FILE_ADDRESS;
+ ptr = (void *)FPGA_CONFIGURATION_FILE_ADDRESS;
+ if (mode != 0) {
+ *(ptr++) = '10XL';
+ *(ptr++) = mode;
+ }
+ pxmc_rocon_rx_data_hist_buff = (void *)ptr;
return 0;
}
return 0;
}
+#include <math.h>
+
int cmd_do_testfncapprox(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
{
char *ps = param[1];
+ unsigned long fnc;
unsigned long val;
unsigned long res;
long diff;
+ long diff_max = 0;
unsigned int xb;
uint32_t x;
uint32_t xl;
- uint64_t yl;
+ double xf;
+ int64_t yl;
+ long count = 1;
+ long step = 1 << (30-7-18+1 +4);
+
+ si_skspace(&ps);
+ if (si_ulong(&ps, &fnc, 0) < 0)
+ return -CMDERR_BADPAR;
+
+ si_skspace(&ps);
+ if (!strcmp(ps, "all")) {
+ val = 0;
+ count = 0x80000000UL / step;
+ if (fnc == 1) {
+ val = 1;
+ }
+ } else {
+ if (si_ulong(&ps, &val, 0) < 0)
+ return -CMDERR_BADPAR;
+ }
+
+ for (; count--; val += step) {
+
+ if (fnc == 1) {
+ x = val;
+ xb = __builtin_clz(x);
+ xl = x << xb;
+ } else {
+ xl = val;
+ }
+
+ fpga_fncapprox_base[fnc] = xl;
+
+ /* dummy read to provide time to function aproximator to proceed computation */
+ res = fpga_fncapprox_base[fnc];
+ res = fpga_fncapprox_base[fnc];
+
+ switch (fnc) {
+ case 0:
+ yl = xl;
+ case 1:
+ yl = (1LL << 62) / xl;
+ break;
+ case 2:
+ xf = (double)xl * M_PI / 2.0 / (1UL << 30);
+ yl = round(sin(xf) * (1UL << 16));
+ break;
+ case 3:
+ xf = (double)xl * M_PI / 2.0 / (1UL << 30);
+ yl = round(cos(xf) * (1UL << 16));
+ break;
+ default:
+ yl = 0;
+ }
+
+ diff = yl - res;
+
+ if ((diff > 0) && (diff > diff_max))
+ diff_max = diff;
+ else if ((diff < 0) && (-diff > diff_max))
+ diff_max = -diff;
+
+ }
+
+ val -= step;
+
+ printf("fnc=%ld val=0x%08lx res=0x%08lx ref=0x%08lx diff=%ld max %ld\n",
+ fnc, val, res, (unsigned long)yl, diff, diff_max);
+
+ return 0;
+}
+
+int cmd_do_testtumblefw(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
+{
+ char *ps = param[1];
+ long pwm_d;
+ long pwm_q;
+ pxmc_state_t *mcs = pxmc_main_list.pxml_arr[0];
+ volatile pxmcc_data_t *mcc_data = pxmc_rocon_mcc_data();
+
+ pxmcc_axis_enable(mcs, 0);
si_skspace(&ps);
- if (si_ulong(&ps, &val, 0) < 0)
+ if (si_long(&ps, &pwm_d, 0) < 0)
return -CMDERR_BADPAR;
- x = val;
- xb = __builtin_clz(x);
- xl = x << xb;
+ si_skspace(&ps);
+ if (si_ulong(&ps, &pwm_q, 0) < 0)
+ return -CMDERR_BADPAR;
+
+
+ if (0) {
+ pxmcc_axis_setup(mcs, PXMCC_MODE_BLDC);
+ }
+ pxmc_clear_flags(mcs,PXMS_ENO_m|PXMS_ENG_m|PXMS_ENR_m|PXMS_BSY_m);
+ pxmcc_axis_pwm_dq_out(mcs, pwm_d, pwm_q);
+ pxmcc_axis_enable(mcs, 1);
+
+ if (0) {
+ mcc_data->axis[1].inp_info = 0;
+ mcc_data->axis[1].out_info = 3;
+ mcc_data->axis[1].pwmtx_info = (12 << 0) | (13 << 8) | (14 << 16);
+ mcc_data->axis[1].mode = PXMCC_MODE_BLDC;
+ mcc_data->axis[1].ccflg = 1;
+ mcc_data->axis[2].inp_info = 0;
+ mcc_data->axis[2].out_info = 6;
+ mcc_data->axis[2].pwmtx_info = (15 << 0) | (16 << 8) | (18 << 16);
+ mcc_data->axis[2].mode = PXMCC_MODE_BLDC;
+ mcc_data->axis[2].ccflg = 1;
+ mcc_data->axis[3].inp_info = 0;
+ mcc_data->axis[3].out_info = 9;
+ mcc_data->axis[3].pwmtx_info = (19 << 0) | (20 << 8) | (21 << 16);
+ mcc_data->axis[3].mode = PXMCC_MODE_BLDC;
+ mcc_data->axis[3].ccflg = 1;
+ }
+
+ printf("spd %ld act_idle %"PRIu32" min_idle %"PRIu32" avail %lu pwm_cycle %"PRIu32"\n",
+ mcs->pxms_as, mcc_data->common.act_idle, mcc_data->common.min_idle,
+ (mcc_data->common.pwm_cycle + 6) / 6, mcc_data->common.pwm_cycle);
+ mcc_data->common.min_idle = 0x7fff;
+
+ return 0;
+}
+
+#define CK_IRC_WORDS 16
+#define CK_TX_WORDS 16
+#define CK_RX_WORDS 16
- *fpga_fncapprox_base = xl;
+#define CK_IRC_START ((uint32_t*)fpga_irc[0])
+#define CK_TX_START (fpga_lx_master_transmitter_base+9)
+#define CK_RX_START (fpga_lx_master_receiver_base+44)
- res = *fpga_fncapprox_base;
+typedef struct ck_state_t {
+ uint32_t ck_irc_base[CK_IRC_WORDS];
+ uint32_t ck_irc_read[CK_IRC_WORDS];
+ uint32_t ck_tx_base[CK_TX_WORDS];
+ uint32_t ck_tx_read[CK_TX_WORDS];
+ uint32_t ck_rx_base[CK_RX_WORDS];
+ uint32_t ck_rx_read[CK_RX_WORDS];
- yl = (1LL << 62) / xl;
+ uint32_t ck_irc_err;
+ uint32_t ck_tx_err;
+ uint32_t ck_rx_err;
+} ck_state_t;
- diff = yl - res;
+int cmd_do_testtumblebus(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
+{
+ int i;
+ int cycles = 10000;
+ static ck_state_t *ckst = NULL;
+ if (ckst == NULL)
+ ckst = malloc(sizeof(*ckst));
+ if (ckst == NULL)
+ return 1;
+
+ ckst->ck_irc_err = 0;
+ ckst->ck_tx_err = 0;
+ ckst->ck_rx_err = 0;
+
+ for (i = 0; i < CK_IRC_WORDS; i++)
+ ckst->ck_irc_base[i] = CK_IRC_START[i];
+
+ for (i = 0; i < CK_TX_WORDS; i++)
+ ckst->ck_tx_base[i] = CK_TX_START[i];
+
+ for (i = 0; i < CK_RX_WORDS; i++)
+ ckst->ck_rx_base[i] = CK_RX_START[i];
+
+ while (cycles--) {
+ if (!ckst->ck_irc_err) {
+ for (i = 0; i < CK_IRC_WORDS; i++)
+ ckst->ck_irc_read[i] = CK_IRC_START[i];
+ for (i = 0; i < CK_IRC_WORDS; i++)
+ if (ckst->ck_irc_read[i] != ckst->ck_irc_base[i]) {
+ ckst->ck_irc_err++;
+ printf("irc+%x %08"PRIx32" != %08"PRIx32"\n",
+ i, ckst->ck_irc_read[i], ckst->ck_irc_base[i]);
+ }
+ }
- printf("val=0x%08lx res=0x%08lx ref=0x%08lx diff=%ld\n",
- val, res, (unsigned long)yl, diff);
+ if (!ckst->ck_tx_err) {
+ for (i = 0; i < CK_TX_WORDS; i++)
+ ckst->ck_tx_read[i] = CK_TX_START[i];
+ for (i = 0; i < CK_TX_WORDS; i++)
+ if (ckst->ck_tx_read[i] != ckst->ck_tx_base[i]) {
+ ckst->ck_tx_err++;
+ printf("tx+%x %08"PRIx32" != %08"PRIx32"\n",
+ i, ckst->ck_tx_read[i], ckst->ck_tx_base[i]);
+ }
+ }
+
+ if (!ckst->ck_rx_err) {
+ for (i = 0; i < CK_RX_WORDS; i++)
+ ckst->ck_rx_read[i] = CK_RX_START[i];
+ for (i = 0; i < CK_RX_WORDS; i++)
+ if (ckst->ck_rx_read[i] != ckst->ck_rx_base[i]) {
+ ckst->ck_rx_err++;
+ printf("rx+%x %08"PRIx32" != %08"PRIx32"\n",
+ i, ckst->ck_rx_read[i], ckst->ck_rx_base[i]);
+ }
+ }
+ }
return 0;
}
cmd_do_testfncapprox, {(void *)0}
};
+cmd_des_t const cmd_des_testtumblefw = {0, 0,
+ "testtumblefw", "test Tumble coprocesor firmware",
+ cmd_do_testtumblefw, {(void *)0}
+ };
+
+cmd_des_t const cmd_des_testtumblebus = {0, 0,
+ "testtumblebus", "test Tumble coprocesor bus",
+ cmd_do_testtumblebus, {(void *)0}
+ };
+
+
cmd_des_t const *const cmd_appl_tests[] =
{
&cmd_des_test_memusage,
&cmd_des_testlxpwrrx,
&cmd_des_testlxpwrstat,
&cmd_des_testfncapprox,
+ &cmd_des_testtumblefw,
+ &cmd_des_testtumblebus,
NULL
};
projects / fpga / lx-cpu1 / lx-rocon.git / blobdiff