RoCoN: add definition of LX Master register for PWM cycle period configuration.

[fpga/lx-cpu1/lx-rocon.git] / sw / app / rocon / appl_fpga.c

diff --git a/sw/app/rocon/appl_fpga.c b/sw/app/rocon/appl_fpga.c
index 1e33fd1e88e09749b0446817088303b7a07fbe94..cfd136dc26a306a42ec298ea5f4c1ce200b79ad6 100644 (file)
--- a/sw/app/rocon/appl_fpga.c
+++ b/sw/app/rocon/appl_fpga.c
@@ -62,6 +62,7 @@ volatile uint32_t *fpga_bus_meas_write2 = (volatile uint32_t *)0x80007FFC;
 volatile uint32_t *fpga_lx_master_transmitter_base = (volatile uint32_t *)FPGA_LX_MASTER_TRANSMITTER_BASE;
 volatile uint32_t *fpga_lx_master_transmitter_reg = (volatile uint32_t *)FPGA_LX_MASTER_TRANSMITTER_REG;
 volatile uint32_t *fpga_lx_master_transmitter_wdog = (volatile uint32_t *)FPGA_LX_MASTER_TRANSMITTER_WDOG;
+volatile uint32_t *fpga_lx_master_transmitter_cycle = (volatile uint32_t *)FPGA_LX_MASTER_TRANSMITTER_CYCLE;
 volatile uint32_t *fpga_lx_master_receiver_base = (volatile uint32_t *)FPGA_LX_MASTER_RECEIVER_BASE;
 volatile uint32_t *fpga_lx_master_receiver_reg = (volatile uint32_t *)FPGA_LX_MASTER_RECEIVER_REG;
 volatile uint32_t *fpga_lx_master_reset = (volatile uint32_t *)FPGA_LX_MASTER_RESET;