RoCoN: Include SDRAM test into command processor.

[fpga/lx-cpu1/lx-rocon.git] / sw / app / rocon / appl_tests.c

diff --git a/sw/app/rocon/appl_tests.c b/sw/app/rocon/appl_tests.c
index 5692ee0ebcb2c1e480d743793e73c9afbcf36335..cffe66f9c76acf3c9952417802367f0d2385bf4e 100644 (file)
--- a/sw/app/rocon/appl_tests.c
+++ b/sw/app/rocon/appl_tests.c
@@ -142,6 +142,96 @@ int cmd_do_spimst_blocking(cmd_io_t *cmd_io, const struct cmd_des *des, char *pa
   return 0;
 }
 
+#ifdef SDRAM_BASE
+int sdram_access_test(void)
+{
+  unsigned int *ptr;
+  unsigned int pattern;
+  size_t ramsz = SDRAM_SIZE;
+  size_t cnt;
+  lt_mstime_t tic;
+  size_t blksz, i;
+
+  lt_mstime_update();
+  tic = actual_msec;
+
+  pattern = 0x12abcdef;
+  for (cnt = ramsz/sizeof(*ptr), ptr = (typeof(ptr))SDRAM_BASE; cnt--;) {
+    *(ptr++) = pattern;
+    pattern = pattern + 0x87654321;
+  }
+
+  lt_mstime_update();
+  printf("SDRAM write %d ms\n", (int)(lt_msdiff_t)(actual_msec - tic));
+
+  lt_mstime_update();
+  tic = actual_msec;
+
+  pattern = 0x12abcdef;
+  for (cnt = ramsz/sizeof(*ptr), ptr = (typeof(ptr))SDRAM_BASE; cnt--;) {
+    if(*ptr != pattern) {
+      printf("SDRAM error modify at %p (%08x)\n", ptr, *ptr ^ pattern);
+      return -1;
+    }
+    *(ptr++) = ~pattern;
+    pattern = pattern + 0x87654321;
+  }
+
+  lt_mstime_update();
+  printf("SDRAM modify %d ms\n", (int)(lt_msdiff_t)(actual_msec - tic));
+
+  lt_mstime_update();
+  tic = actual_msec;
+
+  pattern = 0x12abcdef;
+  for (cnt = ramsz/sizeof(*ptr), ptr = (typeof(ptr))SDRAM_BASE; cnt--;) {
+    if(*(ptr++) != ~pattern) {
+      printf("SDRAM error read at %p (%08x)\n", ptr, *ptr ^ pattern);
+      return -1;
+    }
+    pattern = pattern + 0x87654321;
+  }
+
+  lt_mstime_update();
+  printf("SDRAM read %d ms\n", (int)(lt_msdiff_t)(actual_msec - tic));
+
+  lt_mstime_update();
+  tic = actual_msec;
+
+  pattern = 0;
+  for (cnt = ramsz/sizeof(*ptr), ptr = (typeof(ptr))SDRAM_BASE; cnt--;) {
+    pattern += *(ptr++);
+  }
+
+  lt_mstime_update();
+  printf("SDRAM sum %d ms res 0x%08x\n", (int)(lt_msdiff_t)(actual_msec - tic), pattern);
+
+  for (blksz=1; blksz < 256 ; blksz *= 2) {
+    lt_mstime_update();
+    tic = actual_msec;
+
+    pattern = 0;
+    for (cnt = ramsz/sizeof(*ptr); cnt; cnt -= blksz) {
+      ptr = (typeof(ptr))SDRAM_BASE;
+      //ptr = (typeof(ptr))cmd_do_test_memusage;
+      //ptr = (typeof(ptr))&ptr;
+      for (i = blksz; i--; )
+        pattern += *(ptr++);
+    }
+    lt_mstime_update();
+    printf("SDRAM sum %d blksz %d ms res 0x%08x\n", (int)(lt_msdiff_t)(actual_msec - tic), (int)blksz, pattern);
+  }
+
+  return 0;
+}
+
+int cmd_do_testsdram(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
+{
+  sdram_access_test();
+  return 0;
+}
+#endif /*SDRAM_BASE*/
+
 cmd_des_t const cmd_des_test_memusage={0, 0,
                         "memusage","report memory usage",cmd_do_test_memusage,
                         {0,
@@ -176,6 +266,12 @@ cmd_des_t const cmd_des_spimstx={0, CDESM_OPCHR|CDESM_WR,
                        "SPIMST#","SPI# master communication request",
                        cmd_do_spimst_blocking,{(void*)-1}};
 
+#ifdef SDRAM_BASE
+cmd_des_t const cmd_des_testsdram={0, 0,
+                       "testsdram","test SDRAM",
+                       cmd_do_testsdram,{(void*)0}};
+#endif /*SDRAM_BASE*/
+
 cmd_des_t const *const cmd_appl_tests[]={
   &cmd_des_test_memusage,
   &cmd_des_test_adc,
@@ -186,5 +282,8 @@ cmd_des_t const *const cmd_appl_tests[]={
   &cmd_des_test_loglevel,
   &cmd_des_spimst,
   &cmd_des_spimstx,
+ #ifdef SDRAM_BASE
+  &cmd_des_testsdram,
+ #endif /*SDRAM_BASE*/
   NULL
 };