Testbed for receiver CRC processing check.

[fpga/lx-cpu1/lx-rocon.git] / hw / tb / lx_rocon_top_tb.vhd

diff --git a/hw/tb/lx_rocon_top_tb.vhd b/hw/tb/lx_rocon_top_tb.vhd
index f8e64edb5f8bd193078f993e5964f5c3c29f647e..a9ecdf3e3728e7bd40c68289ab4d1440f74f4a44 100644 (file)
--- a/hw/tb/lx_rocon_top_tb.vhd
+++ b/hw/tb/lx_rocon_top_tb.vhd
@@ -113,6 +113,9 @@ ARCHITECTURE behavior OF lx_rocon_top_tb IS
         signal s1_mosi : std_logic := '1';
         signal s1_sync_out : std_logic := '1';
 
+       signal s1_data : std_logic := '1';
+       signal s1_sync_in_prev : std_logic := '1';
+
         --BiDirs
    signal data : std_logic_vector(31 downto 0);
 
@@ -267,4 +270,17 @@ BEGIN
 
        end process;
 
+       s1_clk_in <= s1_clk_out;
+
+       connect_s1_process : process
+       begin
+               wait until s1_clk_out'event and s1_clk_out = '0';
+               wait for 10 ns;
+
+               s1_data <= s1_mosi;
+               s1_miso <= s1_data;
+               s1_sync_in <= not s1_sync_out or s1_sync_in_prev;
+               s1_sync_in_prev <= not s1_sync_out;
+       end process;
+
 END;