Testbed for receiver CRC processing check.

[fpga/lx-cpu1/lx-rocon.git] / hw / tb / firmware-for-rx-crc / start.S

diff --git a/hw/tb/firmware-for-rx-crc/start.S b/hw/tb/firmware-for-rx-crc/start.S
new file mode 100644 (file)
index 0000000..065542f
--- /dev/null
+++ b/hw/tb/firmware-for-rx-crc/start.S
@@ -0,0 +1,29 @@
+/* LX ROCON firmware reduced startup file */
+
+.globl _main
+.align 2
+
+_main:
+
+       /* Stack pointer */
+       addi     r1, r0, 0xFFC
+
+       /* reset data */
+       addi     r6, r0, _sdata
+       addi     r7, r0, _edata
+       rsub     r18, r6, r7
+       brci     le, r18, .Lenddata
+.Lloopdata:
+       swi      r0, r6, 0
+       addi     r6, r6, 4
+       rsub     r18, r6, r7
+       brci     gt, r18, .Lloopdata
+.Lenddata:
+       /* Init default values */
+       brli     r15, init_defvals
+
+       /* Run program */
+       brli     r15, main
+
+       /* End of program */
+       halt     0