IRC input: simplify and remove dependency on ieee.std_logic_arith.all and work.mbl_pk...

[fpga/lx-cpu1/lx-rocon.git] / hw / irc_proc_main.vhd

diff --git a/hw/irc_proc_main.vhd b/hw/irc_proc_main.vhd
index 092ae142eeb898f343c0ca09df7fbdd8ebdb0c66..8bec00523d07be7cbc3d3e6bc81f42bdcc56947b 100644 (file)
--- a/hw/irc_proc_main.vhd
+++ b/hw/irc_proc_main.vhd
@@ -2,7 +2,6 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.std_logic_unsigned.all;
 use ieee.numeric_std.all;
-use work.mbl_pkg.all;
 use work.util_pkg.all;
 use work.lx_rocon_pkg.all;
 
@@ -46,10 +45,14 @@ architecture Behavioral of irc_proc_main is
        signal ram_write_s  : std_logic_vector(3 downto 0);
        signal ram_data_i_s : std_logic_vector(31 downto 0);
        signal ram_data_o_s : std_logic_vector(31 downto 0);
+       --
+       signal irc_reg_s    : std_logic_vector(31 downto 0);
+       signal irc_reg_r    : std_logic_vector(31 downto 0);
 
 begin
 
        incr: irc_proc_inc
+       generic map (num_irc_g)
        port map
        (
                clk_i   => clk_i,
@@ -59,12 +62,14 @@ begin
        );
 
        -- FIXME: Template needs to support 1-bit WE enabling, getting KEEP conflicts on wea here
-       ram: xilinx_dualport_bram_no_change
+       ram: xilinx_dualport_bram
        generic map
        (
                we_width      => 4,
                byte_width    => 8,
-               address_width => ram_addr_s'length
+               address_width => ram_addr_s'length,
+               port_a_type   => READ_FIRST,
+               port_b_type   => READ_FIRST
        )
        port map
        (
@@ -90,11 +95,12 @@ begin
        ram_addr_s     <= axis_s & op_s(1);
 
 update:
-       process (irc_i, op_r, axis_r, ram_data_o_s, reset_i)
+       process (irc_i, irc_reg_r, op_r, axis_r, ram_data_o_s, reset_i)
                variable skip_v            : std_logic;
                variable irc_v             : IRC_COUNT_OUTPUT_Type;
                variable res_v             : std_logic_vector(31 downto 0);
                variable count_v           : std_logic_vector(31 downto 0);
+               variable src_v             : std_logic_vector(31 downto 0);
        begin
 
                -- Init (reset the index reset events)
@@ -102,9 +108,11 @@ update:
                ram_en_s          <= '0';
                ram_write_s       <= "0000";
                ram_data_i_s      <= (others => '0');
-
-               count_v     := (others => '0');
-               skip_v      := '1';
+               irc_reg_s         <= irc_reg_r;
+               --
+               count_v           := (others => '0');
+               skip_v            := '1';
+               src_v             := (others => '0');
 
                -- No reset
                if reset_i = '0' then
@@ -115,29 +123,25 @@ update:
                                irc_v := irc_i(to_integer(unsigned(axis_r)));
 
                                if op_r(0) = '0' then
-                                       count_v(7 downto 0) := irc_v.qcount;
-                                       skip_v := '0';
-                               else
-                                       if irc_v.index_event = '1' then
-                                               irc_index_reset_o(to_integer(unsigned(axis_r))) <= '1';
-                                               count_v(7 downto 0) := irc_v.index;
-                                               skip_v := '0';
-                                       end if;
+                                       count_v(7 downto 0)   := irc_v.qcount;
+                                       skip_v                := '0';
+                                       src_v                 := ram_data_o_s;
+                                       irc_reg_s             <= ram_data_o_s;
+                               elsif irc_v.index_event = '1' then
+                                       irc_index_reset_o(to_integer(unsigned(axis_r))) <= '1';
+                                       count_v(7 downto 0)   := irc_v.index;
+                                       skip_v                := '0';
+                                       src_v                 := irc_reg_r;
                                end if;
 
                                if skip_v = '0' then
-                                       -- signed extension
-                                       if count_v(7) = '1' then
-                                               count_v(31 downto 8) := (others => '1');
-                                       else
-                                               count_v(31 downto 8) := (others => '0');
-                                       end if;
 
                                        -- calculate qs8
-                                       ep_add32nc(count_v, not ram_data_o_s, '1', res_v);
+                                       res_v(7 downto 0) := std_logic_vector(unsigned(count_v(7 downto 0)) -
+                                                                             unsigned(src_v(7 downto 0)));
 
                                        -- extend it
-                                       count_v(7 downto 0) := res_v(7 downto 0);
+                                       count_v(7 downto 0)    := res_v(7 downto 0);
 
                                        if res_v(7) = '1' then
                                                count_v(31 downto 8) := (others => '1');
@@ -146,7 +150,7 @@ update:
                                        end if;
 
                                        -- add it back
-                                       ep_add32nc(ram_data_o_s, count_v, '0', res_v);
+                                       res_v := std_logic_vector(unsigned(src_v) + unsigned(count_v));
 
                                        -- store it
                                        ram_en_s     <= '1';
@@ -169,8 +173,14 @@ seq:
        begin
 
                wait until clk_i'event and clk_i = '1';
-               op_r     <= op_s;
-               axis_r   <= axis_s;
+               op_r      <= op_s;
+               axis_r    <= axis_s;
+
+               if reset_i = '1' then
+                       irc_reg_r <= (others => '0');
+               else
+                       irc_reg_r <= irc_reg_s;
+               end if;
 
        end process;