RoCoN: FPGA register for Rx event reduction ration configuration.

[fpga/lx-cpu1/lx-rocon.git] / sw / app / rocon / appl_fpga.h

diff --git a/sw/app/rocon/appl_fpga.h b/sw/app/rocon/appl_fpga.h
index 25c0c3f0728e248f3ecfd1b6e63c39c512f4e049..ad66654ba8ed0f0c69f7fb3f00e157bf2f709008 100644 (file)
--- a/sw/app/rocon/appl_fpga.h
+++ b/sw/app/rocon/appl_fpga.h
@@ -54,6 +54,15 @@ extern volatile struct irc_register *fpga_irc8;
 
 extern volatile struct irc_register *fpga_irc[8];
 
+/* Masks */
+#define FPGA_IRC_STATE_MARK_MASK              0x00000001
+#define FPGA_IRC_STATE_AB_ERROR_MASK          0x00000002
+#define FPGA_IRC_STATE_INDEX_EVENT_MASK       0x00000004
+#define FPGA_IRC_STATE_INDEX_MASK             0x00000008
+
+#define FPGA_IRC_STATE_RESET_AB_ERROR_MASK    0x00000002
+#define FPGA_IRC_STATE_RESET_INDEX_EVENT_MASK 0x00000004
+
 extern volatile uint8_t *fpga_irc1_state;
 extern volatile uint8_t *fpga_irc2_state;
 extern volatile uint8_t *fpga_irc3_state;
@@ -69,15 +78,37 @@ extern volatile uint8_t *fpga_irc_reset;
 
 /* LX Master */
 
+#if 0 /* FPGA design version 2 */
 #define FPGA_LX_MASTER_TRANSMITTER_BASE   0x80023000
+#define FPGA_LX_MASTER_RECEIVER_BASE      0x80023804
 #define FPGA_LX_MASTER_RESET              0x80023800
-#define FPGA_LX_MASTER_TRANSMITTER_REG    0x80023804
+#else /* FPGA design version 3 */
+#define FPGA_LX_MASTER_TRANSMITTER_BASE   0x80024000
+#define FPGA_LX_MASTER_RECEIVER_BASE      0x80024800
+#define FPGA_LX_MASTER_RESET              0x80025000
+#endif
+#define FPGA_LX_MASTER_TRANSMITTER_REG    0x80025004
+#define FPGA_LX_MASTER_TRANSMITTER_WDOG   0x80025008
+#define FPGA_LX_MASTER_TRANSMITTER_CYCLE  0x8002500C
+#define FPGA_LX_MASTER_RECEIVER_REG       0x80025010
+#define FPGA_LX_MASTER_RECEIVER_DONE_DIV  0x80025014
 
 extern volatile uint32_t *fpga_lx_master_transmitter_base;
 extern volatile uint32_t *fpga_lx_master_transmitter_reg;
+extern volatile uint32_t *fpga_lx_master_transmitter_cycle;
+extern volatile uint32_t *fpga_lx_master_transmitter_wdog;
+extern volatile uint32_t *fpga_lx_master_receiver_base;
+extern volatile uint32_t *fpga_lx_master_receiver_reg;
 extern volatile uint32_t *fpga_lx_master_reset;
 extern volatile uint32_t *fpga_lx_master_conf;
 
+extern volatile uint32_t *fpga_lx_master_transmitter_control_reg;
+extern volatile uint32_t *fpga_lx_master_receiver_control_reg;
+extern volatile uint32_t *fpga_lx_master_receiver_done_div;
+
+#define FPGA_LX_MASTER_CONTROL_ADDRESS_MASK     0x0000FF00
+#define FPGA_LX_MASTER_CONTROL_DATA_LENGTH_MASK 0x000000FF
+
 /* Configuration defines */
 
 #define FPGA_CONFIGURATION_FILE_ADDRESS 0xA1C00000
@@ -95,6 +126,9 @@ int fpga_tumbl_kick_trace();
 
 void fpga_tumbl_write(unsigned int offset, unsigned char *ptr, int len);
 
+int (*fpga_reconfiguaration_initiated)(void);
+int (*fpga_reconfiguaration_finished)(void);
+
 void fpga_init();
 int fpga_configure();
 int fpga_measure_bus_read();