/* LX Master */
+#if 0 /* FPGA design version 2 */
+#define FPGA_LX_MASTER_TRANSMITTER_BASE 0x80023000
+#define FPGA_LX_MASTER_RECEIVER_BASE 0x80023804
+#define FPGA_LX_MASTER_RESET 0x80023800
+#else /* FPGA design version 3 */
#define FPGA_LX_MASTER_TRANSMITTER_BASE 0x80024000
#define FPGA_LX_MASTER_RECEIVER_BASE 0x80024800
#define FPGA_LX_MASTER_RESET 0x80025000
+#endif
#define FPGA_LX_MASTER_TRANSMITTER_REG 0x80025004
#define FPGA_LX_MASTER_TRANSMITTER_WDOG 0x80025008
#define FPGA_LX_MASTER_RECEIVER_REG 0x80025012