RoCoN: FPGA register for Rx event reduction ration configuration.

[fpga/lx-cpu1/lx-rocon.git] / sw / app / rocon / appl_fpga.h

diff --git a/sw/app/rocon/appl_fpga.h b/sw/app/rocon/appl_fpga.h
index 09df21a8327bdc93ded86d6daaca52fbcbcbf5b0..ad66654ba8ed0f0c69f7fb3f00e157bf2f709008 100644 (file)
--- a/sw/app/rocon/appl_fpga.h
+++ b/sw/app/rocon/appl_fpga.h
@@ -89,10 +89,13 @@ extern volatile uint8_t *fpga_irc_reset;
 #endif
 #define FPGA_LX_MASTER_TRANSMITTER_REG    0x80025004
 #define FPGA_LX_MASTER_TRANSMITTER_WDOG   0x80025008
-#define FPGA_LX_MASTER_RECEIVER_REG       0x80025012
+#define FPGA_LX_MASTER_TRANSMITTER_CYCLE  0x8002500C
+#define FPGA_LX_MASTER_RECEIVER_REG       0x80025010
+#define FPGA_LX_MASTER_RECEIVER_DONE_DIV  0x80025014
 
 extern volatile uint32_t *fpga_lx_master_transmitter_base;
 extern volatile uint32_t *fpga_lx_master_transmitter_reg;
+extern volatile uint32_t *fpga_lx_master_transmitter_cycle;
 extern volatile uint32_t *fpga_lx_master_transmitter_wdog;
 extern volatile uint32_t *fpga_lx_master_receiver_base;
 extern volatile uint32_t *fpga_lx_master_receiver_reg;
@@ -101,6 +104,7 @@ extern volatile uint32_t *fpga_lx_master_conf;
 
 extern volatile uint32_t *fpga_lx_master_transmitter_control_reg;
 extern volatile uint32_t *fpga_lx_master_receiver_control_reg;
+extern volatile uint32_t *fpga_lx_master_receiver_done_div;
 
 #define FPGA_LX_MASTER_CONTROL_ADDRESS_MASK     0x0000FF00
 #define FPGA_LX_MASTER_CONTROL_DATA_LENGTH_MASK 0x000000FF