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[fpga/lx-cpu1/lx-rocon.git] / hw / irc_proc_inc.vhd
1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.std_logic_arith.all;
4 use ieee.std_logic_unsigned.all;
5 use ieee.numeric_std.all;
6 use work.lx_rocon_pkg.all;
7 use work.util_pkg.all;
8
9 -- Increments step in IRC coprocessor
10
11 entity irc_proc_inc is
12         generic
13         (
14                 num_irc_g  : positive := 4
15         );
16         port
17         (
18                 -- Clock
19                 clk_i   : in std_logic;
20                 reset_i : in std_logic;
21                 -- Output
22                 op_o    : out std_logic_vector(1 downto 0);
23                 axis_o  : out std_logic_vector((ceil_log2(num_irc_g)-1) downto 0)
24         );
25 end irc_proc_inc;
26
27 architecture Behavioral of irc_proc_inc is
28
29         signal num_s : std_logic_vector((axis_o'length+1) downto 0);
30
31 begin
32
33         -- higher bits are axis
34         axis_o <= num_s((num_s'length-1) downto 2);
35         -- lower bits are op
36         op_o <= num_s(1 downto 0);
37
38 inc:
39         process
40         begin
41
42                 wait until clk_i'event and clk_i = '1';
43
44                 if reset_i = '1' then
45                         num_s <= std_logic_vector(to_unsigned(4*num_irc_g - 1, num_s'length));
46                 elsif num_s = std_logic_vector(to_unsigned(4*num_irc_g - 1, num_s'length)) then
47                         num_s <= (others => '0');
48                 else
49                         num_s <= std_logic_vector(num_s + 1);
50                 end if;
51
52         end process;
53
54 end Behavioral;
55