]> rtime.felk.cvut.cz Git - fpga/lx-cpu1/lx-dad.git/tree - submodule/
Clean DAD test code a little to use symbolic names for registers and bits.
[fpga/lx-cpu1/lx-dad.git] / submodule /
drwxr-xr-x   ..
m--------- - sysless
m--------- - ulut