Shift some external signals by half of clock cycle to visualize synchronization.

Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>

diff --git a/hw/tb/lx_dad_top_tb.vhd b/hw/tb/lx_dad_top_tb.vhd
index 43f18b774893ead4f728245b6bbebe1486038b42..401bf7f328c8747517db2a54bd91308d3f25f6c5 100644 (file)
--- a/hw/tb/lx_dad_top_tb.vhd
+++ b/hw/tb/lx_dad_top_tb.vhd
@@ -124,19 +124,21 @@ BEGIN
 
                -- Write to example bus memory
                wait until clk_50m'event and clk_50m = '1';
-               wait until clk_50m'event and clk_50m = '1';
+               wait until clk_50m'event and clk_50m = '0';
                address <= x"0004";
                data <= x"12345678";
                bls <= "0000";
                cs0_xc <= '0';
                wait until clk_50m'event and clk_50m = '1';
                wait until clk_50m'event and clk_50m = '1';
+               wait until clk_50m'event and clk_50m = '1';
                cs0_xc <= '1';
                rd <= '1';
                data <= x"abcdef01";
                bls <= "1111";
                data <= (others => 'Z');
                wait until clk_50m'event and clk_50m = '1';
+               wait until clk_50m'event and clk_50m = '1';
 
                -- Simulate external master accesses example bus memory
                xmem_loop: loop
@@ -155,6 +157,7 @@ BEGIN
 
                        wait until clk_50m'event and clk_50m = '1';
                        wait until clk_50m'event and clk_50m = '1';
+                       wait until clk_50m'event and clk_50m = '0';
                        address <= x"0004";
                        rd <= '0';
                        cs0_xc <= '0';
@@ -162,6 +165,8 @@ BEGIN
                        wait until clk_50m'event and clk_50m = '1';
                        wait until clk_50m'event and clk_50m = '1';
                        wait until clk_50m'event and clk_50m = '1';
+                       wait until clk_50m'event and clk_50m = '1';
+                       wait until clk_50m'event and clk_50m = '0';
                        cs0_xc <= '1';
                        rd <= '1';
                        bls <= "1111";