Update DAD hardware testbed.

[fpga/lx-cpu1/lx-dad.git] / hw / tb / Makefile

diff --git a/hw/tb/Makefile b/hw/tb/Makefile
index 537c798123f7db4d20ab198bc10378c42f97bf2c..f96b113a8e2e5fbfb409ef9ae307f4bffc313978 100644 (file)
--- a/hw/tb/Makefile
+++ b/hw/tb/Makefile
@@ -5,7 +5,8 @@ lx_util_SRC=util_pkg.vhd lx_dad_pkg.vhd xilinx_dualport_bram.vhd
 lx_util_DIR=..
 lx_dad_SRC=dff3.vhd dff2.vhd cnt_div.vhd measurement_register.vhd \
        lx_crosdom_ser_fifo.vhd \
-       bus_example.vhd lx_example_mem.vhd bus_measurement.vhd lx_dad_top.vhd
+       bus_example.vhd lx_example_mem.vhd bus_measurement.vhd lx_dad_top.vhd \
+       clockgen.vhd bus_sensor.vhd sensor_mem.vhd lx_adc_if.vhd
 lx_dad_DIR=..
 
 MODULES=lx_util lx_dad
@@ -32,7 +33,7 @@ all:  test-lx-dad
 
 test-lx-dad: analyze-all #imem.bits
        $(GHDL) $(GHDLFLAGS) -m $(ANALYZEFLAGS) lx_dad_top_tb
-       $(GHDL) $(GHDLFLAGS) -r lx_dad_top_tb --stop-time=10000ns --vcd=$@.vcd --wave=$@.ghw
+       $(GHDL) $(GHDLFLAGS) -r lx_dad_top_tb --stop-time=1000000ns --vcd=$@.vcd --wave=$@.ghw
 
 analyze-all: $(SRC)
        $(GHDL) $(GHDLFLAGS) -a $(ANALYZEFLAGS) $(SRC)