fixed FPGA buggs, added support for single shot measurement (fpga does 2 measurements...

[fpga/lx-cpu1/lx-dad.git] / hw / lx_dad_pkg.vhd

diff --git a/hw/lx_dad_pkg.vhd b/hw/lx_dad_pkg.vhd
index 520b20b51d6d4e83fbeb98ce7563f0dfb083b999..137384cca6ae2843337057d41a170a2c5bca4e3e 100644 (file)
--- a/hw/lx_dad_pkg.vhd
+++ b/hw/lx_dad_pkg.vhd
@@ -20,7 +20,7 @@ package lx_dad_pkg is
                phi_2   : out std_logic;
                phi_st  : out std_logic;
                ph_rst  : out std_logic;
-               LED             : out std_logic;
+               --LED           : out std_logic;
                sck_o   : out std_logic;
                cnv_o   : out std_logic;
                
@@ -34,7 +34,7 @@ package lx_dad_pkg is
 
                -- mem related inputs
 
-               addr_i  : in std_logic_vector(1 downto 0);
+               addr_i  : in std_logic_vector(3 downto 0);
                data_i  : in std_logic_vector(31 downto 0);
                ce_i    : in std_logic;
                bls_i   : in std_logic_vector(3 downto 0);
@@ -59,6 +59,7 @@ package lx_dad_pkg is
                data_i       : in std_logic_vector(31 downto 0);
                data_o       : out std_logic_vector(31 downto 0);
 
+               led             : out std_logic;
                
                -- Memory wiring for internal state automata use
                ce_a_i   : in std_logic;
@@ -107,7 +108,7 @@ package lx_dad_pkg is
                cnv_o   : out std_logic;
                data_o  : out std_logic_vector((adc_res-1) downto 0);
                drdy_o  : out std_logic;
-       
+               
                sck_i   : in std_logic;
                SDI             : in std_logic
        );