Re-implemented ADC start logic to enable multiple samples per pixel mode.

[fpga/lx-cpu1/lx-dad.git] / hw / lx_adc_if.vhd

diff --git a/hw/lx_adc_if.vhd b/hw/lx_adc_if.vhd
index 1983ca29b5b009ded6e4a44d695cdd0bdf6d9d63..e9d9fd02e2e6ac54d000f9c6a82db63260e8d416 100644 (file)
--- a/hw/lx_adc_if.vhd
+++ b/hw/lx_adc_if.vhd
@@ -22,7 +22,7 @@ port
        drdy_o  : out std_logic;\r
                \r
        sck_i   : in std_logic;\r
-       SDI             : in std_logic\r
+       SDI     : in std_logic\r
 );\r
 end lx_adc_if;\r
 \r
@@ -37,6 +37,9 @@ architecture rtl of lx_adc_if is
        type    states_i        is (conv, reading, iddle);\r
        signal  state_i         : states_i;\r
        signal  convert         : std_logic;\r
+       signal  odd_even        : std_logic;\r
+       signal  odd_even_r      : std_logic;\r
+       signal  odd_even_last   : std_logic;\r
 \r
        signal drdy_i           : std_logic;\r
        signal drdy_i_last      : std_logic;\r
@@ -47,6 +50,8 @@ architecture rtl of lx_adc_if is
        attribute REGISTER_DUPLICATION of drdy_i : signal is "NO";\r
        attribute REGISTER_DUPLICATION of drdy_i_last : signal is "NO";\r
        attribute REGISTER_DUPLICATION of drdy_i_last_last : signal is "NO";\r
+       attribute REGISTER_DUPLICATION of odd_even : signal is "NO";\r
+       attribute REGISTER_DUPLICATION of odd_even_r : signal is "NO";\r
        \r
 begin\r
 \r
@@ -57,6 +62,7 @@ begin
                        drdy_i_last <= '0';\r
                        drdy_i_last_last <= '0';\r
                        data_o <= (others => '0');\r
+                       odd_even_r <= '0';\r
                elsif rising_edge(clk_i) then\r
                        drdy_i_last_last <= drdy_i_last;\r
                        drdy_i_last <= drdy_i;\r
@@ -65,6 +71,7 @@ begin
                                data_o <= received;\r
                                drdy_o <= '1';\r
                        end if;\r
+                       odd_even_r <= odd_even;\r
                end if;\r
        end process;\r
 \r
@@ -74,19 +81,22 @@ begin
                        active_bit_r <= 17;\r
                        drdy_i <= '0';\r
                        received <= (others => '0');\r
+                       odd_even_last <= '0';\r
                elsif rising_edge(sck_i) then\r
-                       if convert = '1' and active_bit_r = 17 then\r
-                               received(active_bit_r) <= SDI;\r
-                               active_bit_r <= 16;\r
+                       if convert = '1' and ((active_bit_r = adc_res - 1) or\r
+                          (odd_even_last /= odd_even_r)) then\r
+                               received(adc_res - 1) <= SDI;\r
+                               active_bit_r <= adc_res - 2;\r
                                drdy_i <= '0';\r
+                               odd_even_last <= odd_even_r;\r
                        elsif active_bit_r /= 17 then\r
+                               received(active_bit_r) <= SDI;\r
                                if active_bit_r = 0 then\r
                                        drdy_i <= '1';\r
-                                       active_bit_r <= 17;\r
+                                       active_bit_r <= adc_res - 1;\r
                                else\r
                                        active_bit_r <= active_bit_r - 1;\r
                                end if;\r
-                               received(active_bit_r) <= SDI;\r
                        end if;\r
                end if;\r
        end process;\r
@@ -97,6 +107,7 @@ begin
                if rst_i = '1' then\r
                        ckout <= '0';\r
                        conv_cnter <= 0;\r
+                       odd_even <= '0';\r
                elsif rising_edge(clk_i) then\r
                        case state_i is\r
                        when iddle =>\r
@@ -104,6 +115,7 @@ begin
                                        state_i <= conv;\r
                                        cnv_o <= '1';\r
                                        convert <= '1';\r
+                                       odd_even <= not odd_even;\r
                                end if;\r
                        when conv =>\r
                                if conv_cnter = (conv_cycles - 1) then\r