1 ;; GCC machine description for IA-32 and x86-64.
2 ;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 ;; 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
4 ;; Free Software Foundation, Inc.
5 ;; Mostly by William Schelter.
6 ;; x86_64 support added by Jan Hubicka
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 3, or (at your option)
15 ;; GCC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING3. If not see
22 ;; <http://www.gnu.org/licenses/>. */
24 ;; The original PO technology requires these to be ordered by speed,
25 ;; so that assigner will pick the fastest.
27 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 ;; The special asm out single letter directives following a '%' are:
30 ;; L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
31 ;; C -- print opcode suffix for set/cmov insn.
32 ;; c -- like C, but print reversed condition
33 ;; F,f -- likewise, but for floating-point.
34 ;; O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
36 ;; R -- print the prefix for register names.
37 ;; z -- print the opcode suffix for the size of the current operand.
38 ;; Z -- likewise, with special suffixes for x87 instructions.
39 ;; * -- print a star (in certain assembler syntax)
40 ;; A -- print an absolute memory reference.
41 ;; E -- print address with DImode register names if TARGET_64BIT.
42 ;; w -- print the operand as if it's a "word" (HImode) even if it isn't.
43 ;; s -- print a shift double count, followed by the assemblers argument
45 ;; b -- print the QImode name of the register for the indicated operand.
46 ;; %b0 would print %al if operands[0] is reg 0.
47 ;; w -- likewise, print the HImode name of the register.
48 ;; k -- likewise, print the SImode name of the register.
49 ;; q -- likewise, print the DImode name of the register.
50 ;; x -- likewise, print the V4SFmode name of the register.
51 ;; t -- likewise, print the V8SFmode name of the register.
52 ;; h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
53 ;; y -- print "st(0)" instead of "st" as a register.
54 ;; d -- print duplicated register operand for AVX instruction.
55 ;; D -- print condition for SSE cmp instruction.
56 ;; P -- if PIC, print an @PLT suffix.
57 ;; p -- print raw symbol name.
58 ;; X -- don't print any sort of PIC '@' suffix for a symbol.
59 ;; & -- print some in-use local-dynamic symbol name.
60 ;; H -- print a memory address offset by 8; used for sse high-parts
61 ;; Y -- print condition for XOP pcom* instruction.
62 ;; + -- print a branch hint as 'cs' or 'ds' prefix
63 ;; ; -- print a semicolon (after prefixes due to bug in older gas).
64 ;; @ -- print a segment register of thread base pointer load
66 (define_c_enum "unspec" [
67 ;; Relocation specifiers
78 UNSPEC_MACHOPIC_OFFSET
86 UNSPEC_MEMORY_BLOCKAGE
96 ;; Other random patterns
105 UNSPEC_LD_MPIC ; load_macho_picbase
107 UNSPEC_DIV_ALREADY_SPLIT
108 UNSPEC_MS_TO_SYSV_CALL
109 UNSPEC_CALL_NEEDS_VZEROUPPER
113 ;; For SSE/MMX support:
121 ;; Generic math support
123 UNSPEC_IEEE_MIN ; not commutative
124 UNSPEC_IEEE_MAX ; not commutative
126 ;; x87 Floating point
142 UNSPEC_FRNDINT_MASK_PM
146 ;; x87 Double output FP
181 (define_c_enum "unspecv" [
184 UNSPECV_PROBE_STACK_RANGE
187 UNSPECV_SPLIT_STACK_RETURN
193 UNSPECV_LLWP_INTRINSIC
194 UNSPECV_SLWP_INTRINSIC
195 UNSPECV_LWPVAL_INTRINSIC
196 UNSPECV_LWPINS_INTRINSIC
202 ;; For RDRAND support
206 ;; Constants to represent rounding modes in the ROUND instruction
215 ;; Constants to represent pcomtrue/pcomfalse variants
225 ;; Constants used in the XOP pperm instruction
227 [(PPERM_SRC 0x00) /* copy source */
228 (PPERM_INVERT 0x20) /* invert source */
229 (PPERM_REVERSE 0x40) /* bit reverse source */
230 (PPERM_REV_INV 0x60) /* bit reverse & invert src */
231 (PPERM_ZERO 0x80) /* all 0's */
232 (PPERM_ONES 0xa0) /* all 1's */
233 (PPERM_SIGN 0xc0) /* propagate sign bit */
234 (PPERM_INV_SIGN 0xe0) /* invert & propagate sign */
235 (PPERM_SRC1 0x00) /* use first source byte */
236 (PPERM_SRC2 0x10) /* use second source byte */
239 ;; Registers by name.
292 ;; Insns whose names begin with "x86_" are emitted by gen_FOO calls
295 ;; In C guard expressions, put expressions which may be compile-time
296 ;; constants first. This allows for better optimization. For
297 ;; example, write "TARGET_64BIT && reload_completed", not
298 ;; "reload_completed && TARGET_64BIT".
302 (define_attr "cpu" "none,pentium,pentiumpro,geode,k6,athlon,k8,core2,corei7,
303 atom,generic64,amdfam10,bdver1,bdver2,btver1"
304 (const (symbol_ref "ix86_schedule")))
306 ;; A basic instruction type. Refinements due to arguments to be
307 ;; provided in other attributes.
310 alu,alu1,negnot,imov,imovx,lea,
311 incdec,ishift,ishiftx,ishift1,rotate,rotatex,rotate1,imul,imulx,idiv,
312 icmp,test,ibr,setcc,icmov,
313 push,pop,call,callv,leave,
315 fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,fisttp,frndint,
316 sselog,sselog1,sseiadd,sseiadd1,sseishft,sseishft1,sseimul,
317 sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,ssecvt1,sseicvt,ssediv,sseins,
318 ssemuladd,sse4arg,lwp,
319 mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft"
320 (const_string "other"))
322 ;; Main data type used by the insn
324 "unknown,none,QI,HI,SI,DI,TI,OI,SF,DF,XF,TF,V8SF,V4DF,V4SF,V2DF,V2SF,V1DF"
325 (const_string "unknown"))
327 ;; The CPU unit operations uses.
328 (define_attr "unit" "integer,i387,sse,mmx,unknown"
329 (cond [(eq_attr "type" "fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,fisttp,frndint")
330 (const_string "i387")
331 (eq_attr "type" "sselog,sselog1,sseiadd,sseiadd1,sseishft,sseishft1,sseimul,
332 sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,
333 ssecvt1,sseicvt,ssediv,sseins,ssemuladd,sse4arg")
335 (eq_attr "type" "mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft")
337 (eq_attr "type" "other")
338 (const_string "unknown")]
339 (const_string "integer")))
341 ;; The (bounding maximum) length of an instruction immediate.
342 (define_attr "length_immediate" ""
343 (cond [(eq_attr "type" "incdec,setcc,icmov,str,lea,other,multi,idiv,leave,
346 (eq_attr "unit" "i387,sse,mmx")
348 (eq_attr "type" "alu,alu1,negnot,imovx,ishift,ishiftx,ishift1,
349 rotate,rotatex,rotate1,imul,icmp,push,pop")
350 (symbol_ref "ix86_attr_length_immediate_default (insn, true)")
351 (eq_attr "type" "imov,test")
352 (symbol_ref "ix86_attr_length_immediate_default (insn, false)")
353 (eq_attr "type" "call")
354 (if_then_else (match_operand 0 "constant_call_address_operand" "")
357 (eq_attr "type" "callv")
358 (if_then_else (match_operand 1 "constant_call_address_operand" "")
361 ;; We don't know the size before shorten_branches. Expect
362 ;; the instruction to fit for better scheduling.
363 (eq_attr "type" "ibr")
366 (symbol_ref "/* Update immediate_length and other attributes! */
367 gcc_unreachable (),1")))
369 ;; The (bounding maximum) length of an instruction address.
370 (define_attr "length_address" ""
371 (cond [(eq_attr "type" "str,other,multi,fxch")
373 (and (eq_attr "type" "call")
374 (match_operand 0 "constant_call_address_operand" ""))
376 (and (eq_attr "type" "callv")
377 (match_operand 1 "constant_call_address_operand" ""))
380 (symbol_ref "ix86_attr_length_address_default (insn)")))
382 ;; Set when length prefix is used.
383 (define_attr "prefix_data16" ""
384 (cond [(eq_attr "type" "ssemuladd,sse4arg,sseiadd1,ssecvt1")
386 (eq_attr "mode" "HI")
388 (and (eq_attr "unit" "sse") (eq_attr "mode" "V2DF,TI"))
393 ;; Set when string REP prefix is used.
394 (define_attr "prefix_rep" ""
395 (cond [(eq_attr "type" "ssemuladd,sse4arg,sseiadd1,ssecvt1")
397 (and (eq_attr "unit" "sse") (eq_attr "mode" "SF,DF"))
402 ;; Set when 0f opcode prefix is used.
403 (define_attr "prefix_0f" ""
405 (ior (eq_attr "type" "imovx,setcc,icmov,bitmanip")
406 (eq_attr "unit" "sse,mmx"))
410 ;; Set when REX opcode prefix is used.
411 (define_attr "prefix_rex" ""
412 (cond [(not (match_test "TARGET_64BIT"))
414 (and (eq_attr "mode" "DI")
415 (and (eq_attr "type" "!push,pop,call,callv,leave,ibr")
416 (eq_attr "unit" "!mmx")))
418 (and (eq_attr "mode" "QI")
419 (match_test "x86_extended_QIreg_mentioned_p (insn)"))
421 (match_test "x86_extended_reg_mentioned_p (insn)")
423 (and (eq_attr "type" "imovx")
424 (match_operand:QI 1 "ext_QIreg_operand" ""))
429 ;; There are also additional prefixes in 3DNOW, SSSE3.
430 ;; ssemuladd,sse4arg default to 0f24/0f25 and DREX byte,
431 ;; sseiadd1,ssecvt1 to 0f7a with no DREX byte.
432 ;; 3DNOW has 0f0f prefix, SSSE3 and SSE4_{1,2} 0f38/0f3a.
433 (define_attr "prefix_extra" ""
434 (cond [(eq_attr "type" "ssemuladd,sse4arg")
436 (eq_attr "type" "sseiadd1,ssecvt1")
441 ;; Prefix used: original, VEX or maybe VEX.
442 (define_attr "prefix" "orig,vex,maybe_vex"
443 (if_then_else (eq_attr "mode" "OI,V8SF,V4DF")
445 (const_string "orig")))
447 ;; VEX W bit is used.
448 (define_attr "prefix_vex_w" "" (const_int 0))
450 ;; The length of VEX prefix
451 ;; Only instructions with 0f prefix can have 2 byte VEX prefix,
452 ;; 0f38/0f3a prefixes can't. In i386.md 0f3[8a] is
453 ;; still prefix_0f 1, with prefix_extra 1.
454 (define_attr "length_vex" ""
455 (if_then_else (and (eq_attr "prefix_0f" "1")
456 (eq_attr "prefix_extra" "0"))
457 (if_then_else (eq_attr "prefix_vex_w" "1")
458 (symbol_ref "ix86_attr_length_vex_default (insn, true, true)")
459 (symbol_ref "ix86_attr_length_vex_default (insn, true, false)"))
460 (if_then_else (eq_attr "prefix_vex_w" "1")
461 (symbol_ref "ix86_attr_length_vex_default (insn, false, true)")
462 (symbol_ref "ix86_attr_length_vex_default (insn, false, false)"))))
464 ;; Set when modrm byte is used.
465 (define_attr "modrm" ""
466 (cond [(eq_attr "type" "str,leave")
468 (eq_attr "unit" "i387")
470 (and (eq_attr "type" "incdec")
471 (and (not (match_test "TARGET_64BIT"))
472 (ior (match_operand:SI 1 "register_operand" "")
473 (match_operand:HI 1 "register_operand" ""))))
475 (and (eq_attr "type" "push")
476 (not (match_operand 1 "memory_operand" "")))
478 (and (eq_attr "type" "pop")
479 (not (match_operand 0 "memory_operand" "")))
481 (and (eq_attr "type" "imov")
482 (and (not (eq_attr "mode" "DI"))
483 (ior (and (match_operand 0 "register_operand" "")
484 (match_operand 1 "immediate_operand" ""))
485 (ior (and (match_operand 0 "ax_reg_operand" "")
486 (match_operand 1 "memory_displacement_only_operand" ""))
487 (and (match_operand 0 "memory_displacement_only_operand" "")
488 (match_operand 1 "ax_reg_operand" ""))))))
490 (and (eq_attr "type" "call")
491 (match_operand 0 "constant_call_address_operand" ""))
493 (and (eq_attr "type" "callv")
494 (match_operand 1 "constant_call_address_operand" ""))
496 (and (eq_attr "type" "alu,alu1,icmp,test")
497 (match_operand 0 "ax_reg_operand" ""))
498 (symbol_ref "(get_attr_length_immediate (insn) <= (get_attr_mode (insn) != MODE_QI))")
502 ;; The (bounding maximum) length of an instruction in bytes.
503 ;; ??? fistp and frndint are in fact fldcw/{fistp,frndint}/fldcw sequences.
504 ;; Later we may want to split them and compute proper length as for
506 (define_attr "length" ""
507 (cond [(eq_attr "type" "other,multi,fistp,frndint")
509 (eq_attr "type" "fcmp")
511 (eq_attr "unit" "i387")
513 (plus (attr "prefix_data16")
514 (attr "length_address")))
515 (ior (eq_attr "prefix" "vex")
516 (and (eq_attr "prefix" "maybe_vex")
517 (match_test "TARGET_AVX")))
518 (plus (attr "length_vex")
519 (plus (attr "length_immediate")
521 (attr "length_address"))))]
522 (plus (plus (attr "modrm")
523 (plus (attr "prefix_0f")
524 (plus (attr "prefix_rex")
525 (plus (attr "prefix_extra")
527 (plus (attr "prefix_rep")
528 (plus (attr "prefix_data16")
529 (plus (attr "length_immediate")
530 (attr "length_address")))))))
532 ;; The `memory' attribute is `none' if no memory is referenced, `load' or
533 ;; `store' if there is a simple memory reference therein, or `unknown'
534 ;; if the instruction is complex.
536 (define_attr "memory" "none,load,store,both,unknown"
537 (cond [(eq_attr "type" "other,multi,str,lwp")
538 (const_string "unknown")
539 (eq_attr "type" "lea,fcmov,fpspc")
540 (const_string "none")
541 (eq_attr "type" "fistp,leave")
542 (const_string "both")
543 (eq_attr "type" "frndint")
544 (const_string "load")
545 (eq_attr "type" "push")
546 (if_then_else (match_operand 1 "memory_operand" "")
547 (const_string "both")
548 (const_string "store"))
549 (eq_attr "type" "pop")
550 (if_then_else (match_operand 0 "memory_operand" "")
551 (const_string "both")
552 (const_string "load"))
553 (eq_attr "type" "setcc")
554 (if_then_else (match_operand 0 "memory_operand" "")
555 (const_string "store")
556 (const_string "none"))
557 (eq_attr "type" "icmp,test,ssecmp,ssecomi,mmxcmp,fcmp")
558 (if_then_else (ior (match_operand 0 "memory_operand" "")
559 (match_operand 1 "memory_operand" ""))
560 (const_string "load")
561 (const_string "none"))
562 (eq_attr "type" "ibr")
563 (if_then_else (match_operand 0 "memory_operand" "")
564 (const_string "load")
565 (const_string "none"))
566 (eq_attr "type" "call")
567 (if_then_else (match_operand 0 "constant_call_address_operand" "")
568 (const_string "none")
569 (const_string "load"))
570 (eq_attr "type" "callv")
571 (if_then_else (match_operand 1 "constant_call_address_operand" "")
572 (const_string "none")
573 (const_string "load"))
574 (and (eq_attr "type" "alu1,negnot,ishift1,sselog1")
575 (match_operand 1 "memory_operand" ""))
576 (const_string "both")
577 (and (match_operand 0 "memory_operand" "")
578 (match_operand 1 "memory_operand" ""))
579 (const_string "both")
580 (match_operand 0 "memory_operand" "")
581 (const_string "store")
582 (match_operand 1 "memory_operand" "")
583 (const_string "load")
585 "!alu1,negnot,ishift1,
586 imov,imovx,icmp,test,bitmanip,
588 sse,ssemov,ssecmp,ssecomi,ssecvt,ssecvt1,sseicvt,sselog1,
589 sseiadd1,mmx,mmxmov,mmxcmp,mmxcvt")
590 (match_operand 2 "memory_operand" ""))
591 (const_string "load")
592 (and (eq_attr "type" "icmov,ssemuladd,sse4arg")
593 (match_operand 3 "memory_operand" ""))
594 (const_string "load")
596 (const_string "none")))
598 ;; Indicates if an instruction has both an immediate and a displacement.
600 (define_attr "imm_disp" "false,true,unknown"
601 (cond [(eq_attr "type" "other,multi")
602 (const_string "unknown")
603 (and (eq_attr "type" "icmp,test,imov,alu1,ishift1,rotate1")
604 (and (match_operand 0 "memory_displacement_operand" "")
605 (match_operand 1 "immediate_operand" "")))
606 (const_string "true")
607 (and (eq_attr "type" "alu,ishift,ishiftx,rotate,rotatex,imul,idiv")
608 (and (match_operand 0 "memory_displacement_operand" "")
609 (match_operand 2 "immediate_operand" "")))
610 (const_string "true")
612 (const_string "false")))
614 ;; Indicates if an FP operation has an integer source.
616 (define_attr "fp_int_src" "false,true"
617 (const_string "false"))
619 ;; Defines rounding mode of an FP operation.
621 (define_attr "i387_cw" "trunc,floor,ceil,mask_pm,uninitialized,any"
622 (const_string "any"))
624 ;; Define attribute to classify add/sub insns that consumes carry flag (CF)
625 (define_attr "use_carry" "0,1" (const_string "0"))
627 ;; Define attribute to indicate unaligned ssemov insns
628 (define_attr "movu" "0,1" (const_string "0"))
630 ;; Used to control the "enabled" attribute on a per-instruction basis.
631 (define_attr "isa" "base,sse2,sse2_noavx,sse3,sse4,sse4_noavx,noavx,avx,
633 (const_string "base"))
635 (define_attr "enabled" ""
636 (cond [(eq_attr "isa" "sse2") (symbol_ref "TARGET_SSE2")
637 (eq_attr "isa" "sse2_noavx")
638 (symbol_ref "TARGET_SSE2 && !TARGET_AVX")
639 (eq_attr "isa" "sse3") (symbol_ref "TARGET_SSE3")
640 (eq_attr "isa" "sse4") (symbol_ref "TARGET_SSE4_1")
641 (eq_attr "isa" "sse4_noavx")
642 (symbol_ref "TARGET_SSE4_1 && !TARGET_AVX")
643 (eq_attr "isa" "avx") (symbol_ref "TARGET_AVX")
644 (eq_attr "isa" "noavx") (symbol_ref "!TARGET_AVX")
645 (eq_attr "isa" "bmi2") (symbol_ref "TARGET_BMI2")
646 (eq_attr "isa" "fma4") (symbol_ref "TARGET_FMA4")
647 (eq_attr "isa" "fma") (symbol_ref "TARGET_FMA")
651 ;; Describe a user's asm statement.
652 (define_asm_attributes
653 [(set_attr "length" "128")
654 (set_attr "type" "multi")])
656 (define_code_iterator plusminus [plus minus])
658 (define_code_iterator sat_plusminus [ss_plus us_plus ss_minus us_minus])
660 ;; Base name for define_insn
661 (define_code_attr plusminus_insn
662 [(plus "add") (ss_plus "ssadd") (us_plus "usadd")
663 (minus "sub") (ss_minus "sssub") (us_minus "ussub")])
665 ;; Base name for insn mnemonic.
666 (define_code_attr plusminus_mnemonic
667 [(plus "add") (ss_plus "adds") (us_plus "addus")
668 (minus "sub") (ss_minus "subs") (us_minus "subus")])
669 (define_code_attr plusminus_carry_mnemonic
670 [(plus "adc") (minus "sbb")])
672 ;; Mark commutative operators as such in constraints.
673 (define_code_attr comm [(plus "%") (ss_plus "%") (us_plus "%")
674 (minus "") (ss_minus "") (us_minus "")])
676 ;; Mapping of max and min
677 (define_code_iterator maxmin [smax smin umax umin])
679 ;; Mapping of signed max and min
680 (define_code_iterator smaxmin [smax smin])
682 ;; Mapping of unsigned max and min
683 (define_code_iterator umaxmin [umax umin])
685 ;; Base name for integer and FP insn mnemonic
686 (define_code_attr maxmin_int [(smax "maxs") (smin "mins")
687 (umax "maxu") (umin "minu")])
688 (define_code_attr maxmin_float [(smax "max") (smin "min")])
690 ;; Mapping of logic operators
691 (define_code_iterator any_logic [and ior xor])
692 (define_code_iterator any_or [ior xor])
694 ;; Base name for insn mnemonic.
695 (define_code_attr logic [(and "and") (ior "or") (xor "xor")])
697 ;; Mapping of logic-shift operators
698 (define_code_iterator any_lshift [ashift lshiftrt])
700 ;; Mapping of shift-right operators
701 (define_code_iterator any_shiftrt [lshiftrt ashiftrt])
703 ;; Base name for define_insn
704 (define_code_attr shift_insn
705 [(ashift "ashl") (lshiftrt "lshr") (ashiftrt "ashr")])
707 ;; Base name for insn mnemonic.
708 (define_code_attr shift [(ashift "sll") (lshiftrt "shr") (ashiftrt "sar")])
709 (define_code_attr vshift [(ashift "sll") (lshiftrt "srl") (ashiftrt "sra")])
711 ;; Mapping of rotate operators
712 (define_code_iterator any_rotate [rotate rotatert])
714 ;; Base name for define_insn
715 (define_code_attr rotate_insn [(rotate "rotl") (rotatert "rotr")])
717 ;; Base name for insn mnemonic.
718 (define_code_attr rotate [(rotate "rol") (rotatert "ror")])
720 ;; Mapping of abs neg operators
721 (define_code_iterator absneg [abs neg])
723 ;; Base name for x87 insn mnemonic.
724 (define_code_attr absneg_mnemonic [(abs "abs") (neg "chs")])
726 ;; Used in signed and unsigned widening multiplications.
727 (define_code_iterator any_extend [sign_extend zero_extend])
729 ;; Prefix for insn menmonic.
730 (define_code_attr sgnprefix [(sign_extend "i") (zero_extend "")])
732 ;; Prefix for define_insn
733 (define_code_attr u [(sign_extend "") (zero_extend "u")])
734 (define_code_attr s [(sign_extend "s") (zero_extend "u")])
736 ;; All integer modes.
737 (define_mode_iterator SWI1248x [QI HI SI DI])
739 ;; All integer modes without QImode.
740 (define_mode_iterator SWI248x [HI SI DI])
742 ;; All integer modes without QImode and HImode.
743 (define_mode_iterator SWI48x [SI DI])
745 ;; All integer modes without SImode and DImode.
746 (define_mode_iterator SWI12 [QI HI])
748 ;; All integer modes without DImode.
749 (define_mode_iterator SWI124 [QI HI SI])
751 ;; All integer modes without QImode and DImode.
752 (define_mode_iterator SWI24 [HI SI])
754 ;; Single word integer modes.
755 (define_mode_iterator SWI [QI HI SI (DI "TARGET_64BIT")])
757 ;; Single word integer modes without QImode.
758 (define_mode_iterator SWI248 [HI SI (DI "TARGET_64BIT")])
760 ;; Single word integer modes without QImode and HImode.
761 (define_mode_iterator SWI48 [SI (DI "TARGET_64BIT")])
763 ;; All math-dependant single and double word integer modes.
764 (define_mode_iterator SDWIM [(QI "TARGET_QIMODE_MATH")
765 (HI "TARGET_HIMODE_MATH")
766 SI DI (TI "TARGET_64BIT")])
768 ;; Math-dependant single word integer modes.
769 (define_mode_iterator SWIM [(QI "TARGET_QIMODE_MATH")
770 (HI "TARGET_HIMODE_MATH")
771 SI (DI "TARGET_64BIT")])
773 ;; Math-dependant integer modes without DImode.
774 (define_mode_iterator SWIM124 [(QI "TARGET_QIMODE_MATH")
775 (HI "TARGET_HIMODE_MATH")
778 ;; Math-dependant single word integer modes without QImode.
779 (define_mode_iterator SWIM248 [(HI "TARGET_HIMODE_MATH")
780 SI (DI "TARGET_64BIT")])
782 ;; Double word integer modes.
783 (define_mode_iterator DWI [(DI "!TARGET_64BIT")
784 (TI "TARGET_64BIT")])
786 ;; Double word integer modes as mode attribute.
787 (define_mode_attr DWI [(SI "DI") (DI "TI")])
788 (define_mode_attr dwi [(SI "di") (DI "ti")])
790 ;; Half mode for double word integer modes.
791 (define_mode_iterator DWIH [(SI "!TARGET_64BIT")
792 (DI "TARGET_64BIT")])
794 ;; Instruction suffix for integer modes.
795 (define_mode_attr imodesuffix [(QI "b") (HI "w") (SI "l") (DI "q")])
797 ;; Pointer size prefix for integer modes (Intel asm dialect)
798 (define_mode_attr iptrsize [(QI "BYTE")
803 ;; Register class for integer modes.
804 (define_mode_attr r [(QI "q") (HI "r") (SI "r") (DI "r")])
806 ;; Immediate operand constraint for integer modes.
807 (define_mode_attr i [(QI "n") (HI "n") (SI "e") (DI "e")])
809 ;; General operand constraint for word modes.
810 (define_mode_attr g [(QI "qmn") (HI "rmn") (SI "rme") (DI "rme")])
812 ;; Immediate operand constraint for double integer modes.
813 (define_mode_attr di [(SI "nF") (DI "e")])
815 ;; Immediate operand constraint for shifts.
816 (define_mode_attr S [(QI "I") (HI "I") (SI "I") (DI "J") (TI "O")])
818 ;; General operand predicate for integer modes.
819 (define_mode_attr general_operand
820 [(QI "general_operand")
821 (HI "general_operand")
822 (SI "x86_64_general_operand")
823 (DI "x86_64_general_operand")
824 (TI "x86_64_general_operand")])
826 ;; General sign/zero extend operand predicate for integer modes.
827 (define_mode_attr general_szext_operand
828 [(QI "general_operand")
829 (HI "general_operand")
830 (SI "x86_64_szext_general_operand")
831 (DI "x86_64_szext_general_operand")])
833 ;; Immediate operand predicate for integer modes.
834 (define_mode_attr immediate_operand
835 [(QI "immediate_operand")
836 (HI "immediate_operand")
837 (SI "x86_64_immediate_operand")
838 (DI "x86_64_immediate_operand")])
840 ;; Nonmemory operand predicate for integer modes.
841 (define_mode_attr nonmemory_operand
842 [(QI "nonmemory_operand")
843 (HI "nonmemory_operand")
844 (SI "x86_64_nonmemory_operand")
845 (DI "x86_64_nonmemory_operand")])
847 ;; Operand predicate for shifts.
848 (define_mode_attr shift_operand
849 [(QI "nonimmediate_operand")
850 (HI "nonimmediate_operand")
851 (SI "nonimmediate_operand")
852 (DI "shiftdi_operand")
853 (TI "register_operand")])
855 ;; Operand predicate for shift argument.
856 (define_mode_attr shift_immediate_operand
857 [(QI "const_1_to_31_operand")
858 (HI "const_1_to_31_operand")
859 (SI "const_1_to_31_operand")
860 (DI "const_1_to_63_operand")])
862 ;; Input operand predicate for arithmetic left shifts.
863 (define_mode_attr ashl_input_operand
864 [(QI "nonimmediate_operand")
865 (HI "nonimmediate_operand")
866 (SI "nonimmediate_operand")
867 (DI "ashldi_input_operand")
868 (TI "reg_or_pm1_operand")])
870 ;; SSE and x87 SFmode and DFmode floating point modes
871 (define_mode_iterator MODEF [SF DF])
873 ;; All x87 floating point modes
874 (define_mode_iterator X87MODEF [SF DF XF])
876 ;; SSE instruction suffix for various modes
877 (define_mode_attr ssemodesuffix
879 (V8SF "ps") (V4DF "pd")
880 (V4SF "ps") (V2DF "pd")
881 (V16QI "b") (V8HI "w") (V4SI "d") (V2DI "q")
882 (V32QI "b") (V16HI "w") (V8SI "d") (V4DI "q")])
884 ;; SSE vector suffix for floating point modes
885 (define_mode_attr ssevecmodesuffix [(SF "ps") (DF "pd")])
887 ;; SSE vector mode corresponding to a scalar mode
888 (define_mode_attr ssevecmode
889 [(QI "V16QI") (HI "V8HI") (SI "V4SI") (DI "V2DI") (SF "V4SF") (DF "V2DF")])
891 ;; Instruction suffix for REX 64bit operators.
892 (define_mode_attr rex64suffix [(SI "") (DI "{q}")])
894 ;; This mode iterator allows :P to be used for patterns that operate on
895 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
896 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
898 ;; This mode iterator allows :PTR to be used for patterns that operate on
899 ;; ptr_mode sized quantities.
900 (define_mode_iterator PTR
901 [(SI "ptr_mode == SImode") (DI "ptr_mode == DImode")])
903 ;; Scheduling descriptions
905 (include "pentium.md")
908 (include "athlon.md")
909 (include "bdver1.md")
915 ;; Operand and operator predicates and constraints
917 (include "predicates.md")
918 (include "constraints.md")
921 ;; Compare and branch/compare and store instructions.
923 (define_expand "cbranch<mode>4"
924 [(set (reg:CC FLAGS_REG)
925 (compare:CC (match_operand:SDWIM 1 "nonimmediate_operand" "")
926 (match_operand:SDWIM 2 "<general_operand>" "")))
927 (set (pc) (if_then_else
928 (match_operator 0 "ordered_comparison_operator"
929 [(reg:CC FLAGS_REG) (const_int 0)])
930 (label_ref (match_operand 3 "" ""))
934 if (MEM_P (operands[1]) && MEM_P (operands[2]))
935 operands[1] = force_reg (<MODE>mode, operands[1]);
936 ix86_expand_branch (GET_CODE (operands[0]),
937 operands[1], operands[2], operands[3]);
941 (define_expand "cstore<mode>4"
942 [(set (reg:CC FLAGS_REG)
943 (compare:CC (match_operand:SWIM 2 "nonimmediate_operand" "")
944 (match_operand:SWIM 3 "<general_operand>" "")))
945 (set (match_operand:QI 0 "register_operand" "")
946 (match_operator 1 "ordered_comparison_operator"
947 [(reg:CC FLAGS_REG) (const_int 0)]))]
950 if (MEM_P (operands[2]) && MEM_P (operands[3]))
951 operands[2] = force_reg (<MODE>mode, operands[2]);
952 ix86_expand_setcc (operands[0], GET_CODE (operands[1]),
953 operands[2], operands[3]);
957 (define_expand "cmp<mode>_1"
958 [(set (reg:CC FLAGS_REG)
959 (compare:CC (match_operand:SWI48 0 "nonimmediate_operand" "")
960 (match_operand:SWI48 1 "<general_operand>" "")))])
962 (define_insn "*cmp<mode>_ccno_1"
963 [(set (reg FLAGS_REG)
964 (compare (match_operand:SWI 0 "nonimmediate_operand" "<r>,?m<r>")
965 (match_operand:SWI 1 "const0_operand" "")))]
966 "ix86_match_ccmode (insn, CCNOmode)"
968 test{<imodesuffix>}\t%0, %0
969 cmp{<imodesuffix>}\t{%1, %0|%0, %1}"
970 [(set_attr "type" "test,icmp")
971 (set_attr "length_immediate" "0,1")
972 (set_attr "mode" "<MODE>")])
974 (define_insn "*cmp<mode>_1"
975 [(set (reg FLAGS_REG)
976 (compare (match_operand:SWI 0 "nonimmediate_operand" "<r>m,<r>")
977 (match_operand:SWI 1 "<general_operand>" "<r><i>,<r>m")))]
978 "ix86_match_ccmode (insn, CCmode)"
979 "cmp{<imodesuffix>}\t{%1, %0|%0, %1}"
980 [(set_attr "type" "icmp")
981 (set_attr "mode" "<MODE>")])
983 (define_insn "*cmp<mode>_minus_1"
984 [(set (reg FLAGS_REG)
986 (minus:SWI (match_operand:SWI 0 "nonimmediate_operand" "<r>m,<r>")
987 (match_operand:SWI 1 "<general_operand>" "<r><i>,<r>m"))
989 "ix86_match_ccmode (insn, CCGOCmode)"
990 "cmp{<imodesuffix>}\t{%1, %0|%0, %1}"
991 [(set_attr "type" "icmp")
992 (set_attr "mode" "<MODE>")])
994 (define_insn "*cmpqi_ext_1"
995 [(set (reg FLAGS_REG)
997 (match_operand:QI 0 "general_operand" "Qm")
1000 (match_operand 1 "ext_register_operand" "Q")
1002 (const_int 8)) 0)))]
1003 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
1004 "cmp{b}\t{%h1, %0|%0, %h1}"
1005 [(set_attr "type" "icmp")
1006 (set_attr "mode" "QI")])
1008 (define_insn "*cmpqi_ext_1_rex64"
1009 [(set (reg FLAGS_REG)
1011 (match_operand:QI 0 "register_operand" "Q")
1014 (match_operand 1 "ext_register_operand" "Q")
1016 (const_int 8)) 0)))]
1017 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
1018 "cmp{b}\t{%h1, %0|%0, %h1}"
1019 [(set_attr "type" "icmp")
1020 (set_attr "mode" "QI")])
1022 (define_insn "*cmpqi_ext_2"
1023 [(set (reg FLAGS_REG)
1027 (match_operand 0 "ext_register_operand" "Q")
1030 (match_operand:QI 1 "const0_operand" "")))]
1031 "ix86_match_ccmode (insn, CCNOmode)"
1033 [(set_attr "type" "test")
1034 (set_attr "length_immediate" "0")
1035 (set_attr "mode" "QI")])
1037 (define_expand "cmpqi_ext_3"
1038 [(set (reg:CC FLAGS_REG)
1042 (match_operand 0 "ext_register_operand" "")
1045 (match_operand:QI 1 "immediate_operand" "")))])
1047 (define_insn "*cmpqi_ext_3_insn"
1048 [(set (reg FLAGS_REG)
1052 (match_operand 0 "ext_register_operand" "Q")
1055 (match_operand:QI 1 "general_operand" "Qmn")))]
1056 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
1057 "cmp{b}\t{%1, %h0|%h0, %1}"
1058 [(set_attr "type" "icmp")
1059 (set_attr "modrm" "1")
1060 (set_attr "mode" "QI")])
1062 (define_insn "*cmpqi_ext_3_insn_rex64"
1063 [(set (reg FLAGS_REG)
1067 (match_operand 0 "ext_register_operand" "Q")
1070 (match_operand:QI 1 "nonmemory_operand" "Qn")))]
1071 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
1072 "cmp{b}\t{%1, %h0|%h0, %1}"
1073 [(set_attr "type" "icmp")
1074 (set_attr "modrm" "1")
1075 (set_attr "mode" "QI")])
1077 (define_insn "*cmpqi_ext_4"
1078 [(set (reg FLAGS_REG)
1082 (match_operand 0 "ext_register_operand" "Q")
1087 (match_operand 1 "ext_register_operand" "Q")
1089 (const_int 8)) 0)))]
1090 "ix86_match_ccmode (insn, CCmode)"
1091 "cmp{b}\t{%h1, %h0|%h0, %h1}"
1092 [(set_attr "type" "icmp")
1093 (set_attr "mode" "QI")])
1095 ;; These implement float point compares.
1096 ;; %%% See if we can get away with VOIDmode operands on the actual insns,
1097 ;; which would allow mix and match FP modes on the compares. Which is what
1098 ;; the old patterns did, but with many more of them.
1100 (define_expand "cbranchxf4"
1101 [(set (reg:CC FLAGS_REG)
1102 (compare:CC (match_operand:XF 1 "nonmemory_operand" "")
1103 (match_operand:XF 2 "nonmemory_operand" "")))
1104 (set (pc) (if_then_else
1105 (match_operator 0 "ix86_fp_comparison_operator"
1108 (label_ref (match_operand 3 "" ""))
1112 ix86_expand_branch (GET_CODE (operands[0]),
1113 operands[1], operands[2], operands[3]);
1117 (define_expand "cstorexf4"
1118 [(set (reg:CC FLAGS_REG)
1119 (compare:CC (match_operand:XF 2 "nonmemory_operand" "")
1120 (match_operand:XF 3 "nonmemory_operand" "")))
1121 (set (match_operand:QI 0 "register_operand" "")
1122 (match_operator 1 "ix86_fp_comparison_operator"
1127 ix86_expand_setcc (operands[0], GET_CODE (operands[1]),
1128 operands[2], operands[3]);
1132 (define_expand "cbranch<mode>4"
1133 [(set (reg:CC FLAGS_REG)
1134 (compare:CC (match_operand:MODEF 1 "cmp_fp_expander_operand" "")
1135 (match_operand:MODEF 2 "cmp_fp_expander_operand" "")))
1136 (set (pc) (if_then_else
1137 (match_operator 0 "ix86_fp_comparison_operator"
1140 (label_ref (match_operand 3 "" ""))
1142 "TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
1144 ix86_expand_branch (GET_CODE (operands[0]),
1145 operands[1], operands[2], operands[3]);
1149 (define_expand "cstore<mode>4"
1150 [(set (reg:CC FLAGS_REG)
1151 (compare:CC (match_operand:MODEF 2 "cmp_fp_expander_operand" "")
1152 (match_operand:MODEF 3 "cmp_fp_expander_operand" "")))
1153 (set (match_operand:QI 0 "register_operand" "")
1154 (match_operator 1 "ix86_fp_comparison_operator"
1157 "TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
1159 ix86_expand_setcc (operands[0], GET_CODE (operands[1]),
1160 operands[2], operands[3]);
1164 (define_expand "cbranchcc4"
1165 [(set (pc) (if_then_else
1166 (match_operator 0 "comparison_operator"
1167 [(match_operand 1 "flags_reg_operand" "")
1168 (match_operand 2 "const0_operand" "")])
1169 (label_ref (match_operand 3 "" ""))
1173 ix86_expand_branch (GET_CODE (operands[0]),
1174 operands[1], operands[2], operands[3]);
1178 (define_expand "cstorecc4"
1179 [(set (match_operand:QI 0 "register_operand" "")
1180 (match_operator 1 "comparison_operator"
1181 [(match_operand 2 "flags_reg_operand" "")
1182 (match_operand 3 "const0_operand" "")]))]
1185 ix86_expand_setcc (operands[0], GET_CODE (operands[1]),
1186 operands[2], operands[3]);
1191 ;; FP compares, step 1:
1192 ;; Set the FP condition codes.
1194 ;; CCFPmode compare with exceptions
1195 ;; CCFPUmode compare with no exceptions
1197 ;; We may not use "#" to split and emit these, since the REG_DEAD notes
1198 ;; used to manage the reg stack popping would not be preserved.
1200 (define_insn "*cmpfp_0"
1201 [(set (match_operand:HI 0 "register_operand" "=a")
1204 (match_operand 1 "register_operand" "f")
1205 (match_operand 2 "const0_operand" ""))]
1207 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
1208 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
1209 "* return output_fp_compare (insn, operands, false, false);"
1210 [(set_attr "type" "multi")
1211 (set_attr "unit" "i387")
1213 (cond [(match_operand:SF 1 "" "")
1215 (match_operand:DF 1 "" "")
1218 (const_string "XF")))])
1220 (define_insn_and_split "*cmpfp_0_cc"
1221 [(set (reg:CCFP FLAGS_REG)
1223 (match_operand 1 "register_operand" "f")
1224 (match_operand 2 "const0_operand" "")))
1225 (clobber (match_operand:HI 0 "register_operand" "=a"))]
1226 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
1227 && TARGET_SAHF && !TARGET_CMOVE
1228 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
1230 "&& reload_completed"
1233 [(compare:CCFP (match_dup 1)(match_dup 2))]
1235 (set (reg:CC FLAGS_REG)
1236 (unspec:CC [(match_dup 0)] UNSPEC_SAHF))]
1238 [(set_attr "type" "multi")
1239 (set_attr "unit" "i387")
1241 (cond [(match_operand:SF 1 "" "")
1243 (match_operand:DF 1 "" "")
1246 (const_string "XF")))])
1248 (define_insn "*cmpfp_xf"
1249 [(set (match_operand:HI 0 "register_operand" "=a")
1252 (match_operand:XF 1 "register_operand" "f")
1253 (match_operand:XF 2 "register_operand" "f"))]
1256 "* return output_fp_compare (insn, operands, false, false);"
1257 [(set_attr "type" "multi")
1258 (set_attr "unit" "i387")
1259 (set_attr "mode" "XF")])
1261 (define_insn_and_split "*cmpfp_xf_cc"
1262 [(set (reg:CCFP FLAGS_REG)
1264 (match_operand:XF 1 "register_operand" "f")
1265 (match_operand:XF 2 "register_operand" "f")))
1266 (clobber (match_operand:HI 0 "register_operand" "=a"))]
1268 && TARGET_SAHF && !TARGET_CMOVE"
1270 "&& reload_completed"
1273 [(compare:CCFP (match_dup 1)(match_dup 2))]
1275 (set (reg:CC FLAGS_REG)
1276 (unspec:CC [(match_dup 0)] UNSPEC_SAHF))]
1278 [(set_attr "type" "multi")
1279 (set_attr "unit" "i387")
1280 (set_attr "mode" "XF")])
1282 (define_insn "*cmpfp_<mode>"
1283 [(set (match_operand:HI 0 "register_operand" "=a")
1286 (match_operand:MODEF 1 "register_operand" "f")
1287 (match_operand:MODEF 2 "nonimmediate_operand" "fm"))]
1290 "* return output_fp_compare (insn, operands, false, false);"
1291 [(set_attr "type" "multi")
1292 (set_attr "unit" "i387")
1293 (set_attr "mode" "<MODE>")])
1295 (define_insn_and_split "*cmpfp_<mode>_cc"
1296 [(set (reg:CCFP FLAGS_REG)
1298 (match_operand:MODEF 1 "register_operand" "f")
1299 (match_operand:MODEF 2 "nonimmediate_operand" "fm")))
1300 (clobber (match_operand:HI 0 "register_operand" "=a"))]
1302 && TARGET_SAHF && !TARGET_CMOVE"
1304 "&& reload_completed"
1307 [(compare:CCFP (match_dup 1)(match_dup 2))]
1309 (set (reg:CC FLAGS_REG)
1310 (unspec:CC [(match_dup 0)] UNSPEC_SAHF))]
1312 [(set_attr "type" "multi")
1313 (set_attr "unit" "i387")
1314 (set_attr "mode" "<MODE>")])
1316 (define_insn "*cmpfp_u"
1317 [(set (match_operand:HI 0 "register_operand" "=a")
1320 (match_operand 1 "register_operand" "f")
1321 (match_operand 2 "register_operand" "f"))]
1323 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
1324 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
1325 "* return output_fp_compare (insn, operands, false, true);"
1326 [(set_attr "type" "multi")
1327 (set_attr "unit" "i387")
1329 (cond [(match_operand:SF 1 "" "")
1331 (match_operand:DF 1 "" "")
1334 (const_string "XF")))])
1336 (define_insn_and_split "*cmpfp_u_cc"
1337 [(set (reg:CCFPU FLAGS_REG)
1339 (match_operand 1 "register_operand" "f")
1340 (match_operand 2 "register_operand" "f")))
1341 (clobber (match_operand:HI 0 "register_operand" "=a"))]
1342 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
1343 && TARGET_SAHF && !TARGET_CMOVE
1344 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
1346 "&& reload_completed"
1349 [(compare:CCFPU (match_dup 1)(match_dup 2))]
1351 (set (reg:CC FLAGS_REG)
1352 (unspec:CC [(match_dup 0)] UNSPEC_SAHF))]
1354 [(set_attr "type" "multi")
1355 (set_attr "unit" "i387")
1357 (cond [(match_operand:SF 1 "" "")
1359 (match_operand:DF 1 "" "")
1362 (const_string "XF")))])
1364 (define_insn "*cmpfp_<mode>"
1365 [(set (match_operand:HI 0 "register_operand" "=a")
1368 (match_operand 1 "register_operand" "f")
1369 (match_operator 3 "float_operator"
1370 [(match_operand:SWI24 2 "memory_operand" "m")]))]
1372 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
1373 && (TARGET_USE_<MODE>MODE_FIOP || optimize_function_for_size_p (cfun))
1374 && (GET_MODE (operands [3]) == GET_MODE (operands[1]))"
1375 "* return output_fp_compare (insn, operands, false, false);"
1376 [(set_attr "type" "multi")
1377 (set_attr "unit" "i387")
1378 (set_attr "fp_int_src" "true")
1379 (set_attr "mode" "<MODE>")])
1381 (define_insn_and_split "*cmpfp_<mode>_cc"
1382 [(set (reg:CCFP FLAGS_REG)
1384 (match_operand 1 "register_operand" "f")
1385 (match_operator 3 "float_operator"
1386 [(match_operand:SWI24 2 "memory_operand" "m")])))
1387 (clobber (match_operand:HI 0 "register_operand" "=a"))]
1388 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
1389 && TARGET_SAHF && !TARGET_CMOVE
1390 && (TARGET_USE_<MODE>MODE_FIOP || optimize_function_for_size_p (cfun))
1391 && (GET_MODE (operands [3]) == GET_MODE (operands[1]))"
1393 "&& reload_completed"
1398 (match_op_dup 3 [(match_dup 2)]))]
1400 (set (reg:CC FLAGS_REG)
1401 (unspec:CC [(match_dup 0)] UNSPEC_SAHF))]
1403 [(set_attr "type" "multi")
1404 (set_attr "unit" "i387")
1405 (set_attr "fp_int_src" "true")
1406 (set_attr "mode" "<MODE>")])
1408 ;; FP compares, step 2
1409 ;; Move the fpsw to ax.
1411 (define_insn "x86_fnstsw_1"
1412 [(set (match_operand:HI 0 "register_operand" "=a")
1413 (unspec:HI [(reg:CCFP FPSR_REG)] UNSPEC_FNSTSW))]
1416 [(set (attr "length")
1417 (symbol_ref "ix86_attr_length_address_default (insn) + 2"))
1418 (set_attr "mode" "SI")
1419 (set_attr "unit" "i387")])
1421 ;; FP compares, step 3
1422 ;; Get ax into flags, general case.
1424 (define_insn "x86_sahf_1"
1425 [(set (reg:CC FLAGS_REG)
1426 (unspec:CC [(match_operand:HI 0 "register_operand" "a")]
1430 #ifndef HAVE_AS_IX86_SAHF
1432 return ASM_BYTE "0x9e";
1437 [(set_attr "length" "1")
1438 (set_attr "athlon_decode" "vector")
1439 (set_attr "amdfam10_decode" "direct")
1440 (set_attr "bdver1_decode" "direct")
1441 (set_attr "mode" "SI")])
1443 ;; Pentium Pro can do steps 1 through 3 in one go.
1444 ;; comi*, ucomi*, fcomi*, ficomi*, fucomi*
1445 ;; (these i387 instructions set flags directly)
1446 (define_insn "*cmpfp_i_mixed"
1447 [(set (reg:CCFP FLAGS_REG)
1448 (compare:CCFP (match_operand 0 "register_operand" "f,x")
1449 (match_operand 1 "nonimmediate_operand" "f,xm")))]
1450 "TARGET_MIX_SSE_I387
1451 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1452 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1453 "* return output_fp_compare (insn, operands, true, false);"
1454 [(set_attr "type" "fcmp,ssecomi")
1455 (set_attr "prefix" "orig,maybe_vex")
1457 (if_then_else (match_operand:SF 1 "" "")
1459 (const_string "DF")))
1460 (set (attr "prefix_rep")
1461 (if_then_else (eq_attr "type" "ssecomi")
1463 (const_string "*")))
1464 (set (attr "prefix_data16")
1465 (cond [(eq_attr "type" "fcmp")
1467 (eq_attr "mode" "DF")
1470 (const_string "0")))
1471 (set_attr "athlon_decode" "vector")
1472 (set_attr "amdfam10_decode" "direct")
1473 (set_attr "bdver1_decode" "double")])
1475 (define_insn "*cmpfp_i_sse"
1476 [(set (reg:CCFP FLAGS_REG)
1477 (compare:CCFP (match_operand 0 "register_operand" "x")
1478 (match_operand 1 "nonimmediate_operand" "xm")))]
1480 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1481 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1482 "* return output_fp_compare (insn, operands, true, false);"
1483 [(set_attr "type" "ssecomi")
1484 (set_attr "prefix" "maybe_vex")
1486 (if_then_else (match_operand:SF 1 "" "")
1488 (const_string "DF")))
1489 (set_attr "prefix_rep" "0")
1490 (set (attr "prefix_data16")
1491 (if_then_else (eq_attr "mode" "DF")
1493 (const_string "0")))
1494 (set_attr "athlon_decode" "vector")
1495 (set_attr "amdfam10_decode" "direct")
1496 (set_attr "bdver1_decode" "double")])
1498 (define_insn "*cmpfp_i_i387"
1499 [(set (reg:CCFP FLAGS_REG)
1500 (compare:CCFP (match_operand 0 "register_operand" "f")
1501 (match_operand 1 "register_operand" "f")))]
1502 "X87_FLOAT_MODE_P (GET_MODE (operands[0]))
1504 && !(SSE_FLOAT_MODE_P (GET_MODE (operands[0])) && TARGET_SSE_MATH)
1505 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1506 "* return output_fp_compare (insn, operands, true, false);"
1507 [(set_attr "type" "fcmp")
1509 (cond [(match_operand:SF 1 "" "")
1511 (match_operand:DF 1 "" "")
1514 (const_string "XF")))
1515 (set_attr "athlon_decode" "vector")
1516 (set_attr "amdfam10_decode" "direct")
1517 (set_attr "bdver1_decode" "double")])
1519 (define_insn "*cmpfp_iu_mixed"
1520 [(set (reg:CCFPU FLAGS_REG)
1521 (compare:CCFPU (match_operand 0 "register_operand" "f,x")
1522 (match_operand 1 "nonimmediate_operand" "f,xm")))]
1523 "TARGET_MIX_SSE_I387
1524 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1525 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1526 "* return output_fp_compare (insn, operands, true, true);"
1527 [(set_attr "type" "fcmp,ssecomi")
1528 (set_attr "prefix" "orig,maybe_vex")
1530 (if_then_else (match_operand:SF 1 "" "")
1532 (const_string "DF")))
1533 (set (attr "prefix_rep")
1534 (if_then_else (eq_attr "type" "ssecomi")
1536 (const_string "*")))
1537 (set (attr "prefix_data16")
1538 (cond [(eq_attr "type" "fcmp")
1540 (eq_attr "mode" "DF")
1543 (const_string "0")))
1544 (set_attr "athlon_decode" "vector")
1545 (set_attr "amdfam10_decode" "direct")
1546 (set_attr "bdver1_decode" "double")])
1548 (define_insn "*cmpfp_iu_sse"
1549 [(set (reg:CCFPU FLAGS_REG)
1550 (compare:CCFPU (match_operand 0 "register_operand" "x")
1551 (match_operand 1 "nonimmediate_operand" "xm")))]
1553 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1554 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1555 "* return output_fp_compare (insn, operands, true, true);"
1556 [(set_attr "type" "ssecomi")
1557 (set_attr "prefix" "maybe_vex")
1559 (if_then_else (match_operand:SF 1 "" "")
1561 (const_string "DF")))
1562 (set_attr "prefix_rep" "0")
1563 (set (attr "prefix_data16")
1564 (if_then_else (eq_attr "mode" "DF")
1566 (const_string "0")))
1567 (set_attr "athlon_decode" "vector")
1568 (set_attr "amdfam10_decode" "direct")
1569 (set_attr "bdver1_decode" "double")])
1571 (define_insn "*cmpfp_iu_387"
1572 [(set (reg:CCFPU FLAGS_REG)
1573 (compare:CCFPU (match_operand 0 "register_operand" "f")
1574 (match_operand 1 "register_operand" "f")))]
1575 "X87_FLOAT_MODE_P (GET_MODE (operands[0]))
1577 && !(SSE_FLOAT_MODE_P (GET_MODE (operands[0])) && TARGET_SSE_MATH)
1578 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1579 "* return output_fp_compare (insn, operands, true, true);"
1580 [(set_attr "type" "fcmp")
1582 (cond [(match_operand:SF 1 "" "")
1584 (match_operand:DF 1 "" "")
1587 (const_string "XF")))
1588 (set_attr "athlon_decode" "vector")
1589 (set_attr "amdfam10_decode" "direct")
1590 (set_attr "bdver1_decode" "direct")])
1592 ;; Push/pop instructions.
1594 (define_insn "*push<mode>2"
1595 [(set (match_operand:DWI 0 "push_operand" "=<")
1596 (match_operand:DWI 1 "general_no_elim_operand" "riF*o"))]
1599 [(set_attr "type" "multi")
1600 (set_attr "mode" "<MODE>")])
1603 [(set (match_operand:TI 0 "push_operand" "")
1604 (match_operand:TI 1 "general_operand" ""))]
1605 "TARGET_64BIT && reload_completed
1606 && !SSE_REG_P (operands[1])"
1608 "ix86_split_long_move (operands); DONE;")
1610 (define_insn "*pushdi2_rex64"
1611 [(set (match_operand:DI 0 "push_operand" "=<,!<")
1612 (match_operand:DI 1 "general_no_elim_operand" "re*m,n"))]
1617 [(set_attr "type" "push,multi")
1618 (set_attr "mode" "DI")])
1620 ;; Convert impossible pushes of immediate to existing instructions.
1621 ;; First try to get scratch register and go through it. In case this
1622 ;; fails, push sign extended lower part first and then overwrite
1623 ;; upper part by 32bit move.
1625 [(match_scratch:DI 2 "r")
1626 (set (match_operand:DI 0 "push_operand" "")
1627 (match_operand:DI 1 "immediate_operand" ""))]
1628 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
1629 && !x86_64_immediate_operand (operands[1], DImode)"
1630 [(set (match_dup 2) (match_dup 1))
1631 (set (match_dup 0) (match_dup 2))])
1633 ;; We need to define this as both peepholer and splitter for case
1634 ;; peephole2 pass is not run.
1635 ;; "&& 1" is needed to keep it from matching the previous pattern.
1637 [(set (match_operand:DI 0 "push_operand" "")
1638 (match_operand:DI 1 "immediate_operand" ""))]
1639 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
1640 && !x86_64_immediate_operand (operands[1], DImode) && 1"
1641 [(set (match_dup 0) (match_dup 1))
1642 (set (match_dup 2) (match_dup 3))]
1644 split_double_mode (DImode, &operands[1], 1, &operands[2], &operands[3]);
1646 operands[1] = gen_lowpart (DImode, operands[2]);
1647 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
1652 [(set (match_operand:DI 0 "push_operand" "")
1653 (match_operand:DI 1 "immediate_operand" ""))]
1654 "TARGET_64BIT && ((optimize > 0 && flag_peephole2)
1655 ? epilogue_completed : reload_completed)
1656 && !symbolic_operand (operands[1], DImode)
1657 && !x86_64_immediate_operand (operands[1], DImode)"
1658 [(set (match_dup 0) (match_dup 1))
1659 (set (match_dup 2) (match_dup 3))]
1661 split_double_mode (DImode, &operands[1], 1, &operands[2], &operands[3]);
1663 operands[1] = gen_lowpart (DImode, operands[2]);
1664 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
1669 [(set (match_operand:DI 0 "push_operand" "")
1670 (match_operand:DI 1 "general_operand" ""))]
1671 "!TARGET_64BIT && reload_completed
1672 && !(MMX_REG_P (operands[1]) || SSE_REG_P (operands[1]))"
1674 "ix86_split_long_move (operands); DONE;")
1676 (define_insn "*pushsi2"
1677 [(set (match_operand:SI 0 "push_operand" "=<")
1678 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))]
1681 [(set_attr "type" "push")
1682 (set_attr "mode" "SI")])
1684 ;; emit_push_insn when it calls move_by_pieces requires an insn to
1685 ;; "push a byte/word". But actually we use pushl, which has the effect
1686 ;; of rounding the amount pushed up to a word.
1688 ;; For TARGET_64BIT we always round up to 8 bytes.
1689 (define_insn "*push<mode>2_rex64"
1690 [(set (match_operand:SWI124 0 "push_operand" "=X")
1691 (match_operand:SWI124 1 "nonmemory_no_elim_operand" "r<i>"))]
1694 [(set_attr "type" "push")
1695 (set_attr "mode" "DI")])
1697 (define_insn "*push<mode>2"
1698 [(set (match_operand:SWI12 0 "push_operand" "=X")
1699 (match_operand:SWI12 1 "nonmemory_no_elim_operand" "rn"))]
1702 [(set_attr "type" "push")
1703 (set_attr "mode" "SI")])
1705 (define_insn "*push<mode>2_prologue"
1706 [(set (match_operand:P 0 "push_operand" "=<")
1707 (match_operand:P 1 "general_no_elim_operand" "r<i>*m"))
1708 (clobber (mem:BLK (scratch)))]
1710 "push{<imodesuffix>}\t%1"
1711 [(set_attr "type" "push")
1712 (set_attr "mode" "<MODE>")])
1714 (define_insn "*pop<mode>1"
1715 [(set (match_operand:P 0 "nonimmediate_operand" "=r*m")
1716 (match_operand:P 1 "pop_operand" ">"))]
1718 "pop{<imodesuffix>}\t%0"
1719 [(set_attr "type" "pop")
1720 (set_attr "mode" "<MODE>")])
1722 (define_insn "*pop<mode>1_epilogue"
1723 [(set (match_operand:P 0 "nonimmediate_operand" "=r*m")
1724 (match_operand:P 1 "pop_operand" ">"))
1725 (clobber (mem:BLK (scratch)))]
1727 "pop{<imodesuffix>}\t%0"
1728 [(set_attr "type" "pop")
1729 (set_attr "mode" "<MODE>")])
1731 ;; Move instructions.
1733 (define_expand "movoi"
1734 [(set (match_operand:OI 0 "nonimmediate_operand" "")
1735 (match_operand:OI 1 "general_operand" ""))]
1737 "ix86_expand_move (OImode, operands); DONE;")
1739 (define_expand "movti"
1740 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1741 (match_operand:TI 1 "nonimmediate_operand" ""))]
1742 "TARGET_64BIT || TARGET_SSE"
1745 ix86_expand_move (TImode, operands);
1746 else if (push_operand (operands[0], TImode))
1747 ix86_expand_push (TImode, operands[1]);
1749 ix86_expand_vector_move (TImode, operands);
1753 ;; This expands to what emit_move_complex would generate if we didn't
1754 ;; have a movti pattern. Having this avoids problems with reload on
1755 ;; 32-bit targets when SSE is present, but doesn't seem to be harmful
1756 ;; to have around all the time.
1757 (define_expand "movcdi"
1758 [(set (match_operand:CDI 0 "nonimmediate_operand" "")
1759 (match_operand:CDI 1 "general_operand" ""))]
1762 if (push_operand (operands[0], CDImode))
1763 emit_move_complex_push (CDImode, operands[0], operands[1]);
1765 emit_move_complex_parts (operands[0], operands[1]);
1769 (define_expand "mov<mode>"
1770 [(set (match_operand:SWI1248x 0 "nonimmediate_operand" "")
1771 (match_operand:SWI1248x 1 "general_operand" ""))]
1773 "ix86_expand_move (<MODE>mode, operands); DONE;")
1775 (define_insn "*mov<mode>_xor"
1776 [(set (match_operand:SWI48 0 "register_operand" "=r")
1777 (match_operand:SWI48 1 "const0_operand" ""))
1778 (clobber (reg:CC FLAGS_REG))]
1781 [(set_attr "type" "alu1")
1782 (set_attr "mode" "SI")
1783 (set_attr "length_immediate" "0")])
1785 (define_insn "*mov<mode>_or"
1786 [(set (match_operand:SWI48 0 "register_operand" "=r")
1787 (match_operand:SWI48 1 "const_int_operand" ""))
1788 (clobber (reg:CC FLAGS_REG))]
1790 && operands[1] == constm1_rtx"
1791 "or{<imodesuffix>}\t{%1, %0|%0, %1}"
1792 [(set_attr "type" "alu1")
1793 (set_attr "mode" "<MODE>")
1794 (set_attr "length_immediate" "1")])
1796 (define_insn "*movoi_internal_avx"
1797 [(set (match_operand:OI 0 "nonimmediate_operand" "=x,x,m")
1798 (match_operand:OI 1 "vector_move_operand" "C,xm,x"))]
1799 "TARGET_AVX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
1801 switch (which_alternative)
1804 return standard_sse_constant_opcode (insn, operands[1]);
1807 if (misaligned_operand (operands[0], OImode)
1808 || misaligned_operand (operands[1], OImode))
1809 return "vmovdqu\t{%1, %0|%0, %1}";
1811 return "vmovdqa\t{%1, %0|%0, %1}";
1816 [(set_attr "type" "sselog1,ssemov,ssemov")
1817 (set_attr "prefix" "vex")
1818 (set_attr "mode" "OI")])
1820 (define_insn "*movti_internal_rex64"
1821 [(set (match_operand:TI 0 "nonimmediate_operand" "=!r,o,x,x,m")
1822 (match_operand:TI 1 "general_operand" "riFo,re,C,xm,x"))]
1823 "TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
1825 switch (which_alternative)
1831 return standard_sse_constant_opcode (insn, operands[1]);
1834 /* TDmode values are passed as TImode on the stack. Moving them
1835 to stack may result in unaligned memory access. */
1836 if (misaligned_operand (operands[0], TImode)
1837 || misaligned_operand (operands[1], TImode))
1839 if (get_attr_mode (insn) == MODE_V4SF)
1840 return "%vmovups\t{%1, %0|%0, %1}";
1842 return "%vmovdqu\t{%1, %0|%0, %1}";
1846 if (get_attr_mode (insn) == MODE_V4SF)
1847 return "%vmovaps\t{%1, %0|%0, %1}";
1849 return "%vmovdqa\t{%1, %0|%0, %1}";
1855 [(set_attr "type" "*,*,sselog1,ssemov,ssemov")
1856 (set_attr "prefix" "*,*,maybe_vex,maybe_vex,maybe_vex")
1858 (cond [(eq_attr "alternative" "2,3")
1860 (match_test "optimize_function_for_size_p (cfun)")
1861 (const_string "V4SF")
1862 (const_string "TI"))
1863 (eq_attr "alternative" "4")
1865 (ior (match_test "TARGET_SSE_TYPELESS_STORES")
1866 (match_test "optimize_function_for_size_p (cfun)"))
1867 (const_string "V4SF")
1868 (const_string "TI"))]
1869 (const_string "DI")))])
1872 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1873 (match_operand:TI 1 "general_operand" ""))]
1875 && !SSE_REG_P (operands[0]) && !SSE_REG_P (operands[1])"
1877 "ix86_split_long_move (operands); DONE;")
1879 (define_insn "*movti_internal_sse"
1880 [(set (match_operand:TI 0 "nonimmediate_operand" "=x,x,m")
1881 (match_operand:TI 1 "vector_move_operand" "C,xm,x"))]
1882 "TARGET_SSE && !TARGET_64BIT
1883 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
1885 switch (which_alternative)
1888 return standard_sse_constant_opcode (insn, operands[1]);
1891 /* TDmode values are passed as TImode on the stack. Moving them
1892 to stack may result in unaligned memory access. */
1893 if (misaligned_operand (operands[0], TImode)
1894 || misaligned_operand (operands[1], TImode))
1896 if (get_attr_mode (insn) == MODE_V4SF)
1897 return "%vmovups\t{%1, %0|%0, %1}";
1899 return "%vmovdqu\t{%1, %0|%0, %1}";
1903 if (get_attr_mode (insn) == MODE_V4SF)
1904 return "%vmovaps\t{%1, %0|%0, %1}";
1906 return "%vmovdqa\t{%1, %0|%0, %1}";
1912 [(set_attr "type" "sselog1,ssemov,ssemov")
1913 (set_attr "prefix" "maybe_vex")
1915 (cond [(ior (not (match_test "TARGET_SSE2"))
1916 (match_test "optimize_function_for_size_p (cfun)"))
1917 (const_string "V4SF")
1918 (and (eq_attr "alternative" "2")
1919 (match_test "TARGET_SSE_TYPELESS_STORES"))
1920 (const_string "V4SF")]
1921 (const_string "TI")))])
1923 (define_insn "*movdi_internal_rex64"
1924 [(set (match_operand:DI 0 "nonimmediate_operand"
1925 "=r,r ,r,m ,*y,m*y,?*y,?r ,?*Ym,*x,m ,*x,*x,?r ,?*Yi,?*x,?*Ym")
1926 (match_operand:DI 1 "general_operand"
1927 "Z ,rem,i,re,C ,*y ,m ,*Ym,r ,C ,*x,*x,m ,*Yi,r ,*Ym,*x"))]
1928 "TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
1930 switch (get_attr_type (insn))
1933 if (SSE_REG_P (operands[0]))
1934 return "movq2dq\t{%1, %0|%0, %1}";
1936 return "movdq2q\t{%1, %0|%0, %1}";
1939 if (get_attr_mode (insn) == MODE_TI)
1940 return "%vmovdqa\t{%1, %0|%0, %1}";
1941 /* Handle broken assemblers that require movd instead of movq. */
1942 if (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1]))
1943 return "%vmovd\t{%1, %0|%0, %1}";
1945 return "%vmovq\t{%1, %0|%0, %1}";
1948 /* Handle broken assemblers that require movd instead of movq. */
1949 if (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1]))
1950 return "movd\t{%1, %0|%0, %1}";
1952 return "movq\t{%1, %0|%0, %1}";
1955 return standard_sse_constant_opcode (insn, operands[1]);
1958 return "pxor\t%0, %0";
1961 return "lea{q}\t{%E1, %0|%0, %E1}";
1964 gcc_assert (!flag_pic || LEGITIMATE_PIC_OPERAND_P (operands[1]));
1965 if (get_attr_mode (insn) == MODE_SI)
1966 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1967 else if (which_alternative == 2)
1968 return "movabs{q}\t{%1, %0|%0, %1}";
1969 else if (ix86_use_lea_for_mov (insn, operands))
1970 return "lea{q}\t{%E1, %0|%0, %E1}";
1972 return "mov{q}\t{%1, %0|%0, %1}";
1976 (cond [(eq_attr "alternative" "4")
1977 (const_string "mmx")
1978 (eq_attr "alternative" "5,6,7,8")
1979 (const_string "mmxmov")
1980 (eq_attr "alternative" "9")
1981 (const_string "sselog1")
1982 (eq_attr "alternative" "10,11,12,13,14")
1983 (const_string "ssemov")
1984 (eq_attr "alternative" "15,16")
1985 (const_string "ssecvt")
1986 (match_operand 1 "pic_32bit_operand" "")
1987 (const_string "lea")
1989 (const_string "imov")))
1992 (and (eq_attr "alternative" "2") (eq_attr "type" "imov"))
1994 (const_string "*")))
1995 (set (attr "length_immediate")
1997 (and (eq_attr "alternative" "2") (eq_attr "type" "imov"))
1999 (const_string "*")))
2000 (set (attr "prefix_rex")
2001 (if_then_else (eq_attr "alternative" "7,8")
2003 (const_string "*")))
2004 (set (attr "prefix_data16")
2005 (if_then_else (eq_attr "alternative" "10")
2007 (const_string "*")))
2008 (set (attr "prefix")
2009 (if_then_else (eq_attr "alternative" "11,12,13,14,15")
2010 (const_string "maybe_vex")
2011 (const_string "orig")))
2012 (set_attr "mode" "SI,DI,DI,DI,DI,DI,DI,DI,DI,TI,DI,TI,DI,DI,DI,DI,DI")])
2014 ;; Reload patterns to support multi-word load/store
2015 ;; with non-offsetable address.
2016 (define_expand "reload_noff_store"
2017 [(parallel [(match_operand 0 "memory_operand" "=m")
2018 (match_operand 1 "register_operand" "r")
2019 (match_operand:DI 2 "register_operand" "=&r")])]
2022 rtx mem = operands[0];
2023 rtx addr = XEXP (mem, 0);
2025 emit_move_insn (operands[2], addr);
2026 mem = replace_equiv_address_nv (mem, operands[2]);
2028 emit_insn (gen_rtx_SET (VOIDmode, mem, operands[1]));
2032 (define_expand "reload_noff_load"
2033 [(parallel [(match_operand 0 "register_operand" "=r")
2034 (match_operand 1 "memory_operand" "m")
2035 (match_operand:DI 2 "register_operand" "=r")])]
2038 rtx mem = operands[1];
2039 rtx addr = XEXP (mem, 0);
2041 emit_move_insn (operands[2], addr);
2042 mem = replace_equiv_address_nv (mem, operands[2]);
2044 emit_insn (gen_rtx_SET (VOIDmode, operands[0], mem));
2048 (define_insn "*movdi_internal"
2049 [(set (match_operand:DI 0 "nonimmediate_operand"
2050 "=r ,o ,*y,m*y,*y,*x,m ,*x,*x,*x,m ,*x,*x,?*x,?*Ym")
2051 (match_operand:DI 1 "general_operand"
2052 "riFo,riF,C ,*y ,m ,C ,*x,*x,m ,C ,*x,*x,m ,*Ym,*x"))]
2053 "!TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
2055 switch (get_attr_type (insn))
2058 if (SSE_REG_P (operands[0]))
2059 return "movq2dq\t{%1, %0|%0, %1}";
2061 return "movdq2q\t{%1, %0|%0, %1}";
2064 switch (get_attr_mode (insn))
2067 return "%vmovdqa\t{%1, %0|%0, %1}";
2069 return "%vmovq\t{%1, %0|%0, %1}";
2071 return "movaps\t{%1, %0|%0, %1}";
2073 return "movlps\t{%1, %0|%0, %1}";
2079 return "movq\t{%1, %0|%0, %1}";
2082 return standard_sse_constant_opcode (insn, operands[1]);
2085 return "pxor\t%0, %0";
2095 (cond [(eq_attr "alternative" "5,6,7,8,13,14")
2096 (const_string "sse2")
2097 (eq_attr "alternative" "9,10,11,12")
2098 (const_string "noavx")
2100 (const_string "*")))
2102 (cond [(eq_attr "alternative" "0,1")
2103 (const_string "multi")
2104 (eq_attr "alternative" "2")
2105 (const_string "mmx")
2106 (eq_attr "alternative" "3,4")
2107 (const_string "mmxmov")
2108 (eq_attr "alternative" "5,9")
2109 (const_string "sselog1")
2110 (eq_attr "alternative" "13,14")
2111 (const_string "ssecvt")
2113 (const_string "ssemov")))
2114 (set (attr "prefix")
2115 (if_then_else (eq_attr "alternative" "5,6,7,8")
2116 (const_string "maybe_vex")
2117 (const_string "orig")))
2118 (set_attr "mode" "DI,DI,DI,DI,DI,TI,DI,TI,DI,V4SF,V2SF,V4SF,V2SF,DI,DI")])
2121 [(set (match_operand:DI 0 "nonimmediate_operand" "")
2122 (match_operand:DI 1 "general_operand" ""))]
2123 "!TARGET_64BIT && reload_completed
2124 && !(MMX_REG_P (operands[0]) || SSE_REG_P (operands[0]))
2125 && !(MMX_REG_P (operands[1]) || SSE_REG_P (operands[1]))"
2127 "ix86_split_long_move (operands); DONE;")
2129 (define_insn "*movsi_internal"
2130 [(set (match_operand:SI 0 "nonimmediate_operand"
2131 "=r,m ,*y,*y,?rm,?*y,*x,*x,?r ,m ,?*Yi,*x")
2132 (match_operand:SI 1 "general_operand"
2133 "g ,re,C ,*y,*y ,rm ,C ,*x,*Yi,*x,r ,m "))]
2134 "!(MEM_P (operands[0]) && MEM_P (operands[1]))"
2136 switch (get_attr_type (insn))
2139 return standard_sse_constant_opcode (insn, operands[1]);
2142 switch (get_attr_mode (insn))
2145 return "%vmovdqa\t{%1, %0|%0, %1}";
2147 return "%vmovaps\t{%1, %0|%0, %1}";
2149 return "%vmovd\t{%1, %0|%0, %1}";
2151 return "%vmovss\t{%1, %0|%0, %1}";
2157 return "pxor\t%0, %0";
2160 if (get_attr_mode (insn) == MODE_DI)
2161 return "movq\t{%1, %0|%0, %1}";
2162 return "movd\t{%1, %0|%0, %1}";
2165 return "lea{l}\t{%E1, %0|%0, %E1}";
2168 gcc_assert (!flag_pic || LEGITIMATE_PIC_OPERAND_P (operands[1]));
2169 if (ix86_use_lea_for_mov (insn, operands))
2170 return "lea{l}\t{%E1, %0|%0, %E1}";
2172 return "mov{l}\t{%1, %0|%0, %1}";
2176 (cond [(eq_attr "alternative" "2")
2177 (const_string "mmx")
2178 (eq_attr "alternative" "3,4,5")
2179 (const_string "mmxmov")
2180 (eq_attr "alternative" "6")
2181 (const_string "sselog1")
2182 (eq_attr "alternative" "7,8,9,10,11")
2183 (const_string "ssemov")
2184 (match_operand 1 "pic_32bit_operand" "")
2185 (const_string "lea")
2187 (const_string "imov")))
2188 (set (attr "prefix")
2189 (if_then_else (eq_attr "alternative" "0,1,2,3,4,5")
2190 (const_string "orig")
2191 (const_string "maybe_vex")))
2192 (set (attr "prefix_data16")
2193 (if_then_else (and (eq_attr "type" "ssemov") (eq_attr "mode" "SI"))
2195 (const_string "*")))
2197 (cond [(eq_attr "alternative" "2,3")
2199 (eq_attr "alternative" "6,7")
2201 (not (match_test "TARGET_SSE2"))
2202 (const_string "V4SF")
2203 (const_string "TI"))
2204 (and (eq_attr "alternative" "8,9,10,11")
2205 (not (match_test "TARGET_SSE2")))
2208 (const_string "SI")))])
2210 (define_insn "*movhi_internal"
2211 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
2212 (match_operand:HI 1 "general_operand" "r,rn,rm,rn"))]
2213 "!(MEM_P (operands[0]) && MEM_P (operands[1]))"
2215 switch (get_attr_type (insn))
2218 /* movzwl is faster than movw on p2 due to partial word stalls,
2219 though not as fast as an aligned movl. */
2220 return "movz{wl|x}\t{%1, %k0|%k0, %1}";
2222 if (get_attr_mode (insn) == MODE_SI)
2223 return "mov{l}\t{%k1, %k0|%k0, %k1}";
2225 return "mov{w}\t{%1, %0|%0, %1}";
2229 (cond [(match_test "optimize_function_for_size_p (cfun)")
2230 (const_string "imov")
2231 (and (eq_attr "alternative" "0")
2232 (ior (not (match_test "TARGET_PARTIAL_REG_STALL"))
2233 (not (match_test "TARGET_HIMODE_MATH"))))
2234 (const_string "imov")
2235 (and (eq_attr "alternative" "1,2")
2236 (match_operand:HI 1 "aligned_operand" ""))
2237 (const_string "imov")
2238 (and (match_test "TARGET_MOVX")
2239 (eq_attr "alternative" "0,2"))
2240 (const_string "imovx")
2242 (const_string "imov")))
2244 (cond [(eq_attr "type" "imovx")
2246 (and (eq_attr "alternative" "1,2")
2247 (match_operand:HI 1 "aligned_operand" ""))
2249 (and (eq_attr "alternative" "0")
2250 (ior (not (match_test "TARGET_PARTIAL_REG_STALL"))
2251 (not (match_test "TARGET_HIMODE_MATH"))))
2254 (const_string "HI")))])
2256 ;; Situation is quite tricky about when to choose full sized (SImode) move
2257 ;; over QImode moves. For Q_REG -> Q_REG move we use full size only for
2258 ;; partial register dependency machines (such as AMD Athlon), where QImode
2259 ;; moves issue extra dependency and for partial register stalls machines
2260 ;; that don't use QImode patterns (and QImode move cause stall on the next
2263 ;; For loads of Q_REG to NONQ_REG we use full sized moves except for partial
2264 ;; register stall machines with, where we use QImode instructions, since
2265 ;; partial register stall can be caused there. Then we use movzx.
2266 (define_insn "*movqi_internal"
2267 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m")
2268 (match_operand:QI 1 "general_operand" " q,qn,qm,q,rn,qm,qn"))]
2269 "!(MEM_P (operands[0]) && MEM_P (operands[1]))"
2271 switch (get_attr_type (insn))
2274 gcc_assert (ANY_QI_REG_P (operands[1]) || MEM_P (operands[1]));
2275 return "movz{bl|x}\t{%1, %k0|%k0, %1}";
2277 if (get_attr_mode (insn) == MODE_SI)
2278 return "mov{l}\t{%k1, %k0|%k0, %k1}";
2280 return "mov{b}\t{%1, %0|%0, %1}";
2284 (cond [(and (eq_attr "alternative" "5")
2285 (not (match_operand:QI 1 "aligned_operand" "")))
2286 (const_string "imovx")
2287 (match_test "optimize_function_for_size_p (cfun)")
2288 (const_string "imov")
2289 (and (eq_attr "alternative" "3")
2290 (ior (not (match_test "TARGET_PARTIAL_REG_STALL"))
2291 (not (match_test "TARGET_QIMODE_MATH"))))
2292 (const_string "imov")
2293 (eq_attr "alternative" "3,5")
2294 (const_string "imovx")
2295 (and (match_test "TARGET_MOVX")
2296 (eq_attr "alternative" "2"))
2297 (const_string "imovx")
2299 (const_string "imov")))
2301 (cond [(eq_attr "alternative" "3,4,5")
2303 (eq_attr "alternative" "6")
2305 (eq_attr "type" "imovx")
2307 (and (eq_attr "type" "imov")
2308 (and (eq_attr "alternative" "0,1")
2309 (and (match_test "TARGET_PARTIAL_REG_DEPENDENCY")
2310 (and (not (match_test "optimize_function_for_size_p (cfun)"))
2311 (not (match_test "TARGET_PARTIAL_REG_STALL"))))))
2313 ;; Avoid partial register stalls when not using QImode arithmetic
2314 (and (eq_attr "type" "imov")
2315 (and (eq_attr "alternative" "0,1")
2316 (and (match_test "TARGET_PARTIAL_REG_STALL")
2317 (not (match_test "TARGET_QIMODE_MATH")))))
2320 (const_string "QI")))])
2322 ;; Stores and loads of ax to arbitrary constant address.
2323 ;; We fake an second form of instruction to force reload to load address
2324 ;; into register when rax is not available
2325 (define_insn "*movabs<mode>_1"
2326 [(set (mem:SWI1248x (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
2327 (match_operand:SWI1248x 1 "nonmemory_operand" "a,r<i>"))]
2328 "TARGET_LP64 && ix86_check_movabs (insn, 0)"
2330 movabs{<imodesuffix>}\t{%1, %P0|[%P0], %1}
2331 mov{<imodesuffix>}\t{%1, %a0|%a0, %1}"
2332 [(set_attr "type" "imov")
2333 (set_attr "modrm" "0,*")
2334 (set_attr "length_address" "8,0")
2335 (set_attr "length_immediate" "0,*")
2336 (set_attr "memory" "store")
2337 (set_attr "mode" "<MODE>")])
2339 (define_insn "*movabs<mode>_2"
2340 [(set (match_operand:SWI1248x 0 "register_operand" "=a,r")
2341 (mem:SWI1248x (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
2342 "TARGET_LP64 && ix86_check_movabs (insn, 1)"
2344 movabs{<imodesuffix>}\t{%P1, %0|%0, [%P1]}
2345 mov{<imodesuffix>}\t{%a1, %0|%0, %a1}"
2346 [(set_attr "type" "imov")
2347 (set_attr "modrm" "0,*")
2348 (set_attr "length_address" "8,0")
2349 (set_attr "length_immediate" "0")
2350 (set_attr "memory" "load")
2351 (set_attr "mode" "<MODE>")])
2353 (define_insn "*swap<mode>"
2354 [(set (match_operand:SWI48 0 "register_operand" "+r")
2355 (match_operand:SWI48 1 "register_operand" "+r"))
2359 "xchg{<imodesuffix>}\t%1, %0"
2360 [(set_attr "type" "imov")
2361 (set_attr "mode" "<MODE>")
2362 (set_attr "pent_pair" "np")
2363 (set_attr "athlon_decode" "vector")
2364 (set_attr "amdfam10_decode" "double")
2365 (set_attr "bdver1_decode" "double")])
2367 (define_insn "*swap<mode>_1"
2368 [(set (match_operand:SWI12 0 "register_operand" "+r")
2369 (match_operand:SWI12 1 "register_operand" "+r"))
2372 "!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)"
2374 [(set_attr "type" "imov")
2375 (set_attr "mode" "SI")
2376 (set_attr "pent_pair" "np")
2377 (set_attr "athlon_decode" "vector")
2378 (set_attr "amdfam10_decode" "double")
2379 (set_attr "bdver1_decode" "double")])
2381 ;; Not added amdfam10_decode since TARGET_PARTIAL_REG_STALL
2382 ;; is disabled for AMDFAM10
2383 (define_insn "*swap<mode>_2"
2384 [(set (match_operand:SWI12 0 "register_operand" "+<r>")
2385 (match_operand:SWI12 1 "register_operand" "+<r>"))
2388 "TARGET_PARTIAL_REG_STALL"
2389 "xchg{<imodesuffix>}\t%1, %0"
2390 [(set_attr "type" "imov")
2391 (set_attr "mode" "<MODE>")
2392 (set_attr "pent_pair" "np")
2393 (set_attr "athlon_decode" "vector")])
2395 (define_expand "movstrict<mode>"
2396 [(set (strict_low_part (match_operand:SWI12 0 "nonimmediate_operand" ""))
2397 (match_operand:SWI12 1 "general_operand" ""))]
2400 if (TARGET_PARTIAL_REG_STALL && optimize_function_for_speed_p (cfun))
2402 if (GET_CODE (operands[0]) == SUBREG
2403 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (operands[0]))) != MODE_INT)
2405 /* Don't generate memory->memory moves, go through a register */
2406 if (MEM_P (operands[0]) && MEM_P (operands[1]))
2407 operands[1] = force_reg (<MODE>mode, operands[1]);
2410 (define_insn "*movstrict<mode>_1"
2411 [(set (strict_low_part
2412 (match_operand:SWI12 0 "nonimmediate_operand" "+<r>m,<r>"))
2413 (match_operand:SWI12 1 "general_operand" "<r>n,m"))]
2414 "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
2415 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
2416 "mov{<imodesuffix>}\t{%1, %0|%0, %1}"
2417 [(set_attr "type" "imov")
2418 (set_attr "mode" "<MODE>")])
2420 (define_insn "*movstrict<mode>_xor"
2421 [(set (strict_low_part (match_operand:SWI12 0 "register_operand" "+<r>"))
2422 (match_operand:SWI12 1 "const0_operand" ""))
2423 (clobber (reg:CC FLAGS_REG))]
2425 "xor{<imodesuffix>}\t%0, %0"
2426 [(set_attr "type" "alu1")
2427 (set_attr "mode" "<MODE>")
2428 (set_attr "length_immediate" "0")])
2430 (define_insn "*mov<mode>_extv_1"
2431 [(set (match_operand:SWI24 0 "register_operand" "=R")
2432 (sign_extract:SWI24 (match_operand 1 "ext_register_operand" "Q")
2436 "movs{bl|x}\t{%h1, %k0|%k0, %h1}"
2437 [(set_attr "type" "imovx")
2438 (set_attr "mode" "SI")])
2440 (define_insn "*movqi_extv_1_rex64"
2441 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
2442 (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
2447 switch (get_attr_type (insn))
2450 return "movs{bl|x}\t{%h1, %k0|%k0, %h1}";
2452 return "mov{b}\t{%h1, %0|%0, %h1}";
2456 (if_then_else (ior (not (match_operand:QI 0 "QIreg_operand" ""))
2457 (match_test "TARGET_MOVX"))
2458 (const_string "imovx")
2459 (const_string "imov")))
2461 (if_then_else (eq_attr "type" "imovx")
2463 (const_string "QI")))])
2465 (define_insn "*movqi_extv_1"
2466 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?r")
2467 (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
2472 switch (get_attr_type (insn))
2475 return "movs{bl|x}\t{%h1, %k0|%k0, %h1}";
2477 return "mov{b}\t{%h1, %0|%0, %h1}";
2481 (if_then_else (and (match_operand:QI 0 "register_operand" "")
2482 (ior (not (match_operand:QI 0 "QIreg_operand" ""))
2483 (match_test "TARGET_MOVX")))
2484 (const_string "imovx")
2485 (const_string "imov")))
2487 (if_then_else (eq_attr "type" "imovx")
2489 (const_string "QI")))])
2491 (define_insn "*mov<mode>_extzv_1"
2492 [(set (match_operand:SWI48 0 "register_operand" "=R")
2493 (zero_extract:SWI48 (match_operand 1 "ext_register_operand" "Q")
2497 "movz{bl|x}\t{%h1, %k0|%k0, %h1}"
2498 [(set_attr "type" "imovx")
2499 (set_attr "mode" "SI")])
2501 (define_insn "*movqi_extzv_2_rex64"
2502 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
2504 (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
2509 switch (get_attr_type (insn))
2512 return "movz{bl|x}\t{%h1, %k0|%k0, %h1}";
2514 return "mov{b}\t{%h1, %0|%0, %h1}";
2518 (if_then_else (ior (not (match_operand:QI 0 "QIreg_operand" ""))
2519 (match_test "TARGET_MOVX"))
2520 (const_string "imovx")
2521 (const_string "imov")))
2523 (if_then_else (eq_attr "type" "imovx")
2525 (const_string "QI")))])
2527 (define_insn "*movqi_extzv_2"
2528 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?R")
2530 (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
2535 switch (get_attr_type (insn))
2538 return "movz{bl|x}\t{%h1, %k0|%k0, %h1}";
2540 return "mov{b}\t{%h1, %0|%0, %h1}";
2544 (if_then_else (and (match_operand:QI 0 "register_operand" "")
2545 (ior (not (match_operand:QI 0 "QIreg_operand" ""))
2546 (match_test "TARGET_MOVX")))
2547 (const_string "imovx")
2548 (const_string "imov")))
2550 (if_then_else (eq_attr "type" "imovx")
2552 (const_string "QI")))])
2554 (define_expand "mov<mode>_insv_1"
2555 [(set (zero_extract:SWI48 (match_operand 0 "ext_register_operand" "")
2558 (match_operand:SWI48 1 "nonmemory_operand" ""))])
2560 (define_insn "*mov<mode>_insv_1_rex64"
2561 [(set (zero_extract:SWI48x (match_operand 0 "ext_register_operand" "+Q")
2564 (match_operand:SWI48x 1 "nonmemory_operand" "Qn"))]
2567 if (CONST_INT_P (operands[1]))
2568 operands[1] = simplify_gen_subreg (QImode, operands[1], <MODE>mode, 0);
2569 return "mov{b}\t{%b1, %h0|%h0, %b1}";
2571 [(set_attr "type" "imov")
2572 (set_attr "mode" "QI")])
2574 (define_insn "*movsi_insv_1"
2575 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
2578 (match_operand:SI 1 "general_operand" "Qmn"))]
2581 if (CONST_INT_P (operands[1]))
2582 operands[1] = simplify_gen_subreg (QImode, operands[1], SImode, 0);
2583 return "mov{b}\t{%b1, %h0|%h0, %b1}";
2585 [(set_attr "type" "imov")
2586 (set_attr "mode" "QI")])
2588 (define_insn "*movqi_insv_2"
2589 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
2592 (lshiftrt:SI (match_operand:SI 1 "register_operand" "Q")
2595 "mov{b}\t{%h1, %h0|%h0, %h1}"
2596 [(set_attr "type" "imov")
2597 (set_attr "mode" "QI")])
2599 ;; Floating point push instructions.
2601 (define_insn "*pushtf"
2602 [(set (match_operand:TF 0 "push_operand" "=<,<,<")
2603 (match_operand:TF 1 "general_no_elim_operand" "x,Fo,*r"))]
2606 /* This insn should be already split before reg-stack. */
2609 [(set_attr "type" "multi")
2610 (set_attr "unit" "sse,*,*")
2611 (set_attr "mode" "TF,SI,SI")])
2613 ;; %%% Kill this when call knows how to work this out.
2615 [(set (match_operand:TF 0 "push_operand" "")
2616 (match_operand:TF 1 "sse_reg_operand" ""))]
2617 "TARGET_SSE2 && reload_completed"
2618 [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (const_int -16)))
2619 (set (mem:TF (reg:P SP_REG)) (match_dup 1))])
2621 (define_insn "*pushxf"
2622 [(set (match_operand:XF 0 "push_operand" "=<,<")
2623 (match_operand:XF 1 "general_no_elim_operand" "f,ro"))]
2624 "optimize_function_for_speed_p (cfun)"
2626 /* This insn should be already split before reg-stack. */
2629 [(set_attr "type" "multi")
2630 (set_attr "unit" "i387,*")
2631 (set_attr "mode" "XF,SI")])
2633 ;; Size of pushxf is 3 (for sub) + 2 (for fstp) + memory operand size.
2634 ;; Size of pushxf using integer instructions is 3+3*memory operand size
2635 ;; Pushing using integer instructions is longer except for constants
2636 ;; and direct memory references (assuming that any given constant is pushed
2637 ;; only once, but this ought to be handled elsewhere).
2639 (define_insn "*pushxf_nointeger"
2640 [(set (match_operand:XF 0 "push_operand" "=<,<")
2641 (match_operand:XF 1 "general_no_elim_operand" "f,*rFo"))]
2642 "optimize_function_for_size_p (cfun)"
2644 /* This insn should be already split before reg-stack. */
2647 [(set_attr "type" "multi")
2648 (set_attr "unit" "i387,*")
2649 (set_attr "mode" "XF,SI")])
2651 ;; %%% Kill this when call knows how to work this out.
2653 [(set (match_operand:XF 0 "push_operand" "")
2654 (match_operand:XF 1 "fp_register_operand" ""))]
2656 [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (match_dup 2)))
2657 (set (mem:XF (reg:P SP_REG)) (match_dup 1))]
2658 "operands[2] = GEN_INT (-GET_MODE_SIZE (XFmode));")
2660 (define_insn "*pushdf_rex64"
2661 [(set (match_operand:DF 0 "push_operand" "=<,<,<")
2662 (match_operand:DF 1 "general_no_elim_operand" "f,Yd*rFm,x"))]
2665 /* This insn should be already split before reg-stack. */
2668 [(set_attr "type" "multi")
2669 (set_attr "unit" "i387,*,*")
2670 (set_attr "mode" "DF,DI,DF")])
2672 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
2673 ;; Size of pushdf using integer instructions is 2+2*memory operand size
2674 ;; On the average, pushdf using integers can be still shorter.
2676 (define_insn "*pushdf"
2677 [(set (match_operand:DF 0 "push_operand" "=<,<,<")
2678 (match_operand:DF 1 "general_no_elim_operand" "f,Yd*rFo,x"))]
2681 /* This insn should be already split before reg-stack. */
2684 [(set_attr "isa" "*,*,sse2")
2685 (set_attr "type" "multi")
2686 (set_attr "unit" "i387,*,*")
2687 (set_attr "mode" "DF,DI,DF")])
2689 ;; %%% Kill this when call knows how to work this out.
2691 [(set (match_operand:DF 0 "push_operand" "")
2692 (match_operand:DF 1 "any_fp_register_operand" ""))]
2694 [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (const_int -8)))
2695 (set (mem:DF (reg:P SP_REG)) (match_dup 1))])
2697 (define_insn "*pushsf_rex64"
2698 [(set (match_operand:SF 0 "push_operand" "=X,X,X")
2699 (match_operand:SF 1 "nonmemory_no_elim_operand" "f,rF,x"))]
2702 /* Anything else should be already split before reg-stack. */
2703 gcc_assert (which_alternative == 1);
2704 return "push{q}\t%q1";
2706 [(set_attr "type" "multi,push,multi")
2707 (set_attr "unit" "i387,*,*")
2708 (set_attr "mode" "SF,DI,SF")])
2710 (define_insn "*pushsf"
2711 [(set (match_operand:SF 0 "push_operand" "=<,<,<")
2712 (match_operand:SF 1 "general_no_elim_operand" "f,rFm,x"))]
2715 /* Anything else should be already split before reg-stack. */
2716 gcc_assert (which_alternative == 1);
2717 return "push{l}\t%1";
2719 [(set_attr "type" "multi,push,multi")
2720 (set_attr "unit" "i387,*,*")
2721 (set_attr "mode" "SF,SI,SF")])
2723 ;; %%% Kill this when call knows how to work this out.
2725 [(set (match_operand:SF 0 "push_operand" "")
2726 (match_operand:SF 1 "any_fp_register_operand" ""))]
2728 [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (match_dup 2)))
2729 (set (mem:SF (reg:P SP_REG)) (match_dup 1))]
2730 "operands[2] = GEN_INT (-GET_MODE_SIZE (<P:MODE>mode));")
2733 [(set (match_operand:SF 0 "push_operand" "")
2734 (match_operand:SF 1 "memory_operand" ""))]
2736 && (operands[2] = find_constant_src (insn))"
2737 [(set (match_dup 0) (match_dup 2))])
2740 [(set (match_operand 0 "push_operand" "")
2741 (match_operand 1 "general_operand" ""))]
2743 && (GET_MODE (operands[0]) == TFmode
2744 || GET_MODE (operands[0]) == XFmode
2745 || GET_MODE (operands[0]) == DFmode)
2746 && !ANY_FP_REG_P (operands[1])"
2748 "ix86_split_long_move (operands); DONE;")
2750 ;; Floating point move instructions.
2752 (define_expand "movtf"
2753 [(set (match_operand:TF 0 "nonimmediate_operand" "")
2754 (match_operand:TF 1 "nonimmediate_operand" ""))]
2755 "TARGET_64BIT || TARGET_SSE2"
2757 ix86_expand_move (TFmode, operands);
2761 (define_expand "mov<mode>"
2762 [(set (match_operand:X87MODEF 0 "nonimmediate_operand" "")
2763 (match_operand:X87MODEF 1 "general_operand" ""))]
2765 "ix86_expand_move (<MODE>mode, operands); DONE;")
2767 (define_insn "*movtf_internal_rex64"
2768 [(set (match_operand:TF 0 "nonimmediate_operand" "=x,m,x,?*r ,!o")
2769 (match_operand:TF 1 "general_operand" "xm,x,C,*roF,*r"))]
2770 "TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))
2771 && (!can_create_pseudo_p ()
2772 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2773 || GET_CODE (operands[1]) != CONST_DOUBLE
2774 || (optimize_function_for_size_p (cfun)
2775 && standard_sse_constant_p (operands[1])
2776 && !memory_operand (operands[0], TFmode))
2777 || (!TARGET_MEMORY_MISMATCH_STALL
2778 && memory_operand (operands[0], TFmode)))"
2780 switch (which_alternative)
2784 /* Handle misaligned load/store since we
2785 don't have movmisaligntf pattern. */
2786 if (misaligned_operand (operands[0], TFmode)
2787 || misaligned_operand (operands[1], TFmode))
2789 if (get_attr_mode (insn) == MODE_V4SF)
2790 return "%vmovups\t{%1, %0|%0, %1}";
2792 return "%vmovdqu\t{%1, %0|%0, %1}";
2796 if (get_attr_mode (insn) == MODE_V4SF)
2797 return "%vmovaps\t{%1, %0|%0, %1}";
2799 return "%vmovdqa\t{%1, %0|%0, %1}";
2803 return standard_sse_constant_opcode (insn, operands[1]);
2813 [(set_attr "type" "ssemov,ssemov,sselog1,*,*")
2814 (set_attr "prefix" "maybe_vex,maybe_vex,maybe_vex,*,*")
2816 (cond [(eq_attr "alternative" "0,2")
2818 (match_test "optimize_function_for_size_p (cfun)")
2819 (const_string "V4SF")
2820 (const_string "TI"))
2821 (eq_attr "alternative" "1")
2823 (ior (match_test "TARGET_SSE_TYPELESS_STORES")
2824 (match_test "optimize_function_for_size_p (cfun)"))
2825 (const_string "V4SF")
2826 (const_string "TI"))]
2827 (const_string "DI")))])
2829 (define_insn "*movtf_internal_sse2"
2830 [(set (match_operand:TF 0 "nonimmediate_operand" "=x,m,x")
2831 (match_operand:TF 1 "general_operand" "xm,x,C"))]
2832 "TARGET_SSE2 && !TARGET_64BIT
2833 && !(MEM_P (operands[0]) && MEM_P (operands[1]))
2834 && (!can_create_pseudo_p ()
2835 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2836 || GET_CODE (operands[1]) != CONST_DOUBLE
2837 || (optimize_function_for_size_p (cfun)
2838 && standard_sse_constant_p (operands[1])
2839 && !memory_operand (operands[0], TFmode))
2840 || (!TARGET_MEMORY_MISMATCH_STALL
2841 && memory_operand (operands[0], TFmode)))"
2843 switch (which_alternative)
2847 /* Handle misaligned load/store since we
2848 don't have movmisaligntf pattern. */
2849 if (misaligned_operand (operands[0], TFmode)
2850 || misaligned_operand (operands[1], TFmode))
2852 if (get_attr_mode (insn) == MODE_V4SF)
2853 return "%vmovups\t{%1, %0|%0, %1}";
2855 return "%vmovdqu\t{%1, %0|%0, %1}";
2859 if (get_attr_mode (insn) == MODE_V4SF)
2860 return "%vmovaps\t{%1, %0|%0, %1}";
2862 return "%vmovdqa\t{%1, %0|%0, %1}";
2866 return standard_sse_constant_opcode (insn, operands[1]);
2872 [(set_attr "type" "ssemov,ssemov,sselog1")
2873 (set_attr "prefix" "maybe_vex")
2875 (cond [(eq_attr "alternative" "0,2")
2877 (match_test "optimize_function_for_size_p (cfun)")
2878 (const_string "V4SF")
2879 (const_string "TI"))
2880 (eq_attr "alternative" "1")
2882 (ior (match_test "TARGET_SSE_TYPELESS_STORES")
2883 (match_test "optimize_function_for_size_p (cfun)"))
2884 (const_string "V4SF")
2885 (const_string "TI"))]
2886 (const_string "DI")))])
2888 (define_insn "*movxf_internal_rex64"
2889 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,?Yx*r ,!o")
2890 (match_operand:XF 1 "general_operand" "fm,f,G,Yx*roF,Yx*rC"))]
2891 "TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))
2892 && (!can_create_pseudo_p ()
2893 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2894 || GET_CODE (operands[1]) != CONST_DOUBLE
2895 || (optimize_function_for_size_p (cfun)
2896 && standard_80387_constant_p (operands[1]) > 0
2897 && !memory_operand (operands[0], XFmode))
2898 || (!TARGET_MEMORY_MISMATCH_STALL
2899 && memory_operand (operands[0], XFmode)))"
2901 switch (which_alternative)
2905 return output_387_reg_move (insn, operands);
2908 return standard_80387_constant_opcode (operands[1]);
2918 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2919 (set_attr "mode" "XF,XF,XF,SI,SI")])
2921 ;; Possible store forwarding (partial memory) stall in alternative 4.
2922 (define_insn "*movxf_internal"
2923 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,?Yx*r ,!o")
2924 (match_operand:XF 1 "general_operand" "fm,f,G,Yx*roF,Yx*rF"))]
2925 "!TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))
2926 && (!can_create_pseudo_p ()
2927 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2928 || GET_CODE (operands[1]) != CONST_DOUBLE
2929 || (optimize_function_for_size_p (cfun)
2930 && standard_80387_constant_p (operands[1]) > 0
2931 && !memory_operand (operands[0], XFmode))
2932 || (!TARGET_MEMORY_MISMATCH_STALL
2933 && memory_operand (operands[0], XFmode)))"
2935 switch (which_alternative)
2939 return output_387_reg_move (insn, operands);
2942 return standard_80387_constant_opcode (operands[1]);
2952 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2953 (set_attr "mode" "XF,XF,XF,SI,SI")])
2955 (define_insn "*movdf_internal_rex64"
2956 [(set (match_operand:DF 0 "nonimmediate_operand"
2957 "=?Yf*f,?m ,?Yf*f,?r,?m,?r,?r,x,x,x,m,Yi,r ")
2958 (match_operand:DF 1 "general_operand"
2959 "Yf*fm ,Yf*f ,G ,rm,rC,C ,F ,C,x,m,x,r ,Yi"))]
2960 "TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))
2961 && (!can_create_pseudo_p ()
2962 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2963 || GET_CODE (operands[1]) != CONST_DOUBLE
2964 || (optimize_function_for_size_p (cfun)
2965 && ((!(TARGET_SSE2 && TARGET_SSE_MATH)
2966 && standard_80387_constant_p (operands[1]) > 0)
2967 || (TARGET_SSE2 && TARGET_SSE_MATH
2968 && standard_sse_constant_p (operands[1]))))
2969 || memory_operand (operands[0], DFmode))"
2971 switch (which_alternative)
2975 return output_387_reg_move (insn, operands);
2978 return standard_80387_constant_opcode (operands[1]);
2982 return "mov{q}\t{%1, %0|%0, %1}";
2985 return "mov{l}\t{%1, %k0|%k0, %1}";
2988 return "movabs{q}\t{%1, %0|%0, %1}";
2991 return standard_sse_constant_opcode (insn, operands[1]);
2996 switch (get_attr_mode (insn))
2999 if (!TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
3000 return "%vmovapd\t{%1, %0|%0, %1}";
3002 return "%vmovaps\t{%1, %0|%0, %1}";
3005 return "%vmovq\t{%1, %0|%0, %1}";
3007 if (TARGET_AVX && REG_P (operands[0]) && REG_P (operands[1]))
3008 return "vmovsd\t{%1, %0, %0|%0, %0, %1}";
3009 return "%vmovsd\t{%1, %0|%0, %1}";
3011 return "%vmovlpd\t{%1, %d0|%d0, %1}";
3013 return "%vmovlps\t{%1, %d0|%d0, %1}";
3020 /* Handle broken assemblers that require movd instead of movq. */
3021 return "%vmovd\t{%1, %0|%0, %1}";
3028 (cond [(eq_attr "alternative" "0,1,2")
3029 (const_string "fmov")
3030 (eq_attr "alternative" "3,4,5,6")
3031 (const_string "imov")
3032 (eq_attr "alternative" "7")
3033 (const_string "sselog1")
3035 (const_string "ssemov")))
3038 (and (eq_attr "alternative" "6") (eq_attr "type" "imov"))
3040 (const_string "*")))
3041 (set (attr "length_immediate")
3043 (and (eq_attr "alternative" "6") (eq_attr "type" "imov"))
3045 (const_string "*")))
3046 (set (attr "prefix")
3047 (if_then_else (eq_attr "alternative" "0,1,2,3,4,5,6")
3048 (const_string "orig")
3049 (const_string "maybe_vex")))
3050 (set (attr "prefix_data16")
3051 (if_then_else (eq_attr "mode" "V1DF")
3053 (const_string "*")))
3055 (cond [(eq_attr "alternative" "0,1,2")
3057 (eq_attr "alternative" "3,4,6,11,12")
3059 (eq_attr "alternative" "5")
3062 /* xorps is one byte shorter. */
3063 (eq_attr "alternative" "7")
3064 (cond [(match_test "optimize_function_for_size_p (cfun)")
3065 (const_string "V4SF")
3066 (match_test "TARGET_SSE_LOAD0_BY_PXOR")
3069 (const_string "V2DF"))
3071 /* For architectures resolving dependencies on
3072 whole SSE registers use APD move to break dependency
3073 chains, otherwise use short move to avoid extra work.
3075 movaps encodes one byte shorter. */
3076 (eq_attr "alternative" "8")
3078 [(match_test "optimize_function_for_size_p (cfun)")
3079 (const_string "V4SF")
3080 (match_test "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
3081 (const_string "V2DF")
3083 (const_string "DF"))
3084 /* For architectures resolving dependencies on register
3085 parts we may avoid extra work to zero out upper part
3087 (eq_attr "alternative" "9")
3089 (match_test "TARGET_SSE_SPLIT_REGS")
3090 (const_string "V1DF")
3091 (const_string "DF"))
3093 (const_string "DF")))])
3095 ;; Possible store forwarding (partial memory) stall in alternative 4.
3096 (define_insn "*movdf_internal"
3097 [(set (match_operand:DF 0 "nonimmediate_operand"
3098 "=Yf*f,m ,Yf*f,?Yd*r ,!o ,x,x,x,m,*x,*x,*x,m")
3099 (match_operand:DF 1 "general_operand"
3100 "Yf*fm,Yf*f,G ,Yd*roF,Yd*rF,C,x,m,x,C ,*x,m ,*x"))]
3101 "!TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))
3102 && (!can_create_pseudo_p ()
3103 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
3104 || GET_CODE (operands[1]) != CONST_DOUBLE
3105 || (optimize_function_for_size_p (cfun)
3106 && ((!(TARGET_SSE2 && TARGET_SSE_MATH)
3107 && standard_80387_constant_p (operands[1]) > 0)
3108 || (TARGET_SSE2 && TARGET_SSE_MATH
3109 && standard_sse_constant_p (operands[1])))
3110 && !memory_operand (operands[0], DFmode))
3111 || (!TARGET_MEMORY_MISMATCH_STALL
3112 && memory_operand (operands[0], DFmode)))"
3114 switch (which_alternative)
3118 return output_387_reg_move (insn, operands);
3121 return standard_80387_constant_opcode (operands[1]);
3129 return standard_sse_constant_opcode (insn, operands[1]);
3137 switch (get_attr_mode (insn))
3140 if (!TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
3141 return "%vmovapd\t{%1, %0|%0, %1}";
3143 return "%vmovaps\t{%1, %0|%0, %1}";
3146 return "%vmovq\t{%1, %0|%0, %1}";
3148 if (TARGET_AVX && REG_P (operands[0]) && REG_P (operands[1]))
3149 return "vmovsd\t{%1, %0, %0|%0, %0, %1}";
3150 return "%vmovsd\t{%1, %0|%0, %1}";
3152 return "%vmovlpd\t{%1, %d0|%d0, %1}";
3154 return "%vmovlps\t{%1, %d0|%d0, %1}";
3164 (if_then_else (eq_attr "alternative" "5,6,7,8")
3165 (const_string "sse2")
3166 (const_string "*")))
3168 (cond [(eq_attr "alternative" "0,1,2")
3169 (const_string "fmov")
3170 (eq_attr "alternative" "3,4")
3171 (const_string "multi")
3172 (eq_attr "alternative" "5,9")
3173 (const_string "sselog1")
3175 (const_string "ssemov")))
3176 (set (attr "prefix")
3177 (if_then_else (eq_attr "alternative" "0,1,2,3,4")
3178 (const_string "orig")
3179 (const_string "maybe_vex")))
3180 (set (attr "prefix_data16")
3181 (if_then_else (eq_attr "mode" "V1DF")
3183 (const_string "*")))
3185 (cond [(eq_attr "alternative" "0,1,2")
3187 (eq_attr "alternative" "3,4")
3190 /* For SSE1, we have many fewer alternatives. */
3191 (not (match_test "TARGET_SSE2"))
3193 (eq_attr "alternative" "5,6,9,10")
3194 (const_string "V4SF")
3195 (const_string "V2SF"))
3197 /* xorps is one byte shorter. */
3198 (eq_attr "alternative" "5,9")
3199 (cond [(match_test "optimize_function_for_size_p (cfun)")
3200 (const_string "V4SF")
3201 (match_test "TARGET_SSE_LOAD0_BY_PXOR")
3204 (const_string "V2DF"))
3206 /* For architectures resolving dependencies on
3207 whole SSE registers use APD move to break dependency
3208 chains, otherwise use short move to avoid extra work.
3210 movaps encodes one byte shorter. */
3211 (eq_attr "alternative" "6,10")
3213 [(match_test "optimize_function_for_size_p (cfun)")
3214 (const_string "V4SF")
3215 (match_test "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
3216 (const_string "V2DF")
3218 (const_string "DF"))
3219 /* For architectures resolving dependencies on register
3220 parts we may avoid extra work to zero out upper part
3222 (eq_attr "alternative" "7,11")
3224 (match_test "TARGET_SSE_SPLIT_REGS")
3225 (const_string "V1DF")
3226 (const_string "DF"))
3228 (const_string "DF")))])
3230 (define_insn "*movsf_internal"
3231 [(set (match_operand:SF 0 "nonimmediate_operand"
3232 "=Yf*f,m ,Yf*f,?r ,?m,x,x,x,m,!*y,!m,!*y,?Yi,?r,!*Ym,!r")
3233 (match_operand:SF 1 "general_operand"
3234 "Yf*fm,Yf*f,G ,rmF,rF,C,x,m,x,m ,*y,*y ,r ,Yi,r ,*Ym"))]
3235 "!(MEM_P (operands[0]) && MEM_P (operands[1]))
3236 && (!can_create_pseudo_p ()
3237 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
3238 || GET_CODE (operands[1]) != CONST_DOUBLE
3239 || (optimize_function_for_size_p (cfun)
3240 && ((!TARGET_SSE_MATH
3241 && standard_80387_constant_p (operands[1]) > 0)
3243 && standard_sse_constant_p (operands[1]))))
3244 || memory_operand (operands[0], SFmode))"
3246 switch (which_alternative)
3250 return output_387_reg_move (insn, operands);
3253 return standard_80387_constant_opcode (operands[1]);
3257 return "mov{l}\t{%1, %0|%0, %1}";
3260 return standard_sse_constant_opcode (insn, operands[1]);
3263 if (get_attr_mode (insn) == MODE_V4SF)
3264 return "%vmovaps\t{%1, %0|%0, %1}";
3266 return "vmovss\t{%1, %0, %0|%0, %0, %1}";
3270 return "%vmovss\t{%1, %0|%0, %1}";
3276 return "movd\t{%1, %0|%0, %1}";
3279 return "movq\t{%1, %0|%0, %1}";
3283 return "%vmovd\t{%1, %0|%0, %1}";
3290 (cond [(eq_attr "alternative" "0,1,2")
3291 (const_string "fmov")
3292 (eq_attr "alternative" "3,4")
3293 (const_string "imov")
3294 (eq_attr "alternative" "5")
3295 (const_string "sselog1")
3296 (eq_attr "alternative" "9,10,11,14,15")
3297 (const_string "mmxmov")
3299 (const_string "ssemov")))
3300 (set (attr "prefix")
3301 (if_then_else (eq_attr "alternative" "5,6,7,8,12,13")
3302 (const_string "maybe_vex")
3303 (const_string "orig")))
3305 (cond [(eq_attr "alternative" "3,4,9,10")
3307 (eq_attr "alternative" "5")
3309 (and (and (match_test "TARGET_SSE_LOAD0_BY_PXOR")
3310 (match_test "TARGET_SSE2"))
3311 (not (match_test "optimize_function_for_size_p (cfun)")))
3313 (const_string "V4SF"))
3314 /* For architectures resolving dependencies on
3315 whole SSE registers use APS move to break dependency
3316 chains, otherwise use short move to avoid extra work.
3318 Do the same for architectures resolving dependencies on
3319 the parts. While in DF mode it is better to always handle
3320 just register parts, the SF mode is different due to lack
3321 of instructions to load just part of the register. It is
3322 better to maintain the whole registers in single format
3323 to avoid problems on using packed logical operations. */
3324 (eq_attr "alternative" "6")
3326 (ior (match_test "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
3327 (match_test "TARGET_SSE_SPLIT_REGS"))
3328 (const_string "V4SF")
3329 (const_string "SF"))
3330 (eq_attr "alternative" "11")
3331 (const_string "DI")]
3332 (const_string "SF")))])
3335 [(set (match_operand 0 "any_fp_register_operand" "")
3336 (match_operand 1 "memory_operand" ""))]
3338 && (GET_MODE (operands[0]) == TFmode
3339 || GET_MODE (operands[0]) == XFmode
3340 || GET_MODE (operands[0]) == DFmode
3341 || GET_MODE (operands[0]) == SFmode)
3342 && (operands[2] = find_constant_src (insn))"
3343 [(set (match_dup 0) (match_dup 2))]
3345 rtx c = operands[2];
3346 int r = REGNO (operands[0]);
3348 if ((SSE_REGNO_P (r) && !standard_sse_constant_p (c))
3349 || (FP_REGNO_P (r) && standard_80387_constant_p (c) < 1))
3354 [(set (match_operand 0 "any_fp_register_operand" "")
3355 (float_extend (match_operand 1 "memory_operand" "")))]
3357 && (GET_MODE (operands[0]) == TFmode
3358 || GET_MODE (operands[0]) == XFmode
3359 || GET_MODE (operands[0]) == DFmode)
3360 && (operands[2] = find_constant_src (insn))"
3361 [(set (match_dup 0) (match_dup 2))]
3363 rtx c = operands[2];
3364 int r = REGNO (operands[0]);
3366 if ((SSE_REGNO_P (r) && !standard_sse_constant_p (c))
3367 || (FP_REGNO_P (r) && standard_80387_constant_p (c) < 1))
3371 ;; Split the load of -0.0 or -1.0 into fldz;fchs or fld1;fchs sequence
3373 [(set (match_operand:X87MODEF 0 "fp_register_operand" "")
3374 (match_operand:X87MODEF 1 "immediate_operand" ""))]
3376 && (standard_80387_constant_p (operands[1]) == 8
3377 || standard_80387_constant_p (operands[1]) == 9)"
3378 [(set (match_dup 0)(match_dup 1))
3380 (neg:X87MODEF (match_dup 0)))]
3384 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
3385 if (real_isnegzero (&r))
3386 operands[1] = CONST0_RTX (<MODE>mode);
3388 operands[1] = CONST1_RTX (<MODE>mode);
3392 [(set (match_operand 0 "nonimmediate_operand" "")
3393 (match_operand 1 "general_operand" ""))]
3395 && (GET_MODE (operands[0]) == TFmode
3396 || GET_MODE (operands[0]) == XFmode
3397 || GET_MODE (operands[0]) == DFmode)
3398 && !(ANY_FP_REG_P (operands[0]) || ANY_FP_REG_P (operands[1]))"
3400 "ix86_split_long_move (operands); DONE;")
3402 (define_insn "swapxf"
3403 [(set (match_operand:XF 0 "register_operand" "+f")
3404 (match_operand:XF 1 "register_operand" "+f"))
3409 if (STACK_TOP_P (operands[0]))
3414 [(set_attr "type" "fxch")
3415 (set_attr "mode" "XF")])
3417 (define_insn "*swap<mode>"
3418 [(set (match_operand:MODEF 0 "fp_register_operand" "+f")
3419 (match_operand:MODEF 1 "fp_register_operand" "+f"))
3422 "TARGET_80387 || reload_completed"
3424 if (STACK_TOP_P (operands[0]))
3429 [(set_attr "type" "fxch")
3430 (set_attr "mode" "<MODE>")])
3432 ;; Zero extension instructions
3434 (define_expand "zero_extendsidi2"
3435 [(set (match_operand:DI 0 "nonimmediate_operand" "")
3436 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3441 emit_insn (gen_zero_extendsidi2_1 (operands[0], operands[1]));
3446 (define_insn "*zero_extendsidi2_rex64"
3447 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,?*Ym,?*y,?*Yi,*x")
3449 (match_operand:SI 1 "nonimmediate_operand" "rm,0,r ,m ,r ,m")))]
3452 mov{l}\t{%1, %k0|%k0, %1}
3454 movd\t{%1, %0|%0, %1}
3455 movd\t{%1, %0|%0, %1}
3456 %vmovd\t{%1, %0|%0, %1}
3457 %vmovd\t{%1, %0|%0, %1}"
3458 [(set_attr "type" "imovx,imov,mmxmov,mmxmov,ssemov,ssemov")
3459 (set_attr "prefix" "orig,*,orig,orig,maybe_vex,maybe_vex")
3460 (set_attr "prefix_0f" "0,*,*,*,*,*")
3461 (set_attr "mode" "SI,DI,DI,DI,TI,TI")])
3464 [(set (match_operand:DI 0 "memory_operand" "")
3465 (zero_extend:DI (match_dup 0)))]
3467 [(set (match_dup 4) (const_int 0))]
3468 "split_double_mode (DImode, &operands[0], 1, &operands[3], &operands[4]);")
3470 ;; %%% Kill me once multi-word ops are sane.
3471 (define_insn "zero_extendsidi2_1"
3472 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?o,?*Ym,?*y,?*Yi,*x")
3474 (match_operand:SI 1 "nonimmediate_operand" "0,rm,r ,r ,m ,r ,m")))
3475 (clobber (reg:CC FLAGS_REG))]
3481 movd\t{%1, %0|%0, %1}
3482 movd\t{%1, %0|%0, %1}
3483 %vmovd\t{%1, %0|%0, %1}
3484 %vmovd\t{%1, %0|%0, %1}"
3485 [(set_attr "isa" "*,*,*,*,*,*,sse2")
3486 (set_attr "type" "multi,multi,multi,mmxmov,mmxmov,ssemov,ssemov")
3487 (set_attr "prefix" "*,*,*,orig,orig,maybe_vex,maybe_vex")
3488 (set_attr "mode" "SI,SI,SI,DI,DI,TI,TI")])
3491 [(set (match_operand:DI 0 "register_operand" "")
3492 (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
3493 (clobber (reg:CC FLAGS_REG))]
3494 "!TARGET_64BIT && reload_completed
3495 && true_regnum (operands[0]) == true_regnum (operands[1])"
3496 [(set (match_dup 4) (const_int 0))]
3497 "split_double_mode (DImode, &operands[0], 1, &operands[3], &operands[4]);")
3500 [(set (match_operand:DI 0 "nonimmediate_operand" "")
3501 (zero_extend:DI (match_operand:SI 1 "general_operand" "")))
3502 (clobber (reg:CC FLAGS_REG))]
3503 "!TARGET_64BIT && reload_completed
3504 && !(MMX_REG_P (operands[0]) || SSE_REG_P (operands[0]))"
3505 [(set (match_dup 3) (match_dup 1))
3506 (set (match_dup 4) (const_int 0))]
3507 "split_double_mode (DImode, &operands[0], 1, &operands[3], &operands[4]);")
3509 (define_insn "zero_extend<mode>di2"
3510 [(set (match_operand:DI 0 "register_operand" "=r")
3512 (match_operand:SWI12 1 "nonimmediate_operand" "<r>m")))]
3514 "movz{<imodesuffix>l|x}\t{%1, %k0|%k0, %1}"
3515 [(set_attr "type" "imovx")
3516 (set_attr "mode" "SI")])
3518 (define_expand "zero_extendhisi2"
3519 [(set (match_operand:SI 0 "register_operand" "")
3520 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
3523 if (TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun))
3525 operands[1] = force_reg (HImode, operands[1]);
3526 emit_insn (gen_zero_extendhisi2_and (operands[0], operands[1]));
3531 (define_insn_and_split "zero_extendhisi2_and"
3532 [(set (match_operand:SI 0 "register_operand" "=r")
3533 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
3534 (clobber (reg:CC FLAGS_REG))]
3535 "TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun)"
3537 "&& reload_completed"
3538 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535)))
3539 (clobber (reg:CC FLAGS_REG))])]
3541 [(set_attr "type" "alu1")
3542 (set_attr "mode" "SI")])
3544 (define_insn "*zero_extendhisi2_movzwl"
3545 [(set (match_operand:SI 0 "register_operand" "=r")
3546 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
3547 "!TARGET_ZERO_EXTEND_WITH_AND
3548 || optimize_function_for_size_p (cfun)"
3549 "movz{wl|x}\t{%1, %0|%0, %1}"
3550 [(set_attr "type" "imovx")
3551 (set_attr "mode" "SI")])
3553 (define_expand "zero_extendqi<mode>2"
3555 [(set (match_operand:SWI24 0 "register_operand" "")
3556 (zero_extend:SWI24 (match_operand:QI 1 "nonimmediate_operand" "")))
3557 (clobber (reg:CC FLAGS_REG))])])
3559 (define_insn "*zero_extendqi<mode>2_and"
3560 [(set (match_operand:SWI24 0 "register_operand" "=r,?&q")
3561 (zero_extend:SWI24 (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
3562 (clobber (reg:CC FLAGS_REG))]
3563 "TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun)"
3565 [(set_attr "type" "alu1")
3566 (set_attr "mode" "<MODE>")])
3568 ;; When source and destination does not overlap, clear destination
3569 ;; first and then do the movb
3571 [(set (match_operand:SWI24 0 "register_operand" "")
3572 (zero_extend:SWI24 (match_operand:QI 1 "nonimmediate_operand" "")))
3573 (clobber (reg:CC FLAGS_REG))]
3575 && (TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun))
3576 && ANY_QI_REG_P (operands[0])
3577 && (ANY_QI_REG_P (operands[1]) || MEM_P (operands[1]))
3578 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3579 [(set (strict_low_part (match_dup 2)) (match_dup 1))]
3581 operands[2] = gen_lowpart (QImode, operands[0]);
3582 ix86_expand_clear (operands[0]);
3585 (define_insn "*zero_extendqi<mode>2_movzbl_and"
3586 [(set (match_operand:SWI24 0 "register_operand" "=r,r")
3587 (zero_extend:SWI24 (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
3588 (clobber (reg:CC FLAGS_REG))]
3589 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_function_for_size_p (cfun)"
3591 [(set_attr "type" "imovx,alu1")
3592 (set_attr "mode" "<MODE>")])
3594 ;; For the movzbl case strip only the clobber
3596 [(set (match_operand:SWI24 0 "register_operand" "")
3597 (zero_extend:SWI24 (match_operand:QI 1 "nonimmediate_operand" "")))
3598 (clobber (reg:CC FLAGS_REG))]
3600 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_function_for_size_p (cfun))
3601 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
3603 (zero_extend:SWI24 (match_dup 1)))])
3605 ; zero extend to SImode to avoid partial register stalls
3606 (define_insn "*zero_extendqi<mode>2_movzbl"
3607 [(set (match_operand:SWI24 0 "register_operand" "=r")
3608 (zero_extend:SWI24 (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3610 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_function_for_size_p (cfun))"
3611 "movz{bl|x}\t{%1, %k0|%k0, %1}"
3612 [(set_attr "type" "imovx")
3613 (set_attr "mode" "SI")])
3615 ;; Rest is handled by single and.
3617 [(set (match_operand:SWI24 0 "register_operand" "")
3618 (zero_extend:SWI24 (match_operand:QI 1 "register_operand" "")))
3619 (clobber (reg:CC FLAGS_REG))]
3621 && true_regnum (operands[0]) == true_regnum (operands[1])"
3622 [(parallel [(set (match_dup 0) (and:SWI24 (match_dup 0) (const_int 255)))
3623 (clobber (reg:CC FLAGS_REG))])])
3625 ;; Sign extension instructions
3627 (define_expand "extendsidi2"
3628 [(set (match_operand:DI 0 "register_operand" "")
3629 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))]
3634 emit_insn (gen_extendsidi2_1 (operands[0], operands[1]));
3639 (define_insn "*extendsidi2_rex64"
3640 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3641 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "*0,rm")))]
3645 movs{lq|x}\t{%1, %0|%0, %1}"
3646 [(set_attr "type" "imovx")
3647 (set_attr "mode" "DI")
3648 (set_attr "prefix_0f" "0")
3649 (set_attr "modrm" "0,1")])
3651 (define_insn "extendsidi2_1"
3652 [(set (match_operand:DI 0 "nonimmediate_operand" "=*A,r,?r,?*o")
3653 (sign_extend:DI (match_operand:SI 1 "register_operand" "0,0,r,r")))
3654 (clobber (reg:CC FLAGS_REG))
3655 (clobber (match_scratch:SI 2 "=X,X,X,&r"))]
3659 ;; Extend to memory case when source register does die.
3661 [(set (match_operand:DI 0 "memory_operand" "")
3662 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3663 (clobber (reg:CC FLAGS_REG))
3664 (clobber (match_operand:SI 2 "register_operand" ""))]
3666 && dead_or_set_p (insn, operands[1])
3667 && !reg_mentioned_p (operands[1], operands[0]))"
3668 [(set (match_dup 3) (match_dup 1))
3669 (parallel [(set (match_dup 1) (ashiftrt:SI (match_dup 1) (const_int 31)))
3670 (clobber (reg:CC FLAGS_REG))])
3671 (set (match_dup 4) (match_dup 1))]
3672 "split_double_mode (DImode, &operands[0], 1, &operands[3], &operands[4]);")
3674 ;; Extend to memory case when source register does not die.
3676 [(set (match_operand:DI 0 "memory_operand" "")
3677 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3678 (clobber (reg:CC FLAGS_REG))
3679 (clobber (match_operand:SI 2 "register_operand" ""))]
3683 split_double_mode (DImode, &operands[0], 1, &operands[3], &operands[4]);
3685 emit_move_insn (operands[3], operands[1]);
3687 /* Generate a cltd if possible and doing so it profitable. */
3688 if ((optimize_function_for_size_p (cfun) || TARGET_USE_CLTD)
3689 && true_regnum (operands[1]) == AX_REG
3690 && true_regnum (operands[2]) == DX_REG)
3692 emit_insn (gen_ashrsi3_cvt (operands[2], operands[1], GEN_INT (31)));
3696 emit_move_insn (operands[2], operands[1]);
3697 emit_insn (gen_ashrsi3_cvt (operands[2], operands[2], GEN_INT (31)));
3699 emit_move_insn (operands[4], operands[2]);
3703 ;; Extend to register case. Optimize case where source and destination
3704 ;; registers match and cases where we can use cltd.
3706 [(set (match_operand:DI 0 "register_operand" "")
3707 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3708 (clobber (reg:CC FLAGS_REG))
3709 (clobber (match_scratch:SI 2 ""))]
3713 split_double_mode (DImode, &operands[0], 1, &operands[3], &operands[4]);
3715 if (true_regnum (operands[3]) != true_regnum (operands[1]))
3716 emit_move_insn (operands[3], operands[1]);
3718 /* Generate a cltd if possible and doing so it profitable. */
3719 if ((optimize_function_for_size_p (cfun) || TARGET_USE_CLTD)
3720 && true_regnum (operands[3]) == AX_REG
3721 && true_regnum (operands[4]) == DX_REG)
3723 emit_insn (gen_ashrsi3_cvt (operands[4], operands[3], GEN_INT (31)));
3727 if (true_regnum (operands[4]) != true_regnum (operands[1]))
3728 emit_move_insn (operands[4], operands[1]);
3730 emit_insn (gen_ashrsi3_cvt (operands[4], operands[4], GEN_INT (31)));
3734 (define_insn "extend<mode>di2"
3735 [(set (match_operand:DI 0 "register_operand" "=r")
3737 (match_operand:SWI12 1 "nonimmediate_operand" "<r>m")))]
3739 "movs{<imodesuffix>q|x}\t{%1, %0|%0, %1}"
3740 [(set_attr "type" "imovx")
3741 (set_attr "mode" "DI")])
3743 (define_insn "extendhisi2"
3744 [(set (match_operand:SI 0 "register_operand" "=*a,r")
3745 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm")))]
3748 switch (get_attr_prefix_0f (insn))
3751 return "{cwtl|cwde}";
3753 return "movs{wl|x}\t{%1, %0|%0, %1}";
3756 [(set_attr "type" "imovx")
3757 (set_attr "mode" "SI")
3758 (set (attr "prefix_0f")
3759 ;; movsx is short decodable while cwtl is vector decoded.
3760 (if_then_else (and (eq_attr "cpu" "!k6")
3761 (eq_attr "alternative" "0"))
3763 (const_string "1")))
3765 (if_then_else (eq_attr "prefix_0f" "0")
3767 (const_string "1")))])
3769 (define_insn "*extendhisi2_zext"
3770 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3773 (match_operand:HI 1 "nonimmediate_operand" "*0,rm"))))]
3776 switch (get_attr_prefix_0f (insn))
3779 return "{cwtl|cwde}";
3781 return "movs{wl|x}\t{%1, %k0|%k0, %1}";
3784 [(set_attr "type" "imovx")
3785 (set_attr "mode" "SI")
3786 (set (attr "prefix_0f")
3787 ;; movsx is short decodable while cwtl is vector decoded.
3788 (if_then_else (and (eq_attr "cpu" "!k6")
3789 (eq_attr "alternative" "0"))
3791 (const_string "1")))
3793 (if_then_else (eq_attr "prefix_0f" "0")
3795 (const_string "1")))])
3797 (define_insn "extendqisi2"
3798 [(set (match_operand:SI 0 "register_operand" "=r")
3799 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3801 "movs{bl|x}\t{%1, %0|%0, %1}"
3802 [(set_attr "type" "imovx")
3803 (set_attr "mode" "SI")])
3805 (define_insn "*extendqisi2_zext"
3806 [(set (match_operand:DI 0 "register_operand" "=r")
3808 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm"))))]
3810 "movs{bl|x}\t{%1, %k0|%k0, %1}"
3811 [(set_attr "type" "imovx")
3812 (set_attr "mode" "SI")])
3814 (define_insn "extendqihi2"
3815 [(set (match_operand:HI 0 "register_operand" "=*a,r")
3816 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "*0,qm")))]
3819 switch (get_attr_prefix_0f (insn))
3822 return "{cbtw|cbw}";
3824 return "movs{bw|x}\t{%1, %0|%0, %1}";
3827 [(set_attr "type" "imovx")
3828 (set_attr "mode" "HI")
3829 (set (attr "prefix_0f")
3830 ;; movsx is short decodable while cwtl is vector decoded.
3831 (if_then_else (and (eq_attr "cpu" "!k6")
3832 (eq_attr "alternative" "0"))
3834 (const_string "1")))
3836 (if_then_else (eq_attr "prefix_0f" "0")
3838 (const_string "1")))])
3840 ;; Conversions between float and double.
3842 ;; These are all no-ops in the model used for the 80387.
3843 ;; So just emit moves.
3845 ;; %%% Kill these when call knows how to work out a DFmode push earlier.
3847 [(set (match_operand:DF 0 "push_operand" "")
3848 (float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))]
3850 [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (const_int -8)))
3851 (set (mem:DF (reg:P SP_REG)) (float_extend:DF (match_dup 1)))])
3854 [(set (match_operand:XF 0 "push_operand" "")
3855 (float_extend:XF (match_operand:MODEF 1 "fp_register_operand" "")))]
3857 [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (match_dup 2)))
3858 (set (mem:XF (reg:P SP_REG)) (float_extend:XF (match_dup 1)))]
3859 "operands[2] = GEN_INT (-GET_MODE_SIZE (XFmode));")
3861 (define_expand "extendsfdf2"
3862 [(set (match_operand:DF 0 "nonimmediate_operand" "")
3863 (float_extend:DF (match_operand:SF 1 "general_operand" "")))]
3864 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
3866 /* ??? Needed for compress_float_constant since all fp constants
3867 are TARGET_LEGITIMATE_CONSTANT_P. */
3868 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3870 if ((!TARGET_SSE2 || TARGET_MIX_SSE_I387)
3871 && standard_80387_constant_p (operands[1]) > 0)
3873 operands[1] = simplify_const_unary_operation
3874 (FLOAT_EXTEND, DFmode, operands[1], SFmode);
3875 emit_move_insn_1 (operands[0], operands[1]);
3878 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
3882 /* For converting SF(xmm2) to DF(xmm1), use the following code instead of
3884 unpcklps xmm2,xmm2 ; packed conversion might crash on signaling NaNs
3886 We do the conversion post reload to avoid producing of 128bit spills
3887 that might lead to ICE on 32bit target. The sequence unlikely combine
3890 [(set (match_operand:DF 0 "register_operand" "")
3892 (match_operand:SF 1 "nonimmediate_operand" "")))]
3893 "TARGET_USE_VECTOR_FP_CONVERTS
3894 && optimize_insn_for_speed_p ()
3895 && reload_completed && SSE_REG_P (operands[0])"
3900 (parallel [(const_int 0) (const_int 1)]))))]
3902 operands[2] = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0);
3903 operands[3] = simplify_gen_subreg (V4SFmode, operands[0], DFmode, 0);
3904 /* Use movss for loading from memory, unpcklps reg, reg for registers.
3905 Try to avoid move when unpacking can be done in source. */
3906 if (REG_P (operands[1]))
3908 /* If it is unsafe to overwrite upper half of source, we need
3909 to move to destination and unpack there. */
3910 if ((ORIGINAL_REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
3911 || PSEUDO_REGNO_BYTES (ORIGINAL_REGNO (operands[1])) > 4)
3912 && true_regnum (operands[0]) != true_regnum (operands[1]))
3914 rtx tmp = gen_rtx_REG (SFmode, true_regnum (operands[0]));
3915 emit_move_insn (tmp, operands[1]);
3918 operands[3] = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
3919 emit_insn (gen_vec_interleave_lowv4sf (operands[3], operands[3],
3923 emit_insn (gen_vec_setv4sf_0 (operands[3],
3924 CONST0_RTX (V4SFmode), operands[1]));
3927 (define_insn "*extendsfdf2_mixed"
3928 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,m,x")
3930 (match_operand:SF 1 "nonimmediate_operand" "fm,f,xm")))]
3931 "TARGET_SSE2 && TARGET_MIX_SSE_I387"
3933 switch (which_alternative)
3937 return output_387_reg_move (insn, operands);
3940 return "%vcvtss2sd\t{%1, %d0|%d0, %1}";
3946 [(set_attr "type" "fmov,fmov,ssecvt")
3947 (set_attr "prefix" "orig,orig,maybe_vex")
3948 (set_attr "mode" "SF,XF,DF")])
3950 (define_insn "*extendsfdf2_sse"
3951 [(set (match_operand:DF 0 "nonimmediate_operand" "=x")
3952 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "xm")))]
3953 "TARGET_SSE2 && TARGET_SSE_MATH"
3954 "%vcvtss2sd\t{%1, %d0|%d0, %1}"
3955 [(set_attr "type" "ssecvt")
3956 (set_attr "prefix" "maybe_vex")
3957 (set_attr "mode" "DF")])
3959 (define_insn "*extendsfdf2_i387"
3960 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,m")
3961 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
3963 "* return output_387_reg_move (insn, operands);"
3964 [(set_attr "type" "fmov")
3965 (set_attr "mode" "SF,XF")])
3967 (define_expand "extend<mode>xf2"
3968 [(set (match_operand:XF 0 "nonimmediate_operand" "")
3969 (float_extend:XF (match_operand:MODEF 1 "general_operand" "")))]
3972 /* ??? Needed for compress_float_constant since all fp constants
3973 are TARGET_LEGITIMATE_CONSTANT_P. */
3974 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3976 if (standard_80387_constant_p (operands[1]) > 0)
3978 operands[1] = simplify_const_unary_operation
3979 (FLOAT_EXTEND, XFmode, operands[1], <MODE>mode);
3980 emit_move_insn_1 (operands[0], operands[1]);
3983 operands[1] = validize_mem (force_const_mem (<MODE>mode, operands[1]));
3987 (define_insn "*extend<mode>xf2_i387"
3988 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
3990 (match_operand:MODEF 1 "nonimmediate_operand" "fm,f")))]
3992 "* return output_387_reg_move (insn, operands);"
3993 [(set_attr "type" "fmov")
3994 (set_attr "mode" "<MODE>,XF")])
3996 ;; %%% This seems bad bad news.
3997 ;; This cannot output into an f-reg because there is no way to be sure
3998 ;; of truncating in that case. Otherwise this is just like a simple move
3999 ;; insn. So we pretend we can output to a reg in order to get better
4000 ;; register preferencing, but we really use a stack slot.
4002 ;; Conversion from DFmode to SFmode.
4004 (define_expand "truncdfsf2"
4005 [(set (match_operand:SF 0 "nonimmediate_operand" "")
4007 (match_operand:DF 1 "nonimmediate_operand" "")))]
4008 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
4010 if (TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_MIX_SSE_I387)
4012 else if (flag_unsafe_math_optimizations)
4016 rtx temp = assign_386_stack_local (SFmode, SLOT_TEMP);
4017 emit_insn (gen_truncdfsf2_with_temp (operands[0], operands[1], temp));
4022 /* For converting DF(xmm2) to SF(xmm1), use the following code instead of
4024 unpcklpd xmm2,xmm2 ; packed conversion might crash on signaling NaNs
4026 We do the conversion post reload to avoid producing of 128bit spills
4027 that might lead to ICE on 32bit target. The sequence unlikely combine
4030 [(set (match_operand:SF 0 "register_operand" "")
4032 (match_operand:DF 1 "nonimmediate_operand" "")))]
4033 "TARGET_USE_VECTOR_FP_CONVERTS
4034 && optimize_insn_for_speed_p ()
4035 && reload_completed && SSE_REG_P (operands[0])"
4038 (float_truncate:V2SF
4042 operands[2] = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
4043 operands[3] = CONST0_RTX (V2SFmode);
4044 operands[4] = simplify_gen_subreg (V2DFmode, operands[0], SFmode, 0);
4045 /* Use movsd for loading from memory, unpcklpd for registers.
4046 Try to avoid move when unpacking can be done in source, or SSE3
4047 movddup is available. */
4048 if (REG_P (operands[1]))
4051 && true_regnum (operands[0]) != true_regnum (operands[1])
4052 && (ORIGINAL_REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
4053 || PSEUDO_REGNO_BYTES (ORIGINAL_REGNO (operands[1])) > 8))
4055 rtx tmp = simplify_gen_subreg (DFmode, operands[0], SFmode, 0);
4056 emit_move_insn (tmp, operands[1]);
4059 else if (!TARGET_SSE3)
4060 operands[4] = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0);
4061 emit_insn (gen_vec_dupv2df (operands[4], operands[1]));
4064 emit_insn (gen_sse2_loadlpd (operands[4],
4065 CONST0_RTX (V2DFmode), operands[1]));
4068 (define_expand "truncdfsf2_with_temp"
4069 [(parallel [(set (match_operand:SF 0 "" "")
4070 (float_truncate:SF (match_operand:DF 1 "" "")))
4071 (clobber (match_operand:SF 2 "" ""))])])
4073 (define_insn "*truncdfsf_fast_mixed"
4074 [(set (match_operand:SF 0 "nonimmediate_operand" "=fm,x")
4076 (match_operand:DF 1 "nonimmediate_operand" "f ,xm")))]
4077 "TARGET_SSE2 && TARGET_MIX_SSE_I387 && flag_unsafe_math_optimizations"
4079 switch (which_alternative)
4082 return output_387_reg_move (insn, operands);
4084 return "%vcvtsd2ss\t{%1, %d0|%d0, %1}";
4089 [(set_attr "type" "fmov,ssecvt")
4090 (set_attr "prefix" "orig,maybe_vex")
4091 (set_attr "mode" "SF")])
4093 ;; Yes, this one doesn't depend on flag_unsafe_math_optimizations,
4094 ;; because nothing we do here is unsafe.
4095 (define_insn "*truncdfsf_fast_sse"
4096 [(set (match_operand:SF 0 "nonimmediate_operand" "=x")
4098 (match_operand:DF 1 "nonimmediate_operand" "xm")))]
4099 "TARGET_SSE2 && TARGET_SSE_MATH"
4100 "%vcvtsd2ss\t{%1, %d0|%d0, %1}"
4101 [(set_attr "type" "ssecvt")
4102 (set_attr "prefix" "maybe_vex")
4103 (set_attr "mode" "SF")])
4105 (define_insn "*truncdfsf_fast_i387"
4106 [(set (match_operand:SF 0 "nonimmediate_operand" "=fm")
4108 (match_operand:DF 1 "nonimmediate_operand" "f")))]
4109 "TARGET_80387 && flag_unsafe_math_optimizations"
4110 "* return output_387_reg_move (insn, operands);"
4111 [(set_attr "type" "fmov")
4112 (set_attr "mode" "SF")])
4114 (define_insn "*truncdfsf_mixed"
4115 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,x ,?f,?x,?*r")
4117 (match_operand:DF 1 "nonimmediate_operand" "f ,xm,f ,f ,f")))
4118 (clobber (match_operand:SF 2 "memory_operand" "=X,X ,m ,m ,m"))]
4119 "TARGET_MIX_SSE_I387"
4121 switch (which_alternative)
4124 return output_387_reg_move (insn, operands);
4126 return "%vcvtsd2ss\t{%1, %d0|%d0, %1}";
4132 [(set_attr "isa" "*,sse2,*,*,*")
4133 (set_attr "type" "fmov,ssecvt,multi,multi,multi")
4134 (set_attr "unit" "*,*,i387,i387,i387")
4135 (set_attr "prefix" "orig,maybe_vex,orig,orig,orig")
4136 (set_attr "mode" "SF")])
4138 (define_insn "*truncdfsf_i387"
4139 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f,?x,?*r")
4141 (match_operand:DF 1 "nonimmediate_operand" "f ,f ,f ,f")))
4142 (clobber (match_operand:SF 2 "memory_operand" "=X,m ,m ,m"))]
4145 switch (which_alternative)
4148 return output_387_reg_move (insn, operands);
4154 [(set_attr "type" "fmov,multi,multi,multi")
4155 (set_attr "unit" "*,i387,i387,i387")
4156 (set_attr "mode" "SF")])
4158 (define_insn "*truncdfsf2_i387_1"
4159 [(set (match_operand:SF 0 "memory_operand" "=m")
4161 (match_operand:DF 1 "register_operand" "f")))]
4163 && !(TARGET_SSE2 && TARGET_SSE_MATH)
4164 && !TARGET_MIX_SSE_I387"
4165 "* return output_387_reg_move (insn, operands);"
4166 [(set_attr "type" "fmov")
4167 (set_attr "mode" "SF")])
4170 [(set (match_operand:SF 0 "register_operand" "")
4172 (match_operand:DF 1 "fp_register_operand" "")))
4173 (clobber (match_operand 2 "" ""))]
4175 [(set (match_dup 2) (match_dup 1))
4176 (set (match_dup 0) (match_dup 2))]
4177 "operands[1] = gen_rtx_REG (SFmode, true_regnum (operands[1]));")
4179 ;; Conversion from XFmode to {SF,DF}mode
4181 (define_expand "truncxf<mode>2"
4182 [(parallel [(set (match_operand:MODEF 0 "nonimmediate_operand" "")
4183 (float_truncate:MODEF
4184 (match_operand:XF 1 "register_operand" "")))
4185 (clobber (match_dup 2))])]
4188 if (flag_unsafe_math_optimizations)
4190 rtx reg = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (<MODE>mode);
4191 emit_insn (gen_truncxf<mode>2_i387_noop (reg, operands[1]));
4192 if (reg != operands[0])
4193 emit_move_insn (operands[0], reg);
4197 operands[2] = assign_386_stack_local (<MODE>mode, SLOT_TEMP);
4200 (define_insn "*truncxfsf2_mixed"
4201 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f,?x,?*r")
4203 (match_operand:XF 1 "register_operand" "f ,f ,f ,f")))
4204 (clobber (match_operand:SF 2 "memory_operand" "=X,m ,m ,m"))]
4207 gcc_assert (!which_alternative);
4208 return output_387_reg_move (insn, operands);
4210 [(set_attr "type" "fmov,multi,multi,multi")
4211 (set_attr "unit" "*,i387,i387,i387")
4212 (set_attr "mode" "SF")])
4214 (define_insn "*truncxfdf2_mixed"
4215 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f,?x,?*r")
4217 (match_operand:XF 1 "register_operand" "f ,f ,f ,f")))
4218 (clobber (match_operand:DF 2 "memory_operand" "=X,m ,m ,m"))]
4221 gcc_assert (!which_alternative);
4222 return output_387_reg_move (insn, operands);
4224 [(set_attr "isa" "*,*,sse2,*")
4225 (set_attr "type" "fmov,multi,multi,multi")
4226 (set_attr "unit" "*,i387,i387,i387")
4227 (set_attr "mode" "DF")])
4229 (define_insn "truncxf<mode>2_i387_noop"
4230 [(set (match_operand:MODEF 0 "register_operand" "=f")
4231 (float_truncate:MODEF
4232 (match_operand:XF 1 "register_operand" "f")))]
4233 "TARGET_80387 && flag_unsafe_math_optimizations"
4234 "* return output_387_reg_move (insn, operands);"
4235 [(set_attr "type" "fmov")
4236 (set_attr "mode" "<MODE>")])
4238 (define_insn "*truncxf<mode>2_i387"
4239 [(set (match_operand:MODEF 0 "memory_operand" "=m")
4240 (float_truncate:MODEF
4241 (match_operand:XF 1 "register_operand" "f")))]
4243 "* return output_387_reg_move (insn, operands);"
4244 [(set_attr "type" "fmov")
4245 (set_attr "mode" "<MODE>")])
4248 [(set (match_operand:MODEF 0 "register_operand" "")
4249 (float_truncate:MODEF
4250 (match_operand:XF 1 "register_operand" "")))
4251 (clobber (match_operand:MODEF 2 "memory_operand" ""))]
4252 "TARGET_80387 && reload_completed"
4253 [(set (match_dup 2) (float_truncate:MODEF (match_dup 1)))
4254 (set (match_dup 0) (match_dup 2))])
4257 [(set (match_operand:MODEF 0 "memory_operand" "")
4258 (float_truncate:MODEF
4259 (match_operand:XF 1 "register_operand" "")))
4260 (clobber (match_operand:MODEF 2 "memory_operand" ""))]
4262 [(set (match_dup 0) (float_truncate:MODEF (match_dup 1)))])
4264 ;; Signed conversion to DImode.
4266 (define_expand "fix_truncxfdi2"
4267 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
4268 (fix:DI (match_operand:XF 1 "register_operand" "")))
4269 (clobber (reg:CC FLAGS_REG))])]
4274 emit_insn (gen_fix_truncdi_fisttp_i387_1 (operands[0], operands[1]));
4279 (define_expand "fix_trunc<mode>di2"
4280 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
4281 (fix:DI (match_operand:MODEF 1 "register_operand" "")))
4282 (clobber (reg:CC FLAGS_REG))])]
4283 "TARGET_80387 || (TARGET_64BIT && SSE_FLOAT_MODE_P (<MODE>mode))"
4286 && !(TARGET_64BIT && SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH))
4288 emit_insn (gen_fix_truncdi_fisttp_i387_1 (operands[0], operands[1]));
4291 if (TARGET_64BIT && SSE_FLOAT_MODE_P (<MODE>mode))
4293 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
4294 emit_insn (gen_fix_trunc<mode>di_sse (out, operands[1]));
4295 if (out != operands[0])
4296 emit_move_insn (operands[0], out);
4301 ;; Signed conversion to SImode.
4303 (define_expand "fix_truncxfsi2"
4304 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4305 (fix:SI (match_operand:XF 1 "register_operand" "")))
4306 (clobber (reg:CC FLAGS_REG))])]
4311 emit_insn (gen_fix_truncsi_fisttp_i387_1 (operands[0], operands[1]));
4316 (define_expand "fix_trunc<mode>si2"
4317 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4318 (fix:SI (match_operand:MODEF 1 "register_operand" "")))
4319 (clobber (reg:CC FLAGS_REG))])]
4320 "TARGET_80387 || SSE_FLOAT_MODE_P (<MODE>mode)"
4323 && !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH))
4325 emit_insn (gen_fix_truncsi_fisttp_i387_1 (operands[0], operands[1]));
4328 if (SSE_FLOAT_MODE_P (<MODE>mode))
4330 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4331 emit_insn (gen_fix_trunc<mode>si_sse (out, operands[1]));
4332 if (out != operands[0])
4333 emit_move_insn (operands[0], out);
4338 ;; Signed conversion to HImode.
4340 (define_expand "fix_trunc<mode>hi2"
4341 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
4342 (fix:HI (match_operand:X87MODEF 1 "register_operand" "")))
4343 (clobber (reg:CC FLAGS_REG))])]
4345 && !(SSE_FLOAT_MODE_P (<MODE>mode) && (!TARGET_FISTTP || TARGET_SSE_MATH))"
4349 emit_insn (gen_fix_trunchi_fisttp_i387_1 (operands[0], operands[1]));
4354 ;; Unsigned conversion to SImode.
4356 (define_expand "fixuns_trunc<mode>si2"
4358 [(set (match_operand:SI 0 "register_operand" "")
4360 (match_operand:MODEF 1 "nonimmediate_operand" "")))
4362 (clobber (match_scratch:<ssevecmode> 3 ""))
4363 (clobber (match_scratch:<ssevecmode> 4 ""))])]
4364 "!TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH"
4366 enum machine_mode mode = <MODE>mode;
4367 enum machine_mode vecmode = <ssevecmode>mode;
4368 REAL_VALUE_TYPE TWO31r;
4371 if (optimize_insn_for_size_p ())
4374 real_ldexp (&TWO31r, &dconst1, 31);
4375 two31 = const_double_from_real_value (TWO31r, mode);
4376 two31 = ix86_build_const_vector (vecmode, true, two31);
4377 operands[2] = force_reg (vecmode, two31);
4380 (define_insn_and_split "*fixuns_trunc<mode>_1"
4381 [(set (match_operand:SI 0 "register_operand" "=&x,&x")
4383 (match_operand:MODEF 3 "nonimmediate_operand" "xm,xm")))
4384 (use (match_operand:<ssevecmode> 4 "nonimmediate_operand" "m,x"))
4385 (clobber (match_scratch:<ssevecmode> 1 "=x,&x"))
4386 (clobber (match_scratch:<ssevecmode> 2 "=x,x"))]
4387 "!TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH
4388 && optimize_function_for_speed_p (cfun)"
4390 "&& reload_completed"
4393 ix86_split_convert_uns_si_sse (operands);
4397 ;; Unsigned conversion to HImode.
4398 ;; Without these patterns, we'll try the unsigned SI conversion which
4399 ;; is complex for SSE, rather than the signed SI conversion, which isn't.
4401 (define_expand "fixuns_trunc<mode>hi2"
4403 (fix:SI (match_operand:MODEF 1 "nonimmediate_operand" "")))
4404 (set (match_operand:HI 0 "nonimmediate_operand" "")
4405 (subreg:HI (match_dup 2) 0))]
4406 "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
4407 "operands[2] = gen_reg_rtx (SImode);")
4409 ;; When SSE is available, it is always faster to use it!
4410 (define_insn "fix_trunc<mode>di_sse"
4411 [(set (match_operand:DI 0 "register_operand" "=r,r")
4412 (fix:DI (match_operand:MODEF 1 "nonimmediate_operand" "x,m")))]
4413 "TARGET_64BIT && SSE_FLOAT_MODE_P (<MODE>mode)
4414 && (!TARGET_FISTTP || TARGET_SSE_MATH)"
4415 "%vcvtt<ssemodesuffix>2si{q}\t{%1, %0|%0, %1}"
4416 [(set_attr "type" "sseicvt")
4417 (set_attr "prefix" "maybe_vex")
4418 (set_attr "prefix_rex" "1")
4419 (set_attr "mode" "<MODE>")
4420 (set_attr "athlon_decode" "double,vector")
4421 (set_attr "amdfam10_decode" "double,double")
4422 (set_attr "bdver1_decode" "double,double")])
4424 (define_insn "fix_trunc<mode>si_sse"
4425 [(set (match_operand:SI 0 "register_operand" "=r,r")
4426 (fix:SI (match_operand:MODEF 1 "nonimmediate_operand" "x,m")))]
4427 "SSE_FLOAT_MODE_P (<MODE>mode)
4428 && (!TARGET_FISTTP || TARGET_SSE_MATH)"
4429 "%vcvtt<ssemodesuffix>2si\t{%1, %0|%0, %1}"
4430 [(set_attr "type" "sseicvt")
4431 (set_attr "prefix" "maybe_vex")
4432 (set_attr "mode" "<MODE>")
4433 (set_attr "athlon_decode" "double,vector")
4434 (set_attr "amdfam10_decode" "double,double")
4435 (set_attr "bdver1_decode" "double,double")])
4437 ;; Shorten x87->SSE reload sequences of fix_trunc?f?i_sse patterns.
4439 [(set (match_operand:MODEF 0 "register_operand" "")
4440 (match_operand:MODEF 1 "memory_operand" ""))
4441 (set (match_operand:SWI48x 2 "register_operand" "")
4442 (fix:SWI48x (match_dup 0)))]
4443 "TARGET_SHORTEN_X87_SSE
4444 && !(TARGET_AVOID_VECTOR_DECODE && optimize_insn_for_speed_p ())
4445 && peep2_reg_dead_p (2, operands[0])"
4446 [(set (match_dup 2) (fix:SWI48x (match_dup 1)))])
4448 ;; Avoid vector decoded forms of the instruction.
4450 [(match_scratch:DF 2 "x")
4451 (set (match_operand:SWI48x 0 "register_operand" "")
4452 (fix:SWI48x (match_operand:DF 1 "memory_operand" "")))]
4453 "TARGET_SSE2 && TARGET_AVOID_VECTOR_DECODE && optimize_insn_for_speed_p ()"
4454 [(set (match_dup 2) (match_dup 1))
4455 (set (match_dup 0) (fix:SWI48x (match_dup 2)))])
4458 [(match_scratch:SF 2 "x")
4459 (set (match_operand:SWI48x 0 "register_operand" "")
4460 (fix:SWI48x (match_operand:SF 1 "memory_operand" "")))]
4461 "TARGET_AVOID_VECTOR_DECODE && optimize_insn_for_speed_p ()"
4462 [(set (match_dup 2) (match_dup 1))
4463 (set (match_dup 0) (fix:SWI48x (match_dup 2)))])
4465 (define_insn_and_split "fix_trunc<mode>_fisttp_i387_1"
4466 [(set (match_operand:SWI248x 0 "nonimmediate_operand" "")
4467 (fix:SWI248x (match_operand 1 "register_operand" "")))]
4468 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
4470 && !((SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
4471 && (TARGET_64BIT || <MODE>mode != DImode))
4473 && can_create_pseudo_p ()"
4478 if (memory_operand (operands[0], VOIDmode))
4479 emit_insn (gen_fix_trunc<mode>_i387_fisttp (operands[0], operands[1]));
4482 operands[2] = assign_386_stack_local (<MODE>mode, SLOT_TEMP);
4483 emit_insn (gen_fix_trunc<mode>_i387_fisttp_with_temp (operands[0],
4489 [(set_attr "type" "fisttp")
4490 (set_attr "mode" "<MODE>")])
4492 (define_insn "fix_trunc<mode>_i387_fisttp"
4493 [(set (match_operand:SWI248x 0 "memory_operand" "=m")
4494 (fix:SWI248x (match_operand 1 "register_operand" "f")))
4495 (clobber (match_scratch:XF 2 "=&1f"))]
4496 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
4498 && !((SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
4499 && (TARGET_64BIT || <MODE>mode != DImode))
4500 && TARGET_SSE_MATH)"
4501 "* return output_fix_trunc (insn, operands, true);"
4502 [(set_attr "type" "fisttp")
4503 (set_attr "mode" "<MODE>")])
4505 (define_insn "fix_trunc<mode>_i387_fisttp_with_temp"
4506 [(set (match_operand:SWI248x 0 "nonimmediate_operand" "=m,?r")
4507 (fix:SWI248x (match_operand 1 "register_operand" "f,f")))
4508 (clobber (match_operand:SWI248x 2 "memory_operand" "=X,m"))
4509 (clobber (match_scratch:XF 3 "=&1f,&1f"))]
4510 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
4512 && !((SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
4513 && (TARGET_64BIT || <MODE>mode != DImode))
4514 && TARGET_SSE_MATH)"
4516 [(set_attr "type" "fisttp")
4517 (set_attr "mode" "<MODE>")])
4520 [(set (match_operand:SWI248x 0 "register_operand" "")
4521 (fix:SWI248x (match_operand 1 "register_operand" "")))
4522 (clobber (match_operand:SWI248x 2 "memory_operand" ""))
4523 (clobber (match_scratch 3 ""))]
4525 [(parallel [(set (match_dup 2) (fix:SWI248x (match_dup 1)))
4526 (clobber (match_dup 3))])
4527 (set (match_dup 0) (match_dup 2))])
4530 [(set (match_operand:SWI248x 0 "memory_operand" "")
4531 (fix:SWI248x (match_operand 1 "register_operand" "")))
4532 (clobber (match_operand:SWI248x 2 "memory_operand" ""))
4533 (clobber (match_scratch 3 ""))]
4535 [(parallel [(set (match_dup 0) (fix:SWI248x (match_dup 1)))
4536 (clobber (match_dup 3))])])
4538 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4539 ;; of the machinery. Please note the clobber of FLAGS_REG. In i387 control
4540 ;; word calculation (inserted by LCM in mode switching pass) a FLAGS_REG
4541 ;; clobbering insns can be used. Look at emit_i387_cw_initialization ()
4542 ;; function in i386.c.
4543 (define_insn_and_split "*fix_trunc<mode>_i387_1"
4544 [(set (match_operand:SWI248x 0 "nonimmediate_operand" "")
4545 (fix:SWI248x (match_operand 1 "register_operand" "")))
4546 (clobber (reg:CC FLAGS_REG))]
4547 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
4549 && !(SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
4550 && (TARGET_64BIT || <MODE>mode != DImode))
4551 && can_create_pseudo_p ()"
4556 ix86_optimize_mode_switching[I387_TRUNC] = 1;
4558 operands[2] = assign_386_stack_local (HImode, SLOT_CW_STORED);
4559 operands[3] = assign_386_stack_local (HImode, SLOT_CW_TRUNC);
4560 if (memory_operand (operands[0], VOIDmode))
4561 emit_insn (gen_fix_trunc<mode>_i387 (operands[0], operands[1],
4562 operands[2], operands[3]));
4565 operands[4] = assign_386_stack_local (<MODE>mode, SLOT_TEMP);
4566 emit_insn (gen_fix_trunc<mode>_i387_with_temp (operands[0], operands[1],
4567 operands[2], operands[3],
4572 [(set_attr "type" "fistp")
4573 (set_attr "i387_cw" "trunc")
4574 (set_attr "mode" "<MODE>")])
4576 (define_insn "fix_truncdi_i387"
4577 [(set (match_operand:DI 0 "memory_operand" "=m")
4578 (fix:DI (match_operand 1 "register_operand" "f")))
4579 (use (match_operand:HI 2 "memory_operand" "m"))
4580 (use (match_operand:HI 3 "memory_operand" "m"))
4581 (clobber (match_scratch:XF 4 "=&1f"))]
4582 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
4584 && !(TARGET_64BIT && SSE_FLOAT_MODE_P (GET_MODE (operands[1])))"
4585 "* return output_fix_trunc (insn, operands, false);"
4586 [(set_attr "type" "fistp")
4587 (set_attr "i387_cw" "trunc")
4588 (set_attr "mode" "DI")])
4590 (define_insn "fix_truncdi_i387_with_temp"
4591 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
4592 (fix:DI (match_operand 1 "register_operand" "f,f")))
4593 (use (match_operand:HI 2 "memory_operand" "m,m"))
4594 (use (match_operand:HI 3 "memory_operand" "m,m"))
4595 (clobber (match_operand:DI 4 "memory_operand" "=X,m"))
4596 (clobber (match_scratch:XF 5 "=&1f,&1f"))]
4597 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
4599 && !(TARGET_64BIT && SSE_FLOAT_MODE_P (GET_MODE (operands[1])))"
4601 [(set_attr "type" "fistp")
4602 (set_attr "i387_cw" "trunc")
4603 (set_attr "mode" "DI")])
4606 [(set (match_operand:DI 0 "register_operand" "")
4607 (fix:DI (match_operand 1 "register_operand" "")))
4608 (use (match_operand:HI 2 "memory_operand" ""))
4609 (use (match_operand:HI 3 "memory_operand" ""))
4610 (clobber (match_operand:DI 4 "memory_operand" ""))
4611 (clobber (match_scratch 5 ""))]
4613 [(parallel [(set (match_dup 4) (fix:DI (match_dup 1)))
4616 (clobber (match_dup 5))])
4617 (set (match_dup 0) (match_dup 4))])
4620 [(set (match_operand:DI 0 "memory_operand" "")
4621 (fix:DI (match_operand 1 "register_operand" "")))
4622 (use (match_operand:HI 2 "memory_operand" ""))
4623 (use (match_operand:HI 3 "memory_operand" ""))
4624 (clobber (match_operand:DI 4 "memory_operand" ""))
4625 (clobber (match_scratch 5 ""))]
4627 [(parallel [(set (match_dup 0) (fix:DI (match_dup 1)))
4630 (clobber (match_dup 5))])])
4632 (define_insn "fix_trunc<mode>_i387"
4633 [(set (match_operand:SWI24 0 "memory_operand" "=m")
4634 (fix:SWI24 (match_operand 1 "register_operand" "f")))
4635 (use (match_operand:HI 2 "memory_operand" "m"))
4636 (use (match_operand:HI 3 "memory_operand" "m"))]
4637 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
4639 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4640 "* return output_fix_trunc (insn, operands, false);"
4641 [(set_attr "type" "fistp")
4642 (set_attr "i387_cw" "trunc")
4643 (set_attr "mode" "<MODE>")])
4645 (define_insn "fix_trunc<mode>_i387_with_temp"
4646 [(set (match_operand:SWI24 0 "nonimmediate_operand" "=m,?r")
4647 (fix:SWI24 (match_operand 1 "register_operand" "f,f")))
4648 (use (match_operand:HI 2 "memory_operand" "m,m"))
4649 (use (match_operand:HI 3 "memory_operand" "m,m"))
4650 (clobber (match_operand:SWI24 4 "memory_operand" "=X,m"))]
4651 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
4653 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4655 [(set_attr "type" "fistp")
4656 (set_attr "i387_cw" "trunc")
4657 (set_attr "mode" "<MODE>")])
4660 [(set (match_operand:SWI24 0 "register_operand" "")
4661 (fix:SWI24 (match_operand 1 "register_operand" "")))
4662 (use (match_operand:HI 2 "memory_operand" ""))
4663 (use (match_operand:HI 3 "memory_operand" ""))
4664 (clobber (match_operand:SWI24 4 "memory_operand" ""))]
4666 [(parallel [(set (match_dup 4) (fix:SWI24 (match_dup 1)))
4668 (use (match_dup 3))])
4669 (set (match_dup 0) (match_dup 4))])
4672 [(set (match_operand:SWI24 0 "memory_operand" "")
4673 (fix:SWI24 (match_operand 1 "register_operand" "")))
4674 (use (match_operand:HI 2 "memory_operand" ""))
4675 (use (match_operand:HI 3 "memory_operand" ""))
4676 (clobber (match_operand:SWI24 4 "memory_operand" ""))]
4678 [(parallel [(set (match_dup 0) (fix:SWI24 (match_dup 1)))
4680 (use (match_dup 3))])])
4682 (define_insn "x86_fnstcw_1"
4683 [(set (match_operand:HI 0 "memory_operand" "=m")
4684 (unspec:HI [(reg:HI FPCR_REG)] UNSPEC_FSTCW))]
4687 [(set (attr "length")
4688 (symbol_ref "ix86_attr_length_address_default (insn) + 2"))
4689 (set_attr "mode" "HI")
4690 (set_attr "unit" "i387")
4691 (set_attr "bdver1_decode" "vector")])
4693 (define_insn "x86_fldcw_1"
4694 [(set (reg:HI FPCR_REG)
4695 (unspec:HI [(match_operand:HI 0 "memory_operand" "m")] UNSPEC_FLDCW))]
4698 [(set (attr "length")
4699 (symbol_ref "ix86_attr_length_address_default (insn) + 2"))
4700 (set_attr "mode" "HI")
4701 (set_attr "unit" "i387")
4702 (set_attr "athlon_decode" "vector")
4703 (set_attr "amdfam10_decode" "vector")
4704 (set_attr "bdver1_decode" "vector")])
4706 ;; Conversion between fixed point and floating point.
4708 ;; Even though we only accept memory inputs, the backend _really_
4709 ;; wants to be able to do this between registers.
4711 (define_expand "floathi<mode>2"
4712 [(set (match_operand:X87MODEF 0 "register_operand" "")
4713 (float:X87MODEF (match_operand:HI 1 "nonimmediate_operand" "")))]
4715 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
4716 || TARGET_MIX_SSE_I387)")
4718 ;; Pre-reload splitter to add memory clobber to the pattern.
4719 (define_insn_and_split "*floathi<mode>2_1"
4720 [(set (match_operand:X87MODEF 0 "register_operand" "")
4721 (float:X87MODEF (match_operand:HI 1 "register_operand" "")))]
4723 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
4724 || TARGET_MIX_SSE_I387)
4725 && can_create_pseudo_p ()"
4728 [(parallel [(set (match_dup 0)
4729 (float:X87MODEF (match_dup 1)))
4730 (clobber (match_dup 2))])]
4731 "operands[2] = assign_386_stack_local (HImode, SLOT_TEMP);")
4733 (define_insn "*floathi<mode>2_i387_with_temp"
4734 [(set (match_operand:X87MODEF 0 "register_operand" "=f,f")
4735 (float:X87MODEF (match_operand:HI 1 "nonimmediate_operand" "m,?r")))
4736 (clobber (match_operand:HI 2 "memory_operand" "=X,m"))]
4738 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
4739 || TARGET_MIX_SSE_I387)"
4741 [(set_attr "type" "fmov,multi")
4742 (set_attr "mode" "<MODE>")
4743 (set_attr "unit" "*,i387")
4744 (set_attr "fp_int_src" "true")])
4746 (define_insn "*floathi<mode>2_i387"
4747 [(set (match_operand:X87MODEF 0 "register_operand" "=f")
4748 (float:X87MODEF (match_operand:HI 1 "memory_operand" "m")))]
4750 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
4751 || TARGET_MIX_SSE_I387)"
4753 [(set_attr "type" "fmov")
4754 (set_attr "mode" "<MODE>")
4755 (set_attr "fp_int_src" "true")])
4758 [(set (match_operand:X87MODEF 0 "register_operand" "")
4759 (float:X87MODEF (match_operand:HI 1 "register_operand" "")))
4760 (clobber (match_operand:HI 2 "memory_operand" ""))]
4762 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
4763 || TARGET_MIX_SSE_I387)
4764 && reload_completed"
4765 [(set (match_dup 2) (match_dup 1))
4766 (set (match_dup 0) (float:X87MODEF (match_dup 2)))])
4769 [(set (match_operand:X87MODEF 0 "register_operand" "")
4770 (float:X87MODEF (match_operand:HI 1 "memory_operand" "")))
4771 (clobber (match_operand:HI 2 "memory_operand" ""))]
4773 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
4774 || TARGET_MIX_SSE_I387)
4775 && reload_completed"
4776 [(set (match_dup 0) (float:X87MODEF (match_dup 1)))])
4778 (define_expand "float<SWI48x:mode><X87MODEF:mode>2"
4779 [(set (match_operand:X87MODEF 0 "register_operand" "")
4781 (match_operand:SWI48x 1 "nonimmediate_operand" "")))]
4783 || ((<SWI48x:MODE>mode != DImode || TARGET_64BIT)
4784 && SSE_FLOAT_MODE_P (<X87MODEF:MODE>mode) && TARGET_SSE_MATH)"
4786 if (!((<SWI48x:MODE>mode != DImode || TARGET_64BIT)
4787 && SSE_FLOAT_MODE_P (<X87MODEF:MODE>mode) && TARGET_SSE_MATH)
4788 && !X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SWI48x:MODE>mode))
4790 rtx reg = gen_reg_rtx (XFmode);
4791 rtx (*insn)(rtx, rtx);
4793 emit_insn (gen_float<SWI48x:mode>xf2 (reg, operands[1]));
4795 if (<X87MODEF:MODE>mode == SFmode)
4796 insn = gen_truncxfsf2;
4797 else if (<X87MODEF:MODE>mode == DFmode)
4798 insn = gen_truncxfdf2;
4802 emit_insn (insn (operands[0], reg));
4807 ;; Pre-reload splitter to add memory clobber to the pattern.
4808 (define_insn_and_split "*float<SWI48x:mode><X87MODEF:mode>2_1"
4809 [(set (match_operand:X87MODEF 0 "register_operand" "")
4810 (float:X87MODEF (match_operand:SWI48x 1 "register_operand" "")))]
4812 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SWI48x:MODE>mode)
4813 && (!((<SWI48x:MODE>mode != DImode || TARGET_64BIT)
4814 && SSE_FLOAT_MODE_P (<X87MODEF:MODE>mode) && TARGET_SSE_MATH)
4815 || TARGET_MIX_SSE_I387))
4816 || ((<SWI48x:MODE>mode != DImode || TARGET_64BIT)
4817 && SSE_FLOAT_MODE_P (<X87MODEF:MODE>mode) && TARGET_SSE_MATH
4818 && ((<SWI48x:MODE>mode == SImode
4819 && TARGET_SSE2 && TARGET_USE_VECTOR_CONVERTS
4820 && optimize_function_for_speed_p (cfun)
4821 && flag_trapping_math)
4822 || !(TARGET_INTER_UNIT_CONVERSIONS
4823 || optimize_function_for_size_p (cfun)))))
4824 && can_create_pseudo_p ()"
4827 [(parallel [(set (match_dup 0) (float:X87MODEF (match_dup 1)))
4828 (clobber (match_dup 2))])]
4830 operands[2] = assign_386_stack_local (<SWI48x:MODE>mode, SLOT_TEMP);
4832 /* Avoid store forwarding (partial memory) stall penalty
4833 by passing DImode value through XMM registers. */
4834 if (<SWI48x:MODE>mode == DImode && !TARGET_64BIT
4835 && TARGET_80387 && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES
4836 && optimize_function_for_speed_p (cfun))
4838 emit_insn (gen_floatdi<X87MODEF:mode>2_i387_with_xmm (operands[0],
4845 (define_insn "*floatsi<mode>2_vector_mixed_with_temp"
4846 [(set (match_operand:MODEF 0 "register_operand" "=f,f,x,x,x")
4848 (match_operand:SI 1 "nonimmediate_operand" "m,?r,r,m,!x")))
4849 (clobber (match_operand:SI 2 "memory_operand" "=X,m,m,X,m"))]
4850 "TARGET_SSE2 && TARGET_MIX_SSE_I387
4851 && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)"
4853 [(set_attr "type" "fmov,multi,sseicvt,sseicvt,sseicvt")
4854 (set_attr "mode" "<MODE>,<MODE>,<MODE>,<MODE>,<ssevecmode>")
4855 (set_attr "unit" "*,i387,*,*,*")
4856 (set_attr "athlon_decode" "*,*,double,direct,double")
4857 (set_attr "amdfam10_decode" "*,*,vector,double,double")
4858 (set_attr "bdver1_decode" "*,*,double,direct,double")
4859 (set_attr "fp_int_src" "true")])
4861 (define_insn "*floatsi<mode>2_vector_mixed"
4862 [(set (match_operand:MODEF 0 "register_operand" "=f,x")
4863 (float:MODEF (match_operand:SI 1 "memory_operand" "m,m")))]
4864 "TARGET_SSE2 && TARGET_MIX_SSE_I387
4865 && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)"
4869 [(set_attr "type" "fmov,sseicvt")
4870 (set_attr "mode" "<MODE>,<ssevecmode>")
4871 (set_attr "unit" "i387,*")
4872 (set_attr "athlon_decode" "*,direct")
4873 (set_attr "amdfam10_decode" "*,double")
4874 (set_attr "bdver1_decode" "*,direct")
4875 (set_attr "fp_int_src" "true")])
4877 (define_insn "*float<SWI48x:mode><MODEF:mode>2_mixed_with_temp"
4878 [(set (match_operand:MODEF 0 "register_operand" "=f,f,x,x")
4880 (match_operand:SWI48x 1 "nonimmediate_operand" "m,?r,r,m")))
4881 (clobber (match_operand:SWI48x 2 "memory_operand" "=X,m,m,X"))]
4882 "(<SWI48x:MODE>mode != DImode || TARGET_64BIT)
4883 && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387"
4885 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
4886 (set_attr "mode" "<MODEF:MODE>")
4887 (set_attr "unit" "*,i387,*,*")
4888 (set_attr "athlon_decode" "*,*,double,direct")
4889 (set_attr "amdfam10_decode" "*,*,vector,double")
4890 (set_attr "bdver1_decode" "*,*,double,direct")
4891 (set_attr "fp_int_src" "true")])
4894 [(set (match_operand:MODEF 0 "register_operand" "")
4895 (float:MODEF (match_operand:SWI48x 1 "register_operand" "")))
4896 (clobber (match_operand:SWI48x 2 "memory_operand" ""))]
4897 "(<SWI48x:MODE>mode != DImode || TARGET_64BIT)
4898 && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387
4899 && TARGET_INTER_UNIT_CONVERSIONS
4901 && (SSE_REG_P (operands[0])
4902 || (GET_CODE (operands[0]) == SUBREG
4903 && SSE_REG_P (SUBREG_REG (operands[0]))))"
4904 [(set (match_dup 0) (float:MODEF (match_dup 1)))])
4907 [(set (match_operand:MODEF 0 "register_operand" "")
4908 (float:MODEF (match_operand:SWI48x 1 "register_operand" "")))
4909 (clobber (match_operand:SWI48x 2 "memory_operand" ""))]
4910 "(<SWI48x:MODE>mode != DImode || TARGET_64BIT)
4911 && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387
4912 && !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))
4914 && (SSE_REG_P (operands[0])
4915 || (GET_CODE (operands[0]) == SUBREG
4916 && SSE_REG_P (SUBREG_REG (operands[0]))))"
4917 [(set (match_dup 2) (match_dup 1))
4918 (set (match_dup 0) (float:MODEF (match_dup 2)))])
4920 (define_insn "*float<SWI48x:mode><MODEF:mode>2_mixed_interunit"
4921 [(set (match_operand:MODEF 0 "register_operand" "=f,x,x")
4923 (match_operand:SWI48x 1 "nonimmediate_operand" "m,r,m")))]
4924 "(<SWI48x:MODE>mode != DImode || TARGET_64BIT)
4925 && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387
4926 && (TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))"
4929 %vcvtsi2<MODEF:ssemodesuffix><SWI48x:rex64suffix>\t{%1, %d0|%d0, %1}
4930 %vcvtsi2<MODEF:ssemodesuffix><SWI48x:rex64suffix>\t{%1, %d0|%d0, %1}"
4931 [(set_attr "type" "fmov,sseicvt,sseicvt")
4932 (set_attr "prefix" "orig,maybe_vex,maybe_vex")
4933 (set_attr "mode" "<MODEF:MODE>")
4934 (set (attr "prefix_rex")
4936 (and (eq_attr "prefix" "maybe_vex")
4937 (match_test "<SWI48x:MODE>mode == DImode"))
4939 (const_string "*")))
4940 (set_attr "unit" "i387,*,*")
4941 (set_attr "athlon_decode" "*,double,direct")
4942 (set_attr "amdfam10_decode" "*,vector,double")
4943 (set_attr "bdver1_decode" "*,double,direct")
4944 (set_attr "fp_int_src" "true")])
4946 (define_insn "*float<SWI48x:mode><MODEF:mode>2_mixed_nointerunit"
4947 [(set (match_operand:MODEF 0 "register_operand" "=f,x")
4949 (match_operand:SWI48x 1 "memory_operand" "m,m")))]
4950 "(<SWI48x:MODE>mode != DImode || TARGET_64BIT)
4951 && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387
4952 && !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))"
4955 %vcvtsi2<MODEF:ssemodesuffix><SWI48x:rex64suffix>\t{%1, %d0|%d0, %1}"
4956 [(set_attr "type" "fmov,sseicvt")
4957 (set_attr "prefix" "orig,maybe_vex")
4958 (set_attr "mode" "<MODEF:MODE>")
4959 (set (attr "prefix_rex")
4961 (and (eq_attr "prefix" "maybe_vex")
4962 (match_test "<SWI48x:MODE>mode == DImode"))
4964 (const_string "*")))
4965 (set_attr "athlon_decode" "*,direct")
4966 (set_attr "amdfam10_decode" "*,double")
4967 (set_attr "bdver1_decode" "*,direct")
4968 (set_attr "fp_int_src" "true")])
4970 (define_insn "*floatsi<mode>2_vector_sse_with_temp"
4971 [(set (match_operand:MODEF 0 "register_operand" "=x,x,x")
4973 (match_operand:SI 1 "nonimmediate_operand" "r,m,!x")))
4974 (clobber (match_operand:SI 2 "memory_operand" "=m,X,m"))]
4975 "TARGET_SSE2 && TARGET_SSE_MATH
4976 && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)"
4978 [(set_attr "type" "sseicvt")
4979 (set_attr "mode" "<MODE>,<MODE>,<ssevecmode>")
4980 (set_attr "athlon_decode" "double,direct,double")
4981 (set_attr "amdfam10_decode" "vector,double,double")
4982 (set_attr "bdver1_decode" "double,direct,double")
4983 (set_attr "fp_int_src" "true")])
4985 (define_insn "*floatsi<mode>2_vector_sse"
4986 [(set (match_operand:MODEF 0 "register_operand" "=x")
4987 (float:MODEF (match_operand:SI 1 "memory_operand" "m")))]
4988 "TARGET_SSE2 && TARGET_SSE_MATH
4989 && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)"
4991 [(set_attr "type" "sseicvt")
4992 (set_attr "mode" "<MODE>")
4993 (set_attr "athlon_decode" "direct")
4994 (set_attr "amdfam10_decode" "double")
4995 (set_attr "bdver1_decode" "direct")
4996 (set_attr "fp_int_src" "true")])
4999 [(set (match_operand:MODEF 0 "register_operand" "")
5000 (float:MODEF (match_operand:SI 1 "register_operand" "")))
5001 (clobber (match_operand:SI 2 "memory_operand" ""))]
5002 "TARGET_SSE2 && TARGET_SSE_MATH
5003 && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)
5005 && (SSE_REG_P (operands[0])
5006 || (GET_CODE (operands[0]) == SUBREG
5007 && SSE_REG_P (SUBREG_REG (operands[0]))))"
5010 rtx op1 = operands[1];
5012 operands[3] = simplify_gen_subreg (<ssevecmode>mode, operands[0],
5014 if (GET_CODE (op1) == SUBREG)
5015 op1 = SUBREG_REG (op1);
5017 if (GENERAL_REG_P (op1) && TARGET_INTER_UNIT_MOVES)
5019 operands[4] = simplify_gen_subreg (V4SImode, operands[0], <MODE>mode, 0);
5020 emit_insn (gen_sse2_loadld (operands[4],
5021 CONST0_RTX (V4SImode), operands[1]));
5023 /* We can ignore possible trapping value in the
5024 high part of SSE register for non-trapping math. */
5025 else if (SSE_REG_P (op1) && !flag_trapping_math)
5026 operands[4] = simplify_gen_subreg (V4SImode, operands[1], SImode, 0);
5029 operands[4] = simplify_gen_subreg (V4SImode, operands[0], <MODE>mode, 0);
5030 emit_move_insn (operands[2], operands[1]);
5031 emit_insn (gen_sse2_loadld (operands[4],
5032 CONST0_RTX (V4SImode), operands[2]));
5034 if (<ssevecmode>mode == V4SFmode)
5035 emit_insn (gen_floatv4siv4sf2 (operands[3], operands[4]));
5037 emit_insn (gen_sse2_cvtdq2pd (operands[3], operands[4]));
5042 [(set (match_operand:MODEF 0 "register_operand" "")
5043 (float:MODEF (match_operand:SI 1 "memory_operand" "")))
5044 (clobber (match_operand:SI 2 "memory_operand" ""))]
5045 "TARGET_SSE2 && TARGET_SSE_MATH
5046 && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)
5048 && (SSE_REG_P (operands[0])
5049 || (GET_CODE (operands[0]) == SUBREG
5050 && SSE_REG_P (SUBREG_REG (operands[0]))))"
5053 operands[3] = simplify_gen_subreg (<ssevecmode>mode, operands[0],
5055 operands[4] = simplify_gen_subreg (V4SImode, operands[0], <MODE>mode, 0);
5057 emit_insn (gen_sse2_loadld (operands[4],
5058 CONST0_RTX (V4SImode), operands[1]));
5059 if (<ssevecmode>mode == V4SFmode)
5060 emit_insn (gen_floatv4siv4sf2 (operands[3], operands[4]));
5062 emit_insn (gen_sse2_cvtdq2pd (operands[3], operands[4]));
5067 [(set (match_operand:MODEF 0 "register_operand" "")
5068 (float:MODEF (match_operand:SI 1 "register_operand" "")))]
5069 "TARGET_SSE2 && TARGET_SSE_MATH
5070 && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)
5072 && (SSE_REG_P (operands[0])
5073 || (GET_CODE (operands[0]) == SUBREG
5074 && SSE_REG_P (SUBREG_REG (operands[0]))))"
5077 rtx op1 = operands[1];
5079 operands[3] = simplify_gen_subreg (<ssevecmode>mode, operands[0],
5081 if (GET_CODE (op1) == SUBREG)
5082 op1 = SUBREG_REG (op1);
5084 if (GENERAL_REG_P (op1))
5086 operands[4] = simplify_gen_subreg (V4SImode, operands[0], <MODE>mode, 0);
5087 if (TARGET_INTER_UNIT_MOVES)
5088 emit_insn (gen_sse2_loadld (operands[4],
5089 CONST0_RTX (V4SImode), operands[1]));
5092 operands[5] = ix86_force_to_memory (GET_MODE (operands[1]),
5094 emit_insn (gen_sse2_loadld (operands[4],
5095 CONST0_RTX (V4SImode), operands[5]));
5096 ix86_free_from_memory (GET_MODE (operands[1]));
5099 /* We can ignore possible trapping value in the
5100 high part of SSE register for non-trapping math. */
5101 else if (SSE_REG_P (op1) && !flag_trapping_math)
5102 operands[4] = simplify_gen_subreg (V4SImode, operands[1], SImode, 0);
5105 if (<ssevecmode>mode == V4SFmode)
5106 emit_insn (gen_floatv4siv4sf2 (operands[3], operands[4]));
5108 emit_insn (gen_sse2_cvtdq2pd (operands[3], operands[4]));
5113 [(set (match_operand:MODEF 0 "register_operand" "")
5114 (float:MODEF (match_operand:SI 1 "memory_operand" "")))]
5115 "TARGET_SSE2 && TARGET_SSE_MATH
5116 && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)
5118 && (SSE_REG_P (operands[0])
5119 || (GET_CODE (operands[0]) == SUBREG
5120 && SSE_REG_P (SUBREG_REG (operands[0]))))"
5123 operands[3] = simplify_gen_subreg (<ssevecmode>mode, operands[0],
5125 operands[4] = simplify_gen_subreg (V4SImode, operands[0], <MODE>mode, 0);
5127 emit_insn (gen_sse2_loadld (operands[4],
5128 CONST0_RTX (V4SImode), operands[1]));
5129 if (<ssevecmode>mode == V4SFmode)
5130 emit_insn (gen_floatv4siv4sf2 (operands[3], operands[4]));
5132 emit_insn (gen_sse2_cvtdq2pd (operands[3], operands[4]));
5136 (define_insn "*float<SWI48x:mode><MODEF:mode>2_sse_with_temp"
5137 [(set (match_operand:MODEF 0 "register_operand" "=x,x")
5139 (match_operand:SWI48x 1 "nonimmediate_operand" "r,m")))
5140 (clobber (match_operand:SWI48x 2 "memory_operand" "=m,X"))]
5141 "(<SWI48x:MODE>mode != DImode || TARGET_64BIT)
5142 && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH"
5144 [(set_attr "type" "sseicvt")
5145 (set_attr "mode" "<MODEF:MODE>")
5146 (set_attr "athlon_decode" "double,direct")
5147 (set_attr "amdfam10_decode" "vector,double")
5148 (set_attr "bdver1_decode" "double,direct")
5149 (set_attr "fp_int_src" "true")])
5151 (define_insn "*float<SWI48x:mode><MODEF:mode>2_sse_interunit"
5152 [(set (match_operand:MODEF 0 "register_operand" "=x,x")
5154 (match_operand:SWI48x 1 "nonimmediate_operand" "r,m")))]
5155 "(<SWI48x:MODE>mode != DImode || TARGET_64BIT)
5156 && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
5157 && (TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))"
5158 "%vcvtsi2<MODEF:ssemodesuffix><SWI48x:rex64suffix>\t{%1, %d0|%d0, %1}"
5159 [(set_attr "type" "sseicvt")
5160 (set_attr "prefix" "maybe_vex")
5161 (set_attr "mode" "<MODEF:MODE>")
5162 (set (attr "prefix_rex")
5164 (and (eq_attr "prefix" "maybe_vex")
5165 (match_test "<SWI48x:MODE>mode == DImode"))
5167 (const_string "*")))
5168 (set_attr "athlon_decode" "double,direct")
5169 (set_attr "amdfam10_decode" "vector,double")
5170 (set_attr "bdver1_decode" "double,direct")
5171 (set_attr "fp_int_src" "true")])
5174 [(set (match_operand:MODEF 0 "register_operand" "")
5175 (float:MODEF (match_operand:SWI48x 1 "nonimmediate_operand" "")))
5176 (clobber (match_operand:SWI48x 2 "memory_operand" ""))]
5177 "(<SWI48x:MODE>mode != DImode || TARGET_64BIT)
5178 && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
5179 && (TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))
5181 && (SSE_REG_P (operands[0])
5182 || (GET_CODE (operands[0]) == SUBREG
5183 && SSE_REG_P (SUBREG_REG (operands[0]))))"
5184 [(set (match_dup 0) (float:MODEF (match_dup 1)))])
5186 (define_insn "*float<SWI48x:mode><MODEF:mode>2_sse_nointerunit"
5187 [(set (match_operand:MODEF 0 "register_operand" "=x")
5189 (match_operand:SWI48x 1 "memory_operand" "m")))]
5190 "(<SWI48x:MODE>mode != DImode || TARGET_64BIT)
5191 && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
5192 && !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))"
5193 "%vcvtsi2<MODEF:ssemodesuffix><SWI48x:rex64suffix>\t{%1, %d0|%d0, %1}"
5194 [(set_attr "type" "sseicvt")
5195 (set_attr "prefix" "maybe_vex")
5196 (set_attr "mode" "<MODEF:MODE>")
5197 (set (attr "prefix_rex")
5199 (and (eq_attr "prefix" "maybe_vex")
5200 (match_test "<SWI48x:MODE>mode == DImode"))
5202 (const_string "*")))
5203 (set_attr "athlon_decode" "direct")
5204 (set_attr "amdfam10_decode" "double")
5205 (set_attr "bdver1_decode" "direct")
5206 (set_attr "fp_int_src" "true")])
5209 [(set (match_operand:MODEF 0 "register_operand" "")
5210 (float:MODEF (match_operand:SWI48x 1 "register_operand" "")))
5211 (clobber (match_operand:SWI48x 2 "memory_operand" ""))]
5212 "(<SWI48x:MODE>mode != DImode || TARGET_64BIT)
5213 && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
5214 && !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))
5216 && (SSE_REG_P (operands[0])
5217 || (GET_CODE (operands[0]) == SUBREG
5218 && SSE_REG_P (SUBREG_REG (operands[0]))))"
5219 [(set (match_dup 2) (match_dup 1))
5220 (set (match_dup 0) (float:MODEF (match_dup 2)))])
5223 [(set (match_operand:MODEF 0 "register_operand" "")
5224 (float:MODEF (match_operand:SWI48x 1 "memory_operand" "")))
5225 (clobber (match_operand:SWI48x 2 "memory_operand" ""))]
5226 "(<SWI48x:MODE>mode != DImode || TARGET_64BIT)
5227 && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
5229 && (SSE_REG_P (operands[0])
5230 || (GET_CODE (operands[0]) == SUBREG
5231 && SSE_REG_P (SUBREG_REG (operands[0]))))"
5232 [(set (match_dup 0) (float:MODEF (match_dup 1)))])
5234 (define_insn "*float<SWI48x:mode><X87MODEF:mode>2_i387_with_temp"
5235 [(set (match_operand:X87MODEF 0 "register_operand" "=f,f")
5237 (match_operand:SWI48x 1 "nonimmediate_operand" "m,?r")))
5238 (clobber (match_operand:SWI48x 2 "memory_operand" "=X,m"))]
5240 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SWI48x:MODE>mode)"
5244 [(set_attr "type" "fmov,multi")
5245 (set_attr "mode" "<X87MODEF:MODE>")
5246 (set_attr "unit" "*,i387")
5247 (set_attr "fp_int_src" "true")])
5249 (define_insn "*float<SWI48x:mode><X87MODEF:mode>2_i387"
5250 [(set (match_operand:X87MODEF 0 "register_operand" "=f")
5252 (match_operand:SWI48x 1 "memory_operand" "m")))]
5254 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SWI48x:MODE>mode)"
5256 [(set_attr "type" "fmov")
5257 (set_attr "mode" "<X87MODEF:MODE>")
5258 (set_attr "fp_int_src" "true")])
5261 [(set (match_operand:X87MODEF 0 "fp_register_operand" "")
5262 (float:X87MODEF (match_operand:SWI48x 1 "register_operand" "")))
5263 (clobber (match_operand:SWI48x 2 "memory_operand" ""))]
5265 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SWI48x:MODE>mode)
5266 && reload_completed"
5267 [(set (match_dup 2) (match_dup 1))
5268 (set (match_dup 0) (float:X87MODEF (match_dup 2)))])
5271 [(set (match_operand:X87MODEF 0 "fp_register_operand" "")
5272 (float:X87MODEF (match_operand:SWI48x 1 "memory_operand" "")))
5273 (clobber (match_operand:SWI48x 2 "memory_operand" ""))]
5275 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SWI48x:MODE>mode)
5276 && reload_completed"
5277 [(set (match_dup 0) (float:X87MODEF (match_dup 1)))])
5279 ;; Avoid store forwarding (partial memory) stall penalty
5280 ;; by passing DImode value through XMM registers. */
5282 (define_insn "floatdi<X87MODEF:mode>2_i387_with_xmm"
5283 [(set (match_operand:X87MODEF 0 "register_operand" "=f,f")
5285 (match_operand:DI 1 "nonimmediate_operand" "m,?r")))
5286 (clobber (match_scratch:V4SI 3 "=X,x"))
5287 (clobber (match_scratch:V4SI 4 "=X,x"))
5288 (clobber (match_operand:DI 2 "memory_operand" "=X,m"))]
5289 "TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode)
5290 && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES
5291 && !TARGET_64BIT && optimize_function_for_speed_p (cfun)"
5293 [(set_attr "type" "multi")
5294 (set_attr "mode" "<X87MODEF:MODE>")
5295 (set_attr "unit" "i387")
5296 (set_attr "fp_int_src" "true")])
5299 [(set (match_operand:X87MODEF 0 "fp_register_operand" "")
5300 (float:X87MODEF (match_operand:DI 1 "register_operand" "")))
5301 (clobber (match_scratch:V4SI 3 ""))
5302 (clobber (match_scratch:V4SI 4 ""))
5303 (clobber (match_operand:DI 2 "memory_operand" ""))]
5304 "TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode)
5305 && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES
5306 && !TARGET_64BIT && optimize_function_for_speed_p (cfun)
5307 && reload_completed"
5308 [(set (match_dup 2) (match_dup 3))
5309 (set (match_dup 0) (float:X87MODEF (match_dup 2)))]
5311 /* The DImode arrived in a pair of integral registers (e.g. %edx:%eax).
5312 Assemble the 64-bit DImode value in an xmm register. */
5313 emit_insn (gen_sse2_loadld (operands[3], CONST0_RTX (V4SImode),
5314 gen_rtx_SUBREG (SImode, operands[1], 0)));
5315 emit_insn (gen_sse2_loadld (operands[4], CONST0_RTX (V4SImode),
5316 gen_rtx_SUBREG (SImode, operands[1], 4)));
5317 emit_insn (gen_vec_interleave_lowv4si (operands[3], operands[3],
5320 operands[3] = gen_rtx_REG (DImode, REGNO (operands[3]));
5324 [(set (match_operand:X87MODEF 0 "fp_register_operand" "")
5325 (float:X87MODEF (match_operand:DI 1 "memory_operand" "")))
5326 (clobber (match_scratch:V4SI 3 ""))
5327 (clobber (match_scratch:V4SI 4 ""))
5328 (clobber (match_operand:DI 2 "memory_operand" ""))]
5329 "TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode)
5330 && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES
5331 && !TARGET_64BIT && optimize_function_for_speed_p (cfun)
5332 && reload_completed"
5333 [(set (match_dup 0) (float:X87MODEF (match_dup 1)))])
5335 ;; Avoid store forwarding (partial memory) stall penalty by extending
5336 ;; SImode value to DImode through XMM register instead of pushing two
5337 ;; SImode values to stack. Note that even !TARGET_INTER_UNIT_MOVES
5338 ;; targets benefit from this optimization. Also note that fild
5339 ;; loads from memory only.
5341 (define_insn "*floatunssi<mode>2_1"
5342 [(set (match_operand:X87MODEF 0 "register_operand" "=f,f")
5343 (unsigned_float:X87MODEF
5344 (match_operand:SI 1 "nonimmediate_operand" "x,m")))
5345 (clobber (match_operand:DI 2 "memory_operand" "=m,m"))
5346 (clobber (match_scratch:SI 3 "=X,x"))]
5348 && TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode)
5351 [(set_attr "type" "multi")
5352 (set_attr "mode" "<MODE>")])
5355 [(set (match_operand:X87MODEF 0 "register_operand" "")
5356 (unsigned_float:X87MODEF
5357 (match_operand:SI 1 "register_operand" "")))
5358 (clobber (match_operand:DI 2 "memory_operand" ""))
5359 (clobber (match_scratch:SI 3 ""))]
5361 && TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode)
5363 && reload_completed"
5364 [(set (match_dup 2) (match_dup 1))
5366 (float:X87MODEF (match_dup 2)))]
5367 "operands[1] = simplify_gen_subreg (DImode, operands[1], SImode, 0);")
5370 [(set (match_operand:X87MODEF 0 "register_operand" "")
5371 (unsigned_float:X87MODEF
5372 (match_operand:SI 1 "memory_operand" "")))
5373 (clobber (match_operand:DI 2 "memory_operand" ""))
5374 (clobber (match_scratch:SI 3 ""))]
5376 && TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode)
5378 && reload_completed"
5379 [(set (match_dup 2) (match_dup 3))
5381 (float:X87MODEF (match_dup 2)))]
5383 emit_move_insn (operands[3], operands[1]);
5384 operands[3] = simplify_gen_subreg (DImode, operands[3], SImode, 0);
5387 (define_expand "floatunssi<mode>2"
5389 [(set (match_operand:X87MODEF 0 "register_operand" "")
5390 (unsigned_float:X87MODEF
5391 (match_operand:SI 1 "nonimmediate_operand" "")))
5392 (clobber (match_dup 2))
5393 (clobber (match_scratch:SI 3 ""))])]
5395 && ((TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode)
5397 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH))"
5399 if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
5401 ix86_expand_convert_uns_si<mode>_sse (operands[0], operands[1]);
5405 operands[2] = assign_386_stack_local (DImode, SLOT_TEMP);
5408 (define_expand "floatunsdisf2"
5409 [(use (match_operand:SF 0 "register_operand" ""))
5410 (use (match_operand:DI 1 "nonimmediate_operand" ""))]
5411 "TARGET_64BIT && TARGET_SSE_MATH"
5412 "x86_emit_floatuns (operands); DONE;")
5414 (define_expand "floatunsdidf2"
5415 [(use (match_operand:DF 0 "register_operand" ""))
5416 (use (match_operand:DI 1 "nonimmediate_operand" ""))]
5417 "(TARGET_64BIT || TARGET_KEEPS_VECTOR_ALIGNED_STACK)
5418 && TARGET_SSE2 && TARGET_SSE_MATH"
5421 x86_emit_floatuns (operands);
5423 ix86_expand_convert_uns_didf_sse (operands[0], operands[1]);
5427 ;; Load effective address instructions
5429 (define_insn_and_split "*lea<mode>"
5430 [(set (match_operand:SWI48 0 "register_operand" "=r")
5431 (match_operand:SWI48 1 "lea_address_operand" "p"))]
5434 rtx addr = operands[1];
5436 if (SImode_address_operand (addr, VOIDmode))
5438 gcc_assert (TARGET_64BIT);
5439 return "lea{l}\t{%E1, %k0|%k0, %E1}";
5442 return "lea{<imodesuffix>}\t{%E1, %0|%0, %E1}";
5444 "reload_completed && ix86_avoid_lea_for_addr (insn, operands)"
5447 ix86_split_lea_for_addr (operands, <MODE>mode);
5450 [(set_attr "type" "lea")
5453 (match_operand 1 "SImode_address_operand")
5455 (const_string "<MODE>")))])
5459 (define_expand "add<mode>3"
5460 [(set (match_operand:SDWIM 0 "nonimmediate_operand" "")
5461 (plus:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand" "")
5462 (match_operand:SDWIM 2 "<general_operand>" "")))]
5464 "ix86_expand_binary_operator (PLUS, <MODE>mode, operands); DONE;")
5466 (define_insn_and_split "*add<dwi>3_doubleword"
5467 [(set (match_operand:<DWI> 0 "nonimmediate_operand" "=r,o")
5469 (match_operand:<DWI> 1 "nonimmediate_operand" "%0,0")
5470 (match_operand:<DWI> 2 "<general_operand>" "ro<di>,r<di>")))
5471 (clobber (reg:CC FLAGS_REG))]
5472 "ix86_binary_operator_ok (PLUS, <DWI>mode, operands)"
5475 [(parallel [(set (reg:CC FLAGS_REG)
5476 (unspec:CC [(match_dup 1) (match_dup 2)]
5479 (plus:DWIH (match_dup 1) (match_dup 2)))])
5480 (parallel [(set (match_dup 3)
5484 (ltu:DWIH (reg:CC FLAGS_REG) (const_int 0))
5486 (clobber (reg:CC FLAGS_REG))])]
5487 "split_double_mode (<DWI>mode, &operands[0], 3, &operands[0], &operands[3]);")
5489 (define_insn "*add<mode>3_cc"
5490 [(set (reg:CC FLAGS_REG)
5492 [(match_operand:SWI48 1 "nonimmediate_operand" "%0,0")
5493 (match_operand:SWI48 2 "<general_operand>" "r<i>,rm")]
5495 (set (match_operand:SWI48 0 "nonimmediate_operand" "=rm,r")
5496 (plus:SWI48 (match_dup 1) (match_dup 2)))]
5497 "ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
5498 "add{<imodesuffix>}\t{%2, %0|%0, %2}"
5499 [(set_attr "type" "alu")
5500 (set_attr "mode" "<MODE>")])
5502 (define_insn "addqi3_cc"
5503 [(set (reg:CC FLAGS_REG)
5505 [(match_operand:QI 1 "nonimmediate_operand" "%0,0")
5506 (match_operand:QI 2 "general_operand" "qn,qm")]
5508 (set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
5509 (plus:QI (match_dup 1) (match_dup 2)))]
5510 "ix86_binary_operator_ok (PLUS, QImode, operands)"
5511 "add{b}\t{%2, %0|%0, %2}"
5512 [(set_attr "type" "alu")
5513 (set_attr "mode" "QI")])
5515 (define_insn "*add<mode>_1"
5516 [(set (match_operand:SWI48 0 "nonimmediate_operand" "=r,rm,r,r")
5518 (match_operand:SWI48 1 "nonimmediate_operand" "%0,0,r,r")
5519 (match_operand:SWI48 2 "x86_64_general_operand" "rme,re,0,le")))
5520 (clobber (reg:CC FLAGS_REG))]
5521 "ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
5523 switch (get_attr_type (insn))
5529 gcc_assert (rtx_equal_p (operands[0], operands[1]));
5530 if (operands[2] == const1_rtx)
5531 return "inc{<imodesuffix>}\t%0";
5534 gcc_assert (operands[2] == constm1_rtx);
5535 return "dec{<imodesuffix>}\t%0";
5539 /* For most processors, ADD is faster than LEA. This alternative
5540 was added to use ADD as much as possible. */
5541 if (which_alternative == 2)
5544 tmp = operands[1], operands[1] = operands[2], operands[2] = tmp;
5547 gcc_assert (rtx_equal_p (operands[0], operands[1]));
5548 if (x86_maybe_negate_const_int (&operands[2], <MODE>mode))
5549 return "sub{<imodesuffix>}\t{%2, %0|%0, %2}";
5551 return "add{<imodesuffix>}\t{%2, %0|%0, %2}";
5555 (cond [(eq_attr "alternative" "3")
5556 (const_string "lea")
5557 (match_operand:SWI48 2 "incdec_operand" "")
5558 (const_string "incdec")
5560 (const_string "alu")))
5561 (set (attr "length_immediate")
5563 (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
5565 (const_string "*")))
5566 (set_attr "mode" "<MODE>")])
5568 ;; It may seem that nonimmediate operand is proper one for operand 1.
5569 ;; The addsi_1 pattern allows nonimmediate operand at that place and
5570 ;; we take care in ix86_binary_operator_ok to not allow two memory
5571 ;; operands so proper swapping will be done in reload. This allow
5572 ;; patterns constructed from addsi_1 to match.
5574 (define_insn "addsi_1_zext"
5575 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
5577 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,r,r")
5578 (match_operand:SI 2 "x86_64_general_operand" "rme,0,le"))))
5579 (clobber (reg:CC FLAGS_REG))]
5580 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
5582 switch (get_attr_type (insn))
5588 if (operands[2] == const1_rtx)
5589 return "inc{l}\t%k0";
5592 gcc_assert (operands[2] == constm1_rtx);
5593 return "dec{l}\t%k0";
5597 /* For most processors, ADD is faster than LEA. This alternative
5598 was added to use ADD as much as possible. */
5599 if (which_alternative == 1)
5602 tmp = operands[1], operands[1] = operands[2], operands[2] = tmp;
5605 if (x86_maybe_negate_const_int (&operands[2], SImode))
5606 return "sub{l}\t{%2, %k0|%k0, %2}";
5608 return "add{l}\t{%2, %k0|%k0, %2}";
5612 (cond [(eq_attr "alternative" "2")
5613 (const_string "lea")
5614 (match_operand:SI 2 "incdec_operand" "")
5615 (const_string "incdec")
5617 (const_string "alu")))
5618 (set (attr "length_immediate")
5620 (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
5622 (const_string "*")))
5623 (set_attr "mode" "SI")])
5625 (define_insn "*addhi_1"
5626 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r,Yp")
5627 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,r,Yp")
5628 (match_operand:HI 2 "general_operand" "rn,rm,0,ln")))
5629 (clobber (reg:CC FLAGS_REG))]
5630 "ix86_binary_operator_ok (PLUS, HImode, operands)"
5632 switch (get_attr_type (insn))
5638 gcc_assert (rtx_equal_p (operands[0], operands[1]));
5639 if (operands[2] == const1_rtx)
5640 return "inc{w}\t%0";
5643 gcc_assert (operands[2] == constm1_rtx);
5644 return "dec{w}\t%0";
5648 /* For most processors, ADD is faster than LEA. This alternative
5649 was added to use ADD as much as possible. */
5650 if (which_alternative == 2)
5653 tmp = operands[1], operands[1] = operands[2], operands[2] = tmp;
5656 gcc_assert (rtx_equal_p (operands[0], operands[1]));
5657 if (x86_maybe_negate_const_int (&operands[2], HImode))
5658 return "sub{w}\t{%2, %0|%0, %2}";
5660 return "add{w}\t{%2, %0|%0, %2}";
5664 (cond [(eq_attr "alternative" "3")
5665 (const_string "lea")
5666 (match_operand:HI 2 "incdec_operand" "")
5667 (const_string "incdec")
5669 (const_string "alu")))
5670 (set (attr "length_immediate")
5672 (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
5674 (const_string "*")))
5675 (set_attr "mode" "HI,HI,HI,SI")])
5677 ;; %%% Potential partial reg stall on alternatives 3 and 4. What to do?
5678 (define_insn "*addqi_1"
5679 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,q,r,r,Yp")
5680 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,q,0,r,Yp")
5681 (match_operand:QI 2 "general_operand" "qn,qm,0,rn,0,ln")))
5682 (clobber (reg:CC FLAGS_REG))]
5683 "ix86_binary_operator_ok (PLUS, QImode, operands)"
5685 bool widen = (which_alternative == 3 || which_alternative == 4);
5687 switch (get_attr_type (insn))
5693 gcc_assert (rtx_equal_p (operands[0], operands[1]));
5694 if (operands[2] == const1_rtx)
5695 return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
5698 gcc_assert (operands[2] == constm1_rtx);
5699 return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
5703 /* For most processors, ADD is faster than LEA. These alternatives
5704 were added to use ADD as much as possible. */
5705 if (which_alternative == 2 || which_alternative == 4)
5708 tmp = operands[1], operands[1] = operands[2], operands[2] = tmp;
5711 gcc_assert (rtx_equal_p (operands[0], operands[1]));
5712 if (x86_maybe_negate_const_int (&operands[2], QImode))
5715 return "sub{l}\t{%2, %k0|%k0, %2}";
5717 return "sub{b}\t{%2, %0|%0, %2}";
5720 return "add{l}\t{%k2, %k0|%k0, %k2}";
5722 return "add{b}\t{%2, %0|%0, %2}";
5726 (cond [(eq_attr "alternative" "5")
5727 (const_string "lea")
5728 (match_operand:QI 2 "incdec_operand" "")
5729 (const_string "incdec")
5731 (const_string "alu")))
5732 (set (attr "length_immediate")
5734 (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
5736 (const_string "*")))
5737 (set_attr "mode" "QI,QI,QI,SI,SI,SI")])
5739 (define_insn "*addqi_1_slp"
5740 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
5741 (plus:QI (match_dup 0)
5742 (match_operand:QI 1 "general_operand" "qn,qm")))
5743 (clobber (reg:CC FLAGS_REG))]
5744 "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
5745 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
5747 switch (get_attr_type (insn))
5750 if (operands[1] == const1_rtx)
5751 return "inc{b}\t%0";
5754 gcc_assert (operands[1] == constm1_rtx);
5755 return "dec{b}\t%0";
5759 if (x86_maybe_negate_const_int (&operands[1], QImode))
5760 return "sub{b}\t{%1, %0|%0, %1}";
5762 return "add{b}\t{%1, %0|%0, %1}";
5766 (if_then_else (match_operand:QI 1 "incdec_operand" "")
5767 (const_string "incdec")
5768 (const_string "alu1")))
5769 (set (attr "memory")
5770 (if_then_else (match_operand 1 "memory_operand" "")
5771 (const_string "load")
5772 (const_string "none")))
5773 (set_attr "mode" "QI")])
5775 ;; Split non destructive adds if we cannot use lea.
5777 [(set (match_operand:SWI48 0 "register_operand" "")
5778 (plus:SWI48 (match_operand:SWI48 1 "register_operand" "")
5779 (match_operand:SWI48 2 "nonmemory_operand" "")))
5780 (clobber (reg:CC FLAGS_REG))]
5781 "reload_completed && ix86_avoid_lea_for_add (insn, operands)"
5782 [(set (match_dup 0) (match_dup 1))
5783 (parallel [(set (match_dup 0) (plus:<MODE> (match_dup 0) (match_dup 2)))
5784 (clobber (reg:CC FLAGS_REG))])])
5786 ;; Convert add to the lea pattern to avoid flags dependency.
5788 [(set (match_operand:SWI 0 "register_operand" "")
5789 (plus:SWI (match_operand:SWI 1 "register_operand" "")
5790 (match_operand:SWI 2 "<nonmemory_operand>" "")))
5791 (clobber (reg:CC FLAGS_REG))]
5792 "reload_completed && ix86_lea_for_add_ok (insn, operands)"
5795 enum machine_mode mode = <MODE>mode;
5798 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (SImode))
5801 operands[0] = gen_lowpart (mode, operands[0]);
5802 operands[1] = gen_lowpart (mode, operands[1]);
5803 operands[2] = gen_lowpart (mode, operands[2]);
5806 pat = gen_rtx_PLUS (mode, operands[1], operands[2]);
5808 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5812 ;; Convert add to the lea pattern to avoid flags dependency.
5814 [(set (match_operand:DI 0 "register_operand" "")
5816 (plus:SI (match_operand:SI 1 "register_operand" "")
5817 (match_operand:SI 2 "x86_64_nonmemory_operand" ""))))
5818 (clobber (reg:CC FLAGS_REG))]
5819 "TARGET_64BIT && reload_completed && ix86_lea_for_add_ok (insn, operands)"
5821 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))])
5823 (define_insn "*add<mode>_2"
5824 [(set (reg FLAGS_REG)
5827 (match_operand:SWI 1 "nonimmediate_operand" "%0,0,<r>")
5828 (match_operand:SWI 2 "<general_operand>" "<g>,<r><i>,0"))
5830 (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>,<r>m,<r>")
5831 (plus:SWI (match_dup 1) (match_dup 2)))]
5832 "ix86_match_ccmode (insn, CCGOCmode)
5833 && ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
5835 switch (get_attr_type (insn))
5838 if (operands[2] == const1_rtx)
5839 return "inc{<imodesuffix>}\t%0";
5842 gcc_assert (operands[2] == constm1_rtx);
5843 return "dec{<imodesuffix>}\t%0";
5847 if (which_alternative == 2)
5850 tmp = operands[1], operands[1] = operands[2], operands[2] = tmp;
5853 gcc_assert (rtx_equal_p (operands[0], operands[1]));
5854 if (x86_maybe_negate_const_int (&operands[2], <MODE>mode))
5855 return "sub{<imodesuffix>}\t{%2, %0|%0, %2}";
5857 return "add{<imodesuffix>}\t{%2, %0|%0, %2}";
5861 (if_then_else (match_operand:SWI 2 "incdec_operand" "")
5862 (const_string "incdec")
5863 (const_string "alu")))
5864 (set (attr "length_immediate")
5866 (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
5868 (const_string "*")))
5869 (set_attr "mode" "<MODE>")])
5871 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
5872 (define_insn "*addsi_2_zext"
5873 [(set (reg FLAGS_REG)
5875 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,r")
5876 (match_operand:SI 2 "x86_64_general_operand" "rme,0"))
5878 (set (match_operand:DI 0 "register_operand" "=r,r")
5879 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
5880 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
5881 && ix86_binary_operator_ok (PLUS, SImode, operands)"
5883 switch (get_attr_type (insn))
5886 if (operands[2] == const1_rtx)
5887 return "inc{l}\t%k0";
5890 gcc_assert (operands[2] == constm1_rtx);
5891 return "dec{l}\t%k0";
5895 if (which_alternative == 1)
5898 tmp = operands[1], operands[1] = operands[2], operands[2] = tmp;
5901 if (x86_maybe_negate_const_int (&operands[2], SImode))
5902 return "sub{l}\t{%2, %k0|%k0, %2}";
5904 return "add{l}\t{%2, %k0|%k0, %2}";
5908 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5909 (const_string "incdec")
5910 (const_string "alu")))
5911 (set (attr "length_immediate")
5913 (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
5915 (const_string "*")))
5916 (set_attr "mode" "SI")])
5918 (define_insn "*add<mode>_3"
5919 [(set (reg FLAGS_REG)
5921 (neg:SWI (match_operand:SWI 2 "<general_operand>" "<g>,0"))
5922 (match_operand:SWI 1 "nonimmediate_operand" "%0,<r>")))
5923 (clobber (match_scratch:SWI 0 "=<r>,<r>"))]
5924 "ix86_match_ccmode (insn, CCZmode)
5925 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
5927 switch (get_attr_type (insn))
5930 if (operands[2] == const1_rtx)
5931 return "inc{<imodesuffix>}\t%0";
5934 gcc_assert (operands[2] == constm1_rtx);
5935 return "dec{<imodesuffix>}\t%0";
5939 if (which_alternative == 1)
5942 tmp = operands[1], operands[1] = operands[2], operands[2] = tmp;
5945 gcc_assert (rtx_equal_p (operands[0], operands[1]));
5946 if (x86_maybe_negate_const_int (&operands[2], <MODE>mode))
5947 return "sub{<imodesuffix>}\t{%2, %0|%0, %2}";
5949 return "add{<imodesuffix>}\t{%2, %0|%0, %2}";
5953 (if_then_else (match_operand:SWI 2 "incdec_operand" "")
5954 (const_string "incdec")
5955 (const_string "alu")))
5956 (set (attr "length_immediate")
5958 (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
5960 (const_string "*")))
5961 (set_attr "mode" "<MODE>")])
5963 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
5964 (define_insn "*addsi_3_zext"
5965 [(set (reg FLAGS_REG)
5967 (neg:SI (match_operand:SI 2 "x86_64_general_operand" "rme,0"))
5968 (match_operand:SI 1 "nonimmediate_operand" "%0,r")))
5969 (set (match_operand:DI 0 "register_operand" "=r,r")
5970 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
5971 "TARGET_64BIT && ix86_match_ccmode (insn, CCZmode)
5972 && ix86_binary_operator_ok (PLUS, SImode, operands)"
5974 switch (get_attr_type (insn))
5977 if (operands[2] == const1_rtx)
5978 return "inc{l}\t%k0";
5981 gcc_assert (operands[2] == constm1_rtx);
5982 return "dec{l}\t%k0";
5986 if (which_alternative == 1)
5989 tmp = operands[1], operands[1] = operands[2], operands[2] = tmp;
5992 if (x86_maybe_negate_const_int (&operands[2], SImode))
5993 return "sub{l}\t{%2, %k0|%k0, %2}";
5995 return "add{l}\t{%2, %k0|%k0, %2}";
5999 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6000 (const_string "incdec")
6001 (const_string "alu")))
6002 (set (attr "length_immediate")
6004 (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
6006 (const_string "*")))
6007 (set_attr "mode" "SI")])
6009 ; For comparisons against 1, -1 and 128, we may generate better code
6010 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
6011 ; is matched then. We can't accept general immediate, because for
6012 ; case of overflows, the result is messed up.
6013 ; Also carry flag is reversed compared to cmp, so this conversion is valid
6014 ; only for comparisons not depending on it.
6016 (define_insn "*adddi_4"
6017 [(set (reg FLAGS_REG)
6019 (match_operand:DI 1 "nonimmediate_operand" "0")
6020 (match_operand:DI 2 "x86_64_immediate_operand" "e")))
6021 (clobber (match_scratch:DI 0 "=rm"))]
6023 && ix86_match_ccmode (insn, CCGCmode)"
6025 switch (get_attr_type (insn))
6028 if (operands[2] == constm1_rtx)
6029 return "inc{q}\t%0";
6032 gcc_assert (operands[2] == const1_rtx);
6033 return "dec{q}\t%0";
6037 if (x86_maybe_negate_const_int (&operands[2], DImode))
6038 return "add{q}\t{%2, %0|%0, %2}";
6040 return "sub{q}\t{%2, %0|%0, %2}";
6044 (if_then_else (match_operand:DI 2 "incdec_operand" "")
6045 (const_string "incdec")
6046 (const_string "alu")))
6047 (set (attr "length_immediate")
6049 (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
6051 (const_string "*")))
6052 (set_attr "mode" "DI")])
6054 ; For comparisons against 1, -1 and 128, we may generate better code
6055 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
6056 ; is matched then. We can't accept general immediate, because for
6057 ; case of overflows, the result is messed up.
6058 ; Also carry flag is reversed compared to cmp, so this conversion is valid
6059 ; only for comparisons not depending on it.
6061 (define_insn "*add<mode>_4"
6062 [(set (reg FLAGS_REG)
6064 (match_operand:SWI124 1 "nonimmediate_operand" "0")
6065 (match_operand:SWI124 2 "const_int_operand" "n")))
6066 (clobber (match_scratch:SWI124 0 "=<r>m"))]
6067 "ix86_match_ccmode (insn, CCGCmode)"
6069 switch (get_attr_type (insn))
6072 if (operands[2] == constm1_rtx)
6073 return "inc{<imodesuffix>}\t%0";
6076 gcc_assert (operands[2] == const1_rtx);
6077 return "dec{<imodesuffix>}\t%0";
6081 if (x86_maybe_negate_const_int (&operands[2], <MODE>mode))
6082 return "add{<imodesuffix>}\t{%2, %0|%0, %2}";
6084 return "sub{<imodesuffix>}\t{%2, %0|%0, %2}";
6088 (if_then_else (match_operand:<MODE> 2 "incdec_operand" "")
6089 (const_string "incdec")
6090 (const_string "alu")))
6091 (set (attr "length_immediate")
6093 (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
6095 (const_string "*")))
6096 (set_attr "mode" "<MODE>")])
6098 (define_insn "*add<mode>_5"
6099 [(set (reg FLAGS_REG)
6102 (match_operand:SWI 1 "nonimmediate_operand" "%0,<r>")
6103 (match_operand:SWI 2 "<general_operand>" "<g>,0"))
6105 (clobber (match_scratch:SWI 0 "=<r>,<r>"))]
6106 "ix86_match_ccmode (insn, CCGOCmode)
6107 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
6109 switch (get_attr_type (insn))
6112 if (operands[2] == const1_rtx)
6113 return "inc{<imodesuffix>}\t%0";
6116 gcc_assert (operands[2] == constm1_rtx);
6117 return "dec{<imodesuffix>}\t%0";
6121 if (which_alternative == 1)
6124 tmp = operands[1], operands[1] = operands[2], operands[2] = tmp;
6127 gcc_assert (rtx_equal_p (operands[0], operands[1]));
6128 if (x86_maybe_negate_const_int (&operands[2], <MODE>mode))
6129 return "sub{<imodesuffix>}\t{%2, %0|%0, %2}";
6131 return "add{<imodesuffix>}\t{%2, %0|%0, %2}";
6135 (if_then_else (match_operand:SWI 2 "incdec_operand" "")
6136 (const_string "incdec")
6137 (const_string "alu")))
6138 (set (attr "length_immediate")
6140 (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
6142 (const_string "*")))
6143 (set_attr "mode" "<MODE>")])
6145 (define_insn "*addqi_ext_1_rex64"
6146 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6151 (match_operand 1 "ext_register_operand" "0")
6154 (match_operand:QI 2 "nonmemory_operand" "Qn")))
6155 (clobber (reg:CC FLAGS_REG))]
6158 switch (get_attr_type (insn))
6161 if (operands[2] == const1_rtx)
6162 return "inc{b}\t%h0";
6165 gcc_assert (operands[2] == constm1_rtx);
6166 return "dec{b}\t%h0";
6170 return "add{b}\t{%2, %h0|%h0, %2}";
6174 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6175 (const_string "incdec")
6176 (const_string "alu")))
6177 (set_attr "modrm" "1")
6178 (set_attr "mode" "QI")])
6180 (define_insn "addqi_ext_1"
6181 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6186 (match_operand 1 "ext_register_operand" "0")
6189 (match_operand:QI 2 "general_operand" "Qmn")))
6190 (clobber (reg:CC FLAGS_REG))]
6193 switch (get_attr_type (insn))
6196 if (operands[2] == const1_rtx)
6197 return "inc{b}\t%h0";
6200 gcc_assert (operands[2] == constm1_rtx);
6201 return "dec{b}\t%h0";
6205 return "add{b}\t{%2, %h0|%h0, %2}";
6209 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6210 (const_string "incdec")
6211 (const_string "alu")))
6212 (set_attr "modrm" "1")
6213 (set_attr "mode" "QI")])
6215 (define_insn "*addqi_ext_2"
6216 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6221 (match_operand 1 "ext_register_operand" "%0")
6225 (match_operand 2 "ext_register_operand" "Q")
6228 (clobber (reg:CC FLAGS_REG))]
6230 "add{b}\t{%h2, %h0|%h0, %h2}"
6231 [(set_attr "type" "alu")
6232 (set_attr "mode" "QI")])
6234 ;; The lea patterns for modes less than 32 bits need to be matched by
6235 ;; several insns converted to real lea by splitters.
6237 (define_insn_and_split "*lea_general_1"
6238 [(set (match_operand 0 "register_operand" "=r")
6239 (plus (plus (match_operand 1 "index_register_operand" "l")
6240 (match_operand 2 "register_operand" "r"))
6241 (match_operand 3 "immediate_operand" "i")))]
6242 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode)
6243 && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
6244 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6245 && GET_MODE (operands[0]) == GET_MODE (operands[2])
6246 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
6247 || GET_MODE (operands[3]) == VOIDmode)"
6249 "&& reload_completed"
6252 enum machine_mode mode = SImode;
6255 operands[0] = gen_lowpart (mode, operands[0]);
6256 operands[1] = gen_lowpart (mode, operands[1]);
6257 operands[2] = gen_lowpart (mode, operands[2]);
6258 operands[3] = gen_lowpart (mode, operands[3]);
6260 pat = gen_rtx_PLUS (mode, gen_rtx_PLUS (mode, operands[1], operands[2]),
6263 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
6266 [(set_attr "type" "lea")
6267 (set_attr "mode" "SI")])
6269 (define_insn_and_split "*lea_general_2"
6270 [(set (match_operand 0 "register_operand" "=r")
6271 (plus (mult (match_operand 1 "index_register_operand" "l")
6272 (match_operand 2 "const248_operand" "n"))
6273 (match_operand 3 "nonmemory_operand" "ri")))]
6274 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode)
6275 && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
6276 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6277 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
6278 || GET_MODE (operands[3]) == VOIDmode)"
6280 "&& reload_completed"
6283 enum machine_mode mode = SImode;
6286 operands[0] = gen_lowpart (mode, operands[0]);
6287 operands[1] = gen_lowpart (mode, operands[1]);
6288 operands[3] = gen_lowpart (mode, operands[3]);
6290 pat = gen_rtx_PLUS (mode, gen_rtx_MULT (mode, operands[1], operands[2]),
6293 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
6296 [(set_attr "type" "lea")
6297 (set_attr "mode" "SI")])
6299 (define_insn_and_split "*lea_general_3"
6300 [(set (match_operand 0 "register_operand" "=r")
6301 (plus (plus (mult (match_operand 1 "index_register_operand" "l")
6302 (match_operand 2 "const248_operand" "n"))
6303 (match_operand 3 "register_operand" "r"))
6304 (match_operand 4 "immediate_operand" "i")))]
6305 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode)
6306 && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
6307 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6308 && GET_MODE (operands[0]) == GET_MODE (operands[3])"
6310 "&& reload_completed"
6313 enum machine_mode mode = SImode;
6316 operands[0] = gen_lowpart (mode, operands[0]);
6317 operands[1] = gen_lowpart (mode, operands[1]);
6318 operands[3] = gen_lowpart (mode, operands[3]);
6319 operands[4] = gen_lowpart (mode, operands[4]);
6321 pat = gen_rtx_PLUS (mode,
6323 gen_rtx_MULT (mode, operands[1],
6328 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
6331 [(set_attr "type" "lea")
6332 (set_attr "mode" "SI")])
6334 (define_insn_and_split "*lea_general_4"
6335 [(set (match_operand 0 "register_operand" "=r")
6337 (match_operand 1 "index_register_operand" "l")
6338 (match_operand 2 "const_int_operand" "n"))
6339 (match_operand 3 "const_int_operand" "n")))]
6340 "(((GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode)
6341 && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)))
6342 || GET_MODE (operands[0]) == SImode
6343 || (TARGET_64BIT && GET_MODE (operands[0]) == DImode))
6344 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6345 && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) - 1 < 3
6346 && ((unsigned HOST_WIDE_INT) INTVAL (operands[3])
6347 < ((unsigned HOST_WIDE_INT) 1 << INTVAL (operands[2])))"
6349 "&& reload_completed"
6352 enum machine_mode mode = GET_MODE (operands[0]);
6355 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (SImode))
6358 operands[0] = gen_lowpart (mode, operands[0]);
6359 operands[1] = gen_lowpart (mode, operands[1]);
6362 operands[2] = GEN_INT (1 << INTVAL (operands[2]));
6364 pat = plus_constant (gen_rtx_MULT (mode, operands[1], operands[2]),
6365 INTVAL (operands[3]));
6367 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
6370 [(set_attr "type" "lea")
6372 (if_then_else (match_operand:DI 0 "" "")
6374 (const_string "SI")))])
6376 ;; Subtract instructions
6378 (define_expand "sub<mode>3"
6379 [(set (match_operand:SDWIM 0 "nonimmediate_operand" "")
6380 (minus:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand" "")
6381 (match_operand:SDWIM 2 "<general_operand>" "")))]
6383 "ix86_expand_binary_operator (MINUS, <MODE>mode, operands); DONE;")
6385 (define_insn_and_split "*sub<dwi>3_doubleword"
6386 [(set (match_operand:<DWI> 0 "nonimmediate_operand" "=r,o")
6388 (match_operand:<DWI> 1 "nonimmediate_operand" "0,0")
6389 (match_operand:<DWI> 2 "<general_operand>" "ro<di>,r<di>")))
6390 (clobber (reg:CC FLAGS_REG))]
6391 "ix86_binary_operator_ok (MINUS, <MODE>mode, operands)"
6394 [(parallel [(set (reg:CC FLAGS_REG)
6395 (compare:CC (match_dup 1) (match_dup 2)))
6397 (minus:DWIH (match_dup 1) (match_dup 2)))])
6398 (parallel [(set (match_dup 3)
6402 (ltu:DWIH (reg:CC FLAGS_REG) (const_int 0))
6404 (clobber (reg:CC FLAGS_REG))])]
6405 "split_double_mode (<DWI>mode, &operands[0], 3, &operands[0], &operands[3]);")
6407 (define_insn "*sub<mode>_1"
6408 [(set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")
6410 (match_operand:SWI 1 "nonimmediate_operand" "0,0")
6411 (match_operand:SWI 2 "<general_operand>" "<r><i>,<r>m")))
6412 (clobber (reg:CC FLAGS_REG))]
6413 "ix86_binary_operator_ok (MINUS, <MODE>mode, operands)"
6414 "sub{<imodesuffix>}\t{%2, %0|%0, %2}"
6415 [(set_attr "type" "alu")
6416 (set_attr "mode" "<MODE>")])
6418 (define_insn "*subsi_1_zext"
6419 [(set (match_operand:DI 0 "register_operand" "=r")
6421 (minus:SI (match_operand:SI 1 "register_operand" "0")
6422 (match_operand:SI 2 "x86_64_general_operand" "rme"))))
6423 (clobber (reg:CC FLAGS_REG))]
6424 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
6425 "sub{l}\t{%2, %k0|%k0, %2}"
6426 [(set_attr "type" "alu")
6427 (set_attr "mode" "SI")])
6429 (define_insn "*subqi_1_slp"
6430 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
6431 (minus:QI (match_dup 0)
6432 (match_operand:QI 1 "general_operand" "qn,qm")))
6433 (clobber (reg:CC FLAGS_REG))]
6434 "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
6435 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
6436 "sub{b}\t{%1, %0|%0, %1}"
6437 [(set_attr "type" "alu1")
6438 (set_attr "mode" "QI")])
6440 (define_insn "*sub<mode>_2"
6441 [(set (reg FLAGS_REG)
6444 (match_operand:SWI 1 "nonimmediate_operand" "0,0")
6445 (match_operand:SWI 2 "<general_operand>" "<r><i>,<r>m"))
6447 (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")
6448 (minus:SWI (match_dup 1) (match_dup 2)))]
6449 "ix86_match_ccmode (insn, CCGOCmode)
6450 && ix86_binary_operator_ok (MINUS, <MODE>mode, operands)"
6451 "sub{<imodesuffix>}\t{%2, %0|%0, %2}"
6452 [(set_attr "type" "alu")
6453 (set_attr "mode" "<MODE>")])
6455 (define_insn "*subsi_2_zext"
6456 [(set (reg FLAGS_REG)
6458 (minus:SI (match_operand:SI 1 "register_operand" "0")
6459 (match_operand:SI 2 "x86_64_general_operand" "rme"))
6461 (set (match_operand:DI 0 "register_operand" "=r")
6463 (minus:SI (match_dup 1)
6465 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
6466 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6467 "sub{l}\t{%2, %k0|%k0, %2}"
6468 [(set_attr "type" "alu")
6469 (set_attr "mode" "SI")])
6471 (define_insn "*sub<mode>_3"
6472 [(set (reg FLAGS_REG)
6473 (compare (match_operand:SWI 1 "nonimmediate_operand" "0,0")
6474 (match_operand:SWI 2 "<general_operand>" "<r><i>,<r>m")))
6475 (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")
6476 (minus:SWI (match_dup 1) (match_dup 2)))]
6477 "ix86_match_ccmode (insn, CCmode)
6478 && ix86_binary_operator_ok (MINUS, <MODE>mode, operands)"
6479 "sub{<imodesuffix>}\t{%2, %0|%0, %2}"
6480 [(set_attr "type" "alu")
6481 (set_attr "mode" "<MODE>")])
6483 (define_insn "*subsi_3_zext"
6484 [(set (reg FLAGS_REG)
6485 (compare (match_operand:SI 1 "register_operand" "0")
6486 (match_operand:SI 2 "x86_64_general_operand" "rme")))
6487 (set (match_operand:DI 0 "register_operand" "=r")
6489 (minus:SI (match_dup 1)
6491 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
6492 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6493 "sub{l}\t{%2, %1|%1, %2}"
6494 [(set_attr "type" "alu")
6495 (set_attr "mode" "SI")])
6497 ;; Add with carry and subtract with borrow
6499 (define_expand "<plusminus_insn><mode>3_carry"
6501 [(set (match_operand:SWI 0 "nonimmediate_operand" "")
6503 (match_operand:SWI 1 "nonimmediate_operand" "")
6504 (plus:SWI (match_operator:SWI 4 "ix86_carry_flag_operator"
6505 [(match_operand 3 "flags_reg_operand" "")
6507 (match_operand:SWI 2 "<general_operand>" ""))))
6508 (clobber (reg:CC FLAGS_REG))])]
6509 "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)")
6511 (define_insn "*<plusminus_insn><mode>3_carry"
6512 [(set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")
6514 (match_operand:SWI 1 "nonimmediate_operand" "<comm>0,0")
6516 (match_operator 3 "ix86_carry_flag_operator"
6517 [(reg FLAGS_REG) (const_int 0)])
6518 (match_operand:SWI 2 "<general_operand>" "<r><i>,<r>m"))))
6519 (clobber (reg:CC FLAGS_REG))]
6520 "ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
6521 "<plusminus_carry_mnemonic>{<imodesuffix>}\t{%2, %0|%0, %2}"
6522 [(set_attr "type" "alu")
6523 (set_attr "use_carry" "1")
6524 (set_attr "pent_pair" "pu")
6525 (set_attr "mode" "<MODE>")])
6527 (define_insn "*addsi3_carry_zext"
6528 [(set (match_operand:DI 0 "register_operand" "=r")
6530 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
6531 (plus:SI (match_operator 3 "ix86_carry_flag_operator"
6532 [(reg FLAGS_REG) (const_int 0)])
6533 (match_operand:SI 2 "x86_64_general_operand" "rme")))))
6534 (clobber (reg:CC FLAGS_REG))]
6535 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
6536 "adc{l}\t{%2, %k0|%k0, %2}"
6537 [(set_attr "type" "alu")
6538 (set_attr "use_carry" "1")
6539 (set_attr "pent_pair" "pu")
6540 (set_attr "mode" "SI")])
6542 (define_insn "*subsi3_carry_zext"
6543 [(set (match_operand:DI 0 "register_operand" "=r")
6545 (minus:SI (match_operand:SI 1 "register_operand" "0")
6546 (plus:SI (match_operator 3 "ix86_carry_flag_operator"
6547 [(reg FLAGS_REG) (const_int 0)])
6548 (match_operand:SI 2 "x86_64_general_operand" "rme")))))
6549 (clobber (reg:CC FLAGS_REG))]
6550 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
6551 "sbb{l}\t{%2, %k0|%k0, %2}"
6552 [(set_attr "type" "alu")
6553 (set_attr "pent_pair" "pu")
6554 (set_attr "mode" "SI")])
6556 ;; Overflow setting add and subtract instructions
6558 (define_insn "*add<mode>3_cconly_overflow"
6559 [(set (reg:CCC FLAGS_REG)
6562 (match_operand:SWI 1 "nonimmediate_operand" "%0")
6563 (match_operand:SWI 2 "<general_operand>" "<g>"))
6565 (clobber (match_scratch:SWI 0 "=<r>"))]
6566 "!(MEM_P (operands[1]) && MEM_P (operands[2]))"
6567 "add{<imodesuffix>}\t{%2, %0|%0, %2}"
6568 [(set_attr "type" "alu")
6569 (set_attr "mode" "<MODE>")])
6571 (define_insn "*sub<mode>3_cconly_overflow"
6572 [(set (reg:CCC FLAGS_REG)
6575 (match_operand:SWI 0 "nonimmediate_operand" "<r>m,<r>")
6576 (match_operand:SWI 1 "<general_operand>" "<r><i>,<r>m"))
6579 "cmp{<imodesuffix>}\t{%1, %0|%0, %1}"
6580 [(set_attr "type" "icmp")
6581 (set_attr "mode" "<MODE>")])
6583 (define_insn "*<plusminus_insn><mode>3_cc_overflow"
6584 [(set (reg:CCC FLAGS_REG)
6587 (match_operand:SWI 1 "nonimmediate_operand" "<comm>0,0")
6588 (match_operand:SWI 2 "<general_operand>" "<r><i>,<r>m"))
6590 (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")
6591 (plusminus:SWI (match_dup 1) (match_dup 2)))]
6592 "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
6593 "<plusminus_mnemonic>{<imodesuffix>}\t{%2, %0|%0, %2}"
6594 [(set_attr "type" "alu")
6595 (set_attr "mode" "<MODE>")])
6597 (define_insn "*<plusminus_insn>si3_zext_cc_overflow"
6598 [(set (reg:CCC FLAGS_REG)
6601 (match_operand:SI 1 "nonimmediate_operand" "<comm>0")
6602 (match_operand:SI 2 "x86_64_general_operand" "rme"))
6604 (set (match_operand:DI 0 "register_operand" "=r")
6605 (zero_extend:DI (plusminus:SI (match_dup 1) (match_dup 2))))]
6606 "TARGET_64BIT && ix86_binary_operator_ok (<CODE>, SImode, operands)"
6607 "<plusminus_mnemonic>{l}\t{%2, %k0|%k0, %2}"
6608 [(set_attr "type" "alu")
6609 (set_attr "mode" "SI")])
6611 ;; The patterns that match these are at the end of this file.
6613 (define_expand "<plusminus_insn>xf3"
6614 [(set (match_operand:XF 0 "register_operand" "")
6616 (match_operand:XF 1 "register_operand" "")
6617 (match_operand:XF 2 "register_operand" "")))]
6620 (define_expand "<plusminus_insn><mode>3"
6621 [(set (match_operand:MODEF 0 "register_operand" "")
6623 (match_operand:MODEF 1 "register_operand" "")
6624 (match_operand:MODEF 2 "nonimmediate_operand" "")))]
6625 "(TARGET_80387 && X87_ENABLE_ARITH (<MODE>mode))
6626 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)")
6628 ;; Multiply instructions
6630 (define_expand "mul<mode>3"
6631 [(parallel [(set (match_operand:SWIM248 0 "register_operand" "")
6633 (match_operand:SWIM248 1 "register_operand" "")
6634 (match_operand:SWIM248 2 "<general_operand>" "")))
6635 (clobber (reg:CC FLAGS_REG))])])
6637 (define_expand "mulqi3"
6638 [(parallel [(set (match_operand:QI 0 "register_operand" "")
6640 (match_operand:QI 1 "register_operand" "")
6641 (match_operand:QI 2 "nonimmediate_operand" "")))
6642 (clobber (reg:CC FLAGS_REG))])]
6643 "TARGET_QIMODE_MATH")
6646 ;; IMUL reg32/64, reg32/64, imm8 Direct
6647 ;; IMUL reg32/64, mem32/64, imm8 VectorPath
6648 ;; IMUL reg32/64, reg32/64, imm32 Direct
6649 ;; IMUL reg32/64, mem32/64, imm32 VectorPath
6650 ;; IMUL reg32/64, reg32/64 Direct
6651 ;; IMUL reg32/64, mem32/64 Direct
6653 ;; On BDVER1, all above IMULs use DirectPath
6655 (define_insn "*mul<mode>3_1"
6656 [(set (match_operand:SWI48 0 "register_operand" "=r,r,r")
6658 (match_operand:SWI48 1 "nonimmediate_operand" "%rm,rm,0")
6659 (match_operand:SWI48 2 "<general_operand>" "K,<i>,mr")))
6660 (clobber (reg:CC FLAGS_REG))]
6661 "!(MEM_P (operands[1]) && MEM_P (operands[2]))"
6663 imul{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}
6664 imul{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}
6665 imul{<imodesuffix>}\t{%2, %0|%0, %2}"
6666 [(set_attr "type" "imul")
6667 (set_attr "prefix_0f" "0,0,1")
6668 (set (attr "athlon_decode")
6669 (cond [(eq_attr "cpu" "athlon")
6670 (const_string "vector")
6671 (eq_attr "alternative" "1")
6672 (const_string "vector")
6673 (and (eq_attr "alternative" "2")
6674 (match_operand 1 "memory_operand" ""))
6675 (const_string "vector")]
6676 (const_string "direct")))
6677 (set (attr "amdfam10_decode")
6678 (cond [(and (eq_attr "alternative" "0,1")
6679 (match_operand 1 "memory_operand" ""))
6680 (const_string "vector")]
6681 (const_string "direct")))
6682 (set_attr "bdver1_decode" "direct")
6683 (set_attr "mode" "<MODE>")])
6685 (define_insn "*mulsi3_1_zext"
6686 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
6688 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,rm,0")
6689 (match_operand:SI 2 "x86_64_general_operand" "K,e,mr"))))
6690 (clobber (reg:CC FLAGS_REG))]
6692 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
6694 imul{l}\t{%2, %1, %k0|%k0, %1, %2}
6695 imul{l}\t{%2, %1, %k0|%k0, %1, %2}
6696 imul{l}\t{%2, %k0|%k0, %2}"
6697 [(set_attr "type" "imul")
6698 (set_attr "prefix_0f" "0,0,1")
6699 (set (attr "athlon_decode")
6700 (cond [(eq_attr "cpu" "athlon")
6701 (const_string "vector")
6702 (eq_attr "alternative" "1")
6703 (const_string "vector")
6704 (and (eq_attr "alternative" "2")
6705 (match_operand 1 "memory_operand" ""))
6706 (const_string "vector")]
6707 (const_string "direct")))
6708 (set (attr "amdfam10_decode")
6709 (cond [(and (eq_attr "alternative" "0,1")
6710 (match_operand 1 "memory_operand" ""))
6711 (const_string "vector")]
6712 (const_string "direct")))
6713 (set_attr "bdver1_decode" "direct")
6714 (set_attr "mode" "SI")])
6717 ;; IMUL reg16, reg16, imm8 VectorPath
6718 ;; IMUL reg16, mem16, imm8 VectorPath
6719 ;; IMUL reg16, reg16, imm16 VectorPath
6720 ;; IMUL reg16, mem16, imm16 VectorPath
6721 ;; IMUL reg16, reg16 Direct
6722 ;; IMUL reg16, mem16 Direct
6724 ;; On BDVER1, all HI MULs use DoublePath
6726 (define_insn "*mulhi3_1"
6727 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
6728 (mult:HI (match_operand:HI 1 "nonimmediate_operand" "%rm,rm,0")
6729 (match_operand:HI 2 "general_operand" "K,n,mr")))
6730 (clobber (reg:CC FLAGS_REG))]
6732 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
6734 imul{w}\t{%2, %1, %0|%0, %1, %2}
6735 imul{w}\t{%2, %1, %0|%0, %1, %2}
6736 imul{w}\t{%2, %0|%0, %2}"
6737 [(set_attr "type" "imul")
6738 (set_attr "prefix_0f" "0,0,1")
6739 (set (attr "athlon_decode")
6740 (cond [(eq_attr "cpu" "athlon")
6741 (const_string "vector")
6742 (eq_attr "alternative" "1,2")
6743 (const_string "vector")]
6744 (const_string "direct")))
6745 (set (attr "amdfam10_decode")
6746 (cond [(eq_attr "alternative" "0,1")
6747 (const_string "vector")]
6748 (const_string "direct")))
6749 (set_attr "bdver1_decode" "double")
6750 (set_attr "mode" "HI")])
6752 ;;On AMDFAM10 and BDVER1
6756 (define_insn "*mulqi3_1"
6757 [(set (match_operand:QI 0 "register_operand" "=a")
6758 (mult:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
6759 (match_operand:QI 2 "nonimmediate_operand" "qm")))
6760 (clobber (reg:CC FLAGS_REG))]
6762 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
6764 [(set_attr "type" "imul")
6765 (set_attr "length_immediate" "0")
6766 (set (attr "athlon_decode")
6767 (if_then_else (eq_attr "cpu" "athlon")
6768 (const_string "vector")
6769 (const_string "direct")))
6770 (set_attr "amdfam10_decode" "direct")
6771 (set_attr "bdver1_decode" "direct")
6772 (set_attr "mode" "QI")])
6774 (define_expand "<u>mul<mode><dwi>3"
6775 [(parallel [(set (match_operand:<DWI> 0 "register_operand" "")
6778 (match_operand:DWIH 1 "nonimmediate_operand" ""))
6780 (match_operand:DWIH 2 "register_operand" ""))))
6781 (clobber (reg:CC FLAGS_REG))])])
6783 (define_expand "<u>mulqihi3"
6784 [(parallel [(set (match_operand:HI 0 "register_operand" "")
6787 (match_operand:QI 1 "nonimmediate_operand" ""))
6789 (match_operand:QI 2 "register_operand" ""))))
6790 (clobber (reg:CC FLAGS_REG))])]
6791 "TARGET_QIMODE_MATH")
6793 (define_insn "*bmi2_umulditi3_1"
6794 [(set (match_operand:DI 0 "register_operand" "=r")
6796 (match_operand:DI 2 "nonimmediate_operand" "%d")
6797 (match_operand:DI 3 "nonimmediate_operand" "rm")))
6798 (set (match_operand:DI 1 "register_operand" "=r")
6801 (mult:TI (zero_extend:TI (match_dup 2))
6802 (zero_extend:TI (match_dup 3)))
6804 "TARGET_64BIT && TARGET_BMI2
6805 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
6806 "mulx\t{%3, %0, %1|%1, %0, %3}"
6807 [(set_attr "type" "imulx")
6808 (set_attr "prefix" "vex")
6809 (set_attr "mode" "DI")])
6811 (define_insn "*bmi2_umulsidi3_1"
6812 [(set (match_operand:SI 0 "register_operand" "=r")
6814 (match_operand:SI 2 "nonimmediate_operand" "%d")
6815 (match_operand:SI 3 "nonimmediate_operand" "rm")))
6816 (set (match_operand:SI 1 "register_operand" "=r")
6819 (mult:DI (zero_extend:DI (match_dup 2))
6820 (zero_extend:DI (match_dup 3)))
6822 "!TARGET_64BIT && TARGET_BMI2
6823 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
6824 "mulx\t{%3, %0, %1|%1, %0, %3}"
6825 [(set_attr "type" "imulx")
6826 (set_attr "prefix" "vex")
6827 (set_attr "mode" "SI")])
6829 (define_insn "*umul<mode><dwi>3_1"
6830 [(set (match_operand:<DWI> 0 "register_operand" "=A,r")
6833 (match_operand:DWIH 1 "nonimmediate_operand" "%0,d"))
6835 (match_operand:DWIH 2 "nonimmediate_operand" "rm,rm"))))
6836 (clobber (reg:CC FLAGS_REG))]
6837 "!(MEM_P (operands[1]) && MEM_P (operands[2]))"
6839 mul{<imodesuffix>}\t%2
6841 [(set_attr "isa" "*,bmi2")
6842 (set_attr "type" "imul,imulx")
6843 (set_attr "length_immediate" "0,*")
6844 (set (attr "athlon_decode")
6845 (cond [(eq_attr "alternative" "0")
6846 (if_then_else (eq_attr "cpu" "athlon")
6847 (const_string "vector")
6848 (const_string "double"))]
6849 (const_string "*")))
6850 (set_attr "amdfam10_decode" "double,*")
6851 (set_attr "bdver1_decode" "direct,*")
6852 (set_attr "prefix" "orig,vex")
6853 (set_attr "mode" "<MODE>")])
6855 ;; Convert mul to the mulx pattern to avoid flags dependency.
6857 [(set (match_operand:<DWI> 0 "register_operand" "")
6860 (match_operand:DWIH 1 "register_operand" ""))
6862 (match_operand:DWIH 2 "nonimmediate_operand" ""))))
6863 (clobber (reg:CC FLAGS_REG))]
6864 "TARGET_BMI2 && reload_completed
6865 && true_regnum (operands[1]) == DX_REG"
6866 [(parallel [(set (match_dup 3)
6867 (mult:DWIH (match_dup 1) (match_dup 2)))
6871 (mult:<DWI> (zero_extend:<DWI> (match_dup 1))
6872 (zero_extend:<DWI> (match_dup 2)))
6875 split_double_mode (<DWI>mode, &operands[0], 1, &operands[3], &operands[4]);
6877 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
6880 (define_insn "*mul<mode><dwi>3_1"
6881 [(set (match_operand:<DWI> 0 "register_operand" "=A")
6884 (match_operand:DWIH 1 "nonimmediate_operand" "%0"))
6886 (match_operand:DWIH 2 "nonimmediate_operand" "rm"))))
6887 (clobber (reg:CC FLAGS_REG))]
6888 "!(MEM_P (operands[1]) && MEM_P (operands[2]))"
6889 "imul{<imodesuffix>}\t%2"
6890 [(set_attr "type" "imul")
6891 (set_attr "length_immediate" "0")
6892 (set (attr "athlon_decode")
6893 (if_then_else (eq_attr "cpu" "athlon")
6894 (const_string "vector")
6895 (const_string "double")))
6896 (set_attr "amdfam10_decode" "double")
6897 (set_attr "bdver1_decode" "direct")
6898 (set_attr "mode" "<MODE>")])
6900 (define_insn "*<u>mulqihi3_1"
6901 [(set (match_operand:HI 0 "register_operand" "=a")
6904 (match_operand:QI 1 "nonimmediate_operand" "%0"))
6906 (match_operand:QI 2 "nonimmediate_operand" "qm"))))
6907 (clobber (reg:CC FLAGS_REG))]
6909 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
6910 "<sgnprefix>mul{b}\t%2"
6911 [(set_attr "type" "imul")
6912 (set_attr "length_immediate" "0")
6913 (set (attr "athlon_decode")
6914 (if_then_else (eq_attr "cpu" "athlon")
6915 (const_string "vector")
6916 (const_string "direct")))
6917 (set_attr "amdfam10_decode" "direct")
6918 (set_attr "bdver1_decode" "direct")
6919 (set_attr "mode" "QI")])
6921 (define_expand "<s>mul<mode>3_highpart"
6922 [(parallel [(set (match_operand:SWI48 0 "register_operand" "")
6927 (match_operand:SWI48 1 "nonimmediate_operand" ""))
6929 (match_operand:SWI48 2 "register_operand" "")))
6931 (clobber (match_scratch:SWI48 3 ""))
6932 (clobber (reg:CC FLAGS_REG))])]
6934 "operands[4] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));")
6936 (define_insn "*<s>muldi3_highpart_1"
6937 [(set (match_operand:DI 0 "register_operand" "=d")
6942 (match_operand:DI 1 "nonimmediate_operand" "%a"))
6944 (match_operand:DI 2 "nonimmediate_operand" "rm")))
6946 (clobber (match_scratch:DI 3 "=1"))
6947 (clobber (reg:CC FLAGS_REG))]
6949 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
6950 "<sgnprefix>mul{q}\t%2"
6951 [(set_attr "type" "imul")
6952 (set_attr "length_immediate" "0")
6953 (set (attr "athlon_decode")
6954 (if_then_else (eq_attr "cpu" "athlon")
6955 (const_string "vector")
6956 (const_string "double")))
6957 (set_attr "amdfam10_decode" "double")
6958 (set_attr "bdver1_decode" "direct")
6959 (set_attr "mode" "DI")])
6961 (define_insn "*<s>mulsi3_highpart_1"
6962 [(set (match_operand:SI 0 "register_operand" "=d")
6967 (match_operand:SI 1 "nonimmediate_operand" "%a"))
6969 (match_operand:SI 2 "nonimmediate_operand" "rm")))
6971 (clobber (match_scratch:SI 3 "=1"))
6972 (clobber (reg:CC FLAGS_REG))]
6973 "!(MEM_P (operands[1]) && MEM_P (operands[2]))"
6974 "<sgnprefix>mul{l}\t%2"
6975 [(set_attr "type" "imul")
6976 (set_attr "length_immediate" "0")
6977 (set (attr "athlon_decode")
6978 (if_then_else (eq_attr "cpu" "athlon")
6979 (const_string "vector")
6980 (const_string "double")))
6981 (set_attr "amdfam10_decode" "double")
6982 (set_attr "bdver1_decode" "direct")
6983 (set_attr "mode" "SI")])
6985 (define_insn "*<s>mulsi3_highpart_zext"
6986 [(set (match_operand:DI 0 "register_operand" "=d")
6987 (zero_extend:DI (truncate:SI
6989 (mult:DI (any_extend:DI
6990 (match_operand:SI 1 "nonimmediate_operand" "%a"))
6992 (match_operand:SI 2 "nonimmediate_operand" "rm")))
6994 (clobber (match_scratch:SI 3 "=1"))
6995 (clobber (reg:CC FLAGS_REG))]
6997 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
6998 "<sgnprefix>mul{l}\t%2"
6999 [(set_attr "type" "imul")
7000 (set_attr "length_immediate" "0")
7001 (set (attr "athlon_decode")
7002 (if_then_else (eq_attr "cpu" "athlon")
7003 (const_string "vector")
7004 (const_string "double")))
7005 (set_attr "amdfam10_decode" "double")
7006 (set_attr "bdver1_decode" "direct")
7007 (set_attr "mode" "SI")])
7009 ;; The patterns that match these are at the end of this file.
7011 (define_expand "mulxf3"
7012 [(set (match_operand:XF 0 "register_operand" "")
7013 (mult:XF (match_operand:XF 1 "register_operand" "")
7014 (match_operand:XF 2 "register_operand" "")))]
7017 (define_expand "mul<mode>3"
7018 [(set (match_operand:MODEF 0 "register_operand" "")
7019 (mult:MODEF (match_operand:MODEF 1 "register_operand" "")
7020 (match_operand:MODEF 2 "nonimmediate_operand" "")))]
7021 "(TARGET_80387 && X87_ENABLE_ARITH (<MODE>mode))
7022 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)")
7024 ;; Divide instructions
7026 ;; The patterns that match these are at the end of this file.
7028 (define_expand "divxf3"
7029 [(set (match_operand:XF 0 "register_operand" "")
7030 (div:XF (match_operand:XF 1 "register_operand" "")
7031 (match_operand:XF 2 "register_operand" "")))]
7034 (define_expand "divdf3"
7035 [(set (match_operand:DF 0 "register_operand" "")
7036 (div:DF (match_operand:DF 1 "register_operand" "")
7037 (match_operand:DF 2 "nonimmediate_operand" "")))]
7038 "(TARGET_80387 && X87_ENABLE_ARITH (DFmode))
7039 || (TARGET_SSE2 && TARGET_SSE_MATH)")
7041 (define_expand "divsf3"
7042 [(set (match_operand:SF 0 "register_operand" "")
7043 (div:SF (match_operand:SF 1 "register_operand" "")
7044 (match_operand:SF 2 "nonimmediate_operand" "")))]
7045 "(TARGET_80387 && X87_ENABLE_ARITH (SFmode))
7050 && optimize_insn_for_speed_p ()
7051 && flag_finite_math_only && !flag_trapping_math
7052 && flag_unsafe_math_optimizations)
7054 ix86_emit_swdivsf (operands[0], operands[1],
7055 operands[2], SFmode);
7060 ;; Divmod instructions.
7062 (define_expand "divmod<mode>4"
7063 [(parallel [(set (match_operand:SWIM248 0 "register_operand" "")
7065 (match_operand:SWIM248 1 "register_operand" "")
7066 (match_operand:SWIM248 2 "nonimmediate_operand" "")))
7067 (set (match_operand:SWIM248 3 "register_operand" "")
7068 (mod:SWIM248 (match_dup 1) (match_dup 2)))
7069 (clobber (reg:CC FLAGS_REG))])])
7071 ;; Split with 8bit unsigned divide:
7072 ;; if (dividend an divisor are in [0-255])
7073 ;; use 8bit unsigned integer divide
7075 ;; use original integer divide
7077 [(set (match_operand:SWI48 0 "register_operand" "")
7078 (div:SWI48 (match_operand:SWI48 2 "register_operand" "")
7079 (match_operand:SWI48 3 "nonimmediate_operand" "")))
7080 (set (match_operand:SWI48 1 "register_operand" "")
7081 (mod:SWI48 (match_dup 2) (match_dup 3)))
7082 (clobber (reg:CC FLAGS_REG))]
7083 "TARGET_USE_8BIT_IDIV
7084 && TARGET_QIMODE_MATH
7085 && can_create_pseudo_p ()
7086 && !optimize_insn_for_size_p ()"
7088 "ix86_split_idivmod (<MODE>mode, operands, true); DONE;")
7090 (define_insn_and_split "divmod<mode>4_1"
7091 [(set (match_operand:SWI48 0 "register_operand" "=a")
7092 (div:SWI48 (match_operand:SWI48 2 "register_operand" "0")
7093 (match_operand:SWI48 3 "nonimmediate_operand" "rm")))
7094 (set (match_operand:SWI48 1 "register_operand" "=&d")
7095 (mod:SWI48 (match_dup 2) (match_dup 3)))
7096 (unspec [(const_int 0)] UNSPEC_DIV_ALREADY_SPLIT)
7097 (clobber (reg:CC FLAGS_REG))]
7101 [(parallel [(set (match_dup 1)
7102 (ashiftrt:SWI48 (match_dup 4) (match_dup 5)))
7103 (clobber (reg:CC FLAGS_REG))])
7104 (parallel [(set (match_dup 0)
7105 (div:SWI48 (match_dup 2) (match_dup 3)))
7107 (mod:SWI48 (match_dup 2) (match_dup 3)))
7109 (clobber (reg:CC FLAGS_REG))])]
7111 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode)-1);
7113 if (optimize_function_for_size_p (cfun) || TARGET_USE_CLTD)
7114 operands[4] = operands[2];
7117 /* Avoid use of cltd in favor of a mov+shift. */
7118 emit_move_insn (operands[1], operands[2]);
7119 operands[4] = operands[1];
7122 [(set_attr "type" "multi")
7123 (set_attr "mode" "<MODE>")])
7125 (define_insn_and_split "*divmod<mode>4"
7126 [(set (match_operand:SWIM248 0 "register_operand" "=a")
7127 (div:SWIM248 (match_operand:SWIM248 2 "register_operand" "0")
7128 (match_operand:SWIM248 3 "nonimmediate_operand" "rm")))
7129 (set (match_operand:SWIM248 1 "register_operand" "=&d")
7130 (mod:SWIM248 (match_dup 2) (match_dup 3)))
7131 (clobber (reg:CC FLAGS_REG))]
7135 [(parallel [(set (match_dup 1)
7136 (ashiftrt:SWIM248 (match_dup 4) (match_dup 5)))
7137 (clobber (reg:CC FLAGS_REG))])
7138 (parallel [(set (match_dup 0)
7139 (div:SWIM248 (match_dup 2) (match_dup 3)))
7141 (mod:SWIM248 (match_dup 2) (match_dup 3)))
7143 (clobber (reg:CC FLAGS_REG))])]
7145 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode)-1);
7147 if (<MODE>mode != HImode
7148 && (optimize_function_for_size_p (cfun) || TARGET_USE_CLTD))
7149 operands[4] = operands[2];
7152 /* Avoid use of cltd in favor of a mov+shift. */
7153 emit_move_insn (operands[1], operands[2]);
7154 operands[4] = operands[1];
7157 [(set_attr "type" "multi")
7158 (set_attr "mode" "<MODE>")])
7160 (define_insn "*divmod<mode>4_noext"
7161 [(set (match_operand:SWIM248 0 "register_operand" "=a")
7162 (div:SWIM248 (match_operand:SWIM248 2 "register_operand" "0")
7163 (match_operand:SWIM248 3 "nonimmediate_operand" "rm")))
7164 (set (match_operand:SWIM248 1 "register_operand" "=d")
7165 (mod:SWIM248 (match_dup 2) (match_dup 3)))
7166 (use (match_operand:SWIM248 4 "register_operand" "1"))
7167 (clobber (reg:CC FLAGS_REG))]
7169 "idiv{<imodesuffix>}\t%3"
7170 [(set_attr "type" "idiv")
7171 (set_attr "mode" "<MODE>")])
7173 (define_expand "divmodqi4"
7174 [(parallel [(set (match_operand:QI 0 "register_operand" "")
7176 (match_operand:QI 1 "register_operand" "")
7177 (match_operand:QI 2 "nonimmediate_operand" "")))
7178 (set (match_operand:QI 3 "register_operand" "")
7179 (mod:QI (match_dup 1) (match_dup 2)))
7180 (clobber (reg:CC FLAGS_REG))])]
7181 "TARGET_QIMODE_MATH"
7186 tmp0 = gen_reg_rtx (HImode);
7187 tmp1 = gen_reg_rtx (HImode);
7189 /* Extend operands[1] to HImode. Generate 8bit divide. Result is
7191 emit_insn (gen_extendqihi2 (tmp1, operands[1]));
7192 emit_insn (gen_divmodhiqi3 (tmp0, tmp1, operands[2]));
7194 /* Extract remainder from AH. */
7195 tmp1 = gen_rtx_SIGN_EXTRACT (QImode, tmp0, GEN_INT (8), GEN_INT (8));
7196 insn = emit_move_insn (operands[3], tmp1);
7198 mod = gen_rtx_MOD (QImode, operands[1], operands[2]);
7199 set_unique_reg_note (insn, REG_EQUAL, mod);
7201 /* Extract quotient from AL. */
7202 insn = emit_move_insn (operands[0], gen_lowpart (QImode, tmp0));
7204 div = gen_rtx_DIV (QImode, operands[1], operands[2]);
7205 set_unique_reg_note (insn, REG_EQUAL, div);
7210 ;; Divide AX by r/m8, with result stored in
7213 ;; Change div/mod to HImode and extend the second argument to HImode
7214 ;; so that mode of div/mod matches with mode of arguments. Otherwise
7215 ;; combine may fail.
7216 (define_insn "divmodhiqi3"
7217 [(set (match_operand:HI 0 "register_operand" "=a")
7222 (mod:HI (match_operand:HI 1 "register_operand" "0")
7224 (match_operand:QI 2 "nonimmediate_operand" "qm")))))
7228 (div:HI (match_dup 1) (sign_extend:HI (match_dup 2)))))))
7229 (clobber (reg:CC FLAGS_REG))]
7230 "TARGET_QIMODE_MATH"
7232 [(set_attr "type" "idiv")
7233 (set_attr "mode" "QI")])
7235 (define_expand "udivmod<mode>4"
7236 [(parallel [(set (match_operand:SWIM248 0 "register_operand" "")
7238 (match_operand:SWIM248 1 "register_operand" "")
7239 (match_operand:SWIM248 2 "nonimmediate_operand" "")))
7240 (set (match_operand:SWIM248 3 "register_operand" "")
7241 (umod:SWIM248 (match_dup 1) (match_dup 2)))
7242 (clobber (reg:CC FLAGS_REG))])])
7244 ;; Split with 8bit unsigned divide:
7245 ;; if (dividend an divisor are in [0-255])
7246 ;; use 8bit unsigned integer divide
7248 ;; use original integer divide
7250 [(set (match_operand:SWI48 0 "register_operand" "")
7251 (udiv:SWI48 (match_operand:SWI48 2 "register_operand" "")
7252 (match_operand:SWI48 3 "nonimmediate_operand" "")))
7253 (set (match_operand:SWI48 1 "register_operand" "")
7254 (umod:SWI48 (match_dup 2) (match_dup 3)))
7255 (clobber (reg:CC FLAGS_REG))]
7256 "TARGET_USE_8BIT_IDIV
7257 && TARGET_QIMODE_MATH
7258 && can_create_pseudo_p ()
7259 && !optimize_insn_for_size_p ()"
7261 "ix86_split_idivmod (<MODE>mode, operands, false); DONE;")
7263 (define_insn_and_split "udivmod<mode>4_1"
7264 [(set (match_operand:SWI48 0 "register_operand" "=a")
7265 (udiv:SWI48 (match_operand:SWI48 2 "register_operand" "0")
7266 (match_operand:SWI48 3 "nonimmediate_operand" "rm")))
7267 (set (match_operand:SWI48 1 "register_operand" "=&d")
7268 (umod:SWI48 (match_dup 2) (match_dup 3)))
7269 (unspec [(const_int 0)] UNSPEC_DIV_ALREADY_SPLIT)
7270 (clobber (reg:CC FLAGS_REG))]
7274 [(set (match_dup 1) (const_int 0))
7275 (parallel [(set (match_dup 0)
7276 (udiv:SWI48 (match_dup 2) (match_dup 3)))
7278 (umod:SWI48 (match_dup 2) (match_dup 3)))
7280 (clobber (reg:CC FLAGS_REG))])]
7282 [(set_attr "type" "multi")
7283 (set_attr "mode" "<MODE>")])
7285 (define_insn_and_split "*udivmod<mode>4"
7286 [(set (match_operand:SWIM248 0 "register_operand" "=a")
7287 (udiv:SWIM248 (match_operand:SWIM248 2 "register_operand" "0")
7288 (match_operand:SWIM248 3 "nonimmediate_operand" "rm")))
7289 (set (match_operand:SWIM248 1 "register_operand" "=&d")
7290 (umod:SWIM248 (match_dup 2) (match_dup 3)))
7291 (clobber (reg:CC FLAGS_REG))]
7295 [(set (match_dup 1) (const_int 0))
7296 (parallel [(set (match_dup 0)
7297 (udiv:SWIM248 (match_dup 2) (match_dup 3)))
7299 (umod:SWIM248 (match_dup 2) (match_dup 3)))
7301 (clobber (reg:CC FLAGS_REG))])]
7303 [(set_attr "type" "multi")
7304 (set_attr "mode" "<MODE>")])
7306 (define_insn "*udivmod<mode>4_noext"
7307 [(set (match_operand:SWIM248 0 "register_operand" "=a")
7308 (udiv:SWIM248 (match_operand:SWIM248 2 "register_operand" "0")
7309 (match_operand:SWIM248 3 "nonimmediate_operand" "rm")))
7310 (set (match_operand:SWIM248 1 "register_operand" "=d")
7311 (umod:SWIM248 (match_dup 2) (match_dup 3)))
7312 (use (match_operand:SWIM248 4 "register_operand" "1"))
7313 (clobber (reg:CC FLAGS_REG))]
7315 "div{<imodesuffix>}\t%3"
7316 [(set_attr "type" "idiv")
7317 (set_attr "mode" "<MODE>")])
7319 (define_expand "udivmodqi4"
7320 [(parallel [(set (match_operand:QI 0 "register_operand" "")
7322 (match_operand:QI 1 "register_operand" "")
7323 (match_operand:QI 2 "nonimmediate_operand" "")))
7324 (set (match_operand:QI 3 "register_operand" "")
7325 (umod:QI (match_dup 1) (match_dup 2)))
7326 (clobber (reg:CC FLAGS_REG))])]
7327 "TARGET_QIMODE_MATH"
7332 tmp0 = gen_reg_rtx (HImode);
7333 tmp1 = gen_reg_rtx (HImode);
7335 /* Extend operands[1] to HImode. Generate 8bit divide. Result is
7337 emit_insn (gen_zero_extendqihi2 (tmp1, operands[1]));
7338 emit_insn (gen_udivmodhiqi3 (tmp0, tmp1, operands[2]));
7340 /* Extract remainder from AH. */
7341 tmp1 = gen_rtx_ZERO_EXTRACT (SImode, tmp0, GEN_INT (8), GEN_INT (8));
7342 tmp1 = simplify_gen_subreg (QImode, tmp1, SImode, 0);
7343 insn = emit_move_insn (operands[3], tmp1);
7345 mod = gen_rtx_UMOD (QImode, operands[1], operands[2]);
7346 set_unique_reg_note (insn, REG_EQUAL, mod);
7348 /* Extract quotient from AL. */
7349 insn = emit_move_insn (operands[0], gen_lowpart (QImode, tmp0));
7351 div = gen_rtx_UDIV (QImode, operands[1], operands[2]);
7352 set_unique_reg_note (insn, REG_EQUAL, div);
7357 (define_insn "udivmodhiqi3"
7358 [(set (match_operand:HI 0 "register_operand" "=a")
7363 (mod:HI (match_operand:HI 1 "register_operand" "0")
7365 (match_operand:QI 2 "nonimmediate_operand" "qm")))))
7369 (div:HI (match_dup 1) (zero_extend:HI (match_dup 2)))))))
7370 (clobber (reg:CC FLAGS_REG))]
7371 "TARGET_QIMODE_MATH"
7373 [(set_attr "type" "idiv")
7374 (set_attr "mode" "QI")])
7376 ;; We cannot use div/idiv for double division, because it causes
7377 ;; "division by zero" on the overflow and that's not what we expect
7378 ;; from truncate. Because true (non truncating) double division is
7379 ;; never generated, we can't create this insn anyway.
7382 ; [(set (match_operand:SI 0 "register_operand" "=a")
7384 ; (udiv:DI (match_operand:DI 1 "register_operand" "A")
7386 ; (match_operand:SI 2 "nonimmediate_operand" "rm")))))
7387 ; (set (match_operand:SI 3 "register_operand" "=d")
7389 ; (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))
7390 ; (clobber (reg:CC FLAGS_REG))]
7392 ; "div{l}\t{%2, %0|%0, %2}"
7393 ; [(set_attr "type" "idiv")])
7395 ;;- Logical AND instructions
7397 ;; On Pentium, "test imm, reg" is pairable only with eax, ax, and al.
7398 ;; Note that this excludes ah.
7400 (define_expand "testsi_ccno_1"
7401 [(set (reg:CCNO FLAGS_REG)
7403 (and:SI (match_operand:SI 0 "nonimmediate_operand" "")
7404 (match_operand:SI 1 "x86_64_nonmemory_operand" ""))
7407 (define_expand "testqi_ccz_1"
7408 [(set (reg:CCZ FLAGS_REG)
7409 (compare:CCZ (and:QI (match_operand:QI 0 "nonimmediate_operand" "")
7410 (match_operand:QI 1 "nonmemory_operand" ""))
7413 (define_expand "testdi_ccno_1"
7414 [(set (reg:CCNO FLAGS_REG)
7416 (and:DI (match_operand:DI 0 "nonimmediate_operand" "")
7417 (match_operand:DI 1 "x86_64_szext_general_operand" ""))
7419 "TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))")
7421 (define_insn "*testdi_1"
7422 [(set (reg FLAGS_REG)
7425 (match_operand:DI 0 "nonimmediate_operand" "%!*a,r,!*a,r,rm")
7426 (match_operand:DI 1 "x86_64_szext_general_operand" "Z,Z,e,e,re"))
7428 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
7429 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
7431 test{l}\t{%k1, %k0|%k0, %k1}
7432 test{l}\t{%k1, %k0|%k0, %k1}
7433 test{q}\t{%1, %0|%0, %1}
7434 test{q}\t{%1, %0|%0, %1}
7435 test{q}\t{%1, %0|%0, %1}"
7436 [(set_attr "type" "test")
7437 (set_attr "modrm" "0,1,0,1,1")
7438 (set_attr "mode" "SI,SI,DI,DI,DI")])
7440 (define_insn "*testqi_1_maybe_si"
7441 [(set (reg FLAGS_REG)
7444 (match_operand:QI 0 "nonimmediate_operand" "%!*a,q,qm,r")
7445 (match_operand:QI 1 "general_operand" "n,n,qn,n"))
7447 "!(MEM_P (operands[0]) && MEM_P (operands[1]))
7448 && ix86_match_ccmode (insn,
7449 CONST_INT_P (operands[1])
7450 && INTVAL (operands[1]) >= 0 ? CCNOmode : CCZmode)"
7452 if (which_alternative == 3)
7454 if (CONST_INT_P (operands[1]) && INTVAL (operands[1]) < 0)
7455 operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
7456 return "test{l}\t{%1, %k0|%k0, %1}";
7458 return "test{b}\t{%1, %0|%0, %1}";
7460 [(set_attr "type" "test")
7461 (set_attr "modrm" "0,1,1,1")
7462 (set_attr "mode" "QI,QI,QI,SI")
7463 (set_attr "pent_pair" "uv,np,uv,np")])
7465 (define_insn "*test<mode>_1"
7466 [(set (reg FLAGS_REG)
7469 (match_operand:SWI124 0 "nonimmediate_operand" "%!*a,<r>,<r>m")
7470 (match_operand:SWI124 1 "<general_operand>" "<i>,<i>,<r><i>"))
7472 "ix86_match_ccmode (insn, CCNOmode)
7473 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
7474 "test{<imodesuffix>}\t{%1, %0|%0, %1}"
7475 [(set_attr "type" "test")
7476 (set_attr "modrm" "0,1,1")
7477 (set_attr "mode" "<MODE>")
7478 (set_attr "pent_pair" "uv,np,uv")])
7480 (define_expand "testqi_ext_ccno_0"
7481 [(set (reg:CCNO FLAGS_REG)
7485 (match_operand 0 "ext_register_operand" "")
7488 (match_operand 1 "const_int_operand" ""))
7491 (define_insn "*testqi_ext_0"
7492 [(set (reg FLAGS_REG)
7496 (match_operand 0 "ext_register_operand" "Q")
7499 (match_operand 1 "const_int_operand" "n"))
7501 "ix86_match_ccmode (insn, CCNOmode)"
7502 "test{b}\t{%1, %h0|%h0, %1}"
7503 [(set_attr "type" "test")
7504 (set_attr "mode" "QI")
7505 (set_attr "length_immediate" "1")
7506 (set_attr "modrm" "1")
7507 (set_attr "pent_pair" "np")])
7509 (define_insn "*testqi_ext_1_rex64"
7510 [(set (reg FLAGS_REG)
7514 (match_operand 0 "ext_register_operand" "Q")
7518 (match_operand:QI 1 "register_operand" "Q")))
7520 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
7521 "test{b}\t{%1, %h0|%h0, %1}"
7522 [(set_attr "type" "test")
7523 (set_attr "mode" "QI")])
7525 (define_insn "*testqi_ext_1"
7526 [(set (reg FLAGS_REG)
7530 (match_operand 0 "ext_register_operand" "Q")
7534 (match_operand:QI 1 "general_operand" "Qm")))
7536 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
7537 "test{b}\t{%1, %h0|%h0, %1}"
7538 [(set_attr "type" "test")
7539 (set_attr "mode" "QI")])
7541 (define_insn "*testqi_ext_2"
7542 [(set (reg FLAGS_REG)
7546 (match_operand 0 "ext_register_operand" "Q")
7550 (match_operand 1 "ext_register_operand" "Q")
7554 "ix86_match_ccmode (insn, CCNOmode)"
7555 "test{b}\t{%h1, %h0|%h0, %h1}"
7556 [(set_attr "type" "test")
7557 (set_attr "mode" "QI")])
7559 (define_insn "*testqi_ext_3_rex64"
7560 [(set (reg FLAGS_REG)
7561 (compare (zero_extract:DI
7562 (match_operand 0 "nonimmediate_operand" "rm")
7563 (match_operand:DI 1 "const_int_operand" "")
7564 (match_operand:DI 2 "const_int_operand" ""))
7567 && ix86_match_ccmode (insn, CCNOmode)
7568 && INTVAL (operands[1]) > 0
7569 && INTVAL (operands[2]) >= 0
7570 /* Ensure that resulting mask is zero or sign extended operand. */
7571 && (INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
7572 || (INTVAL (operands[1]) + INTVAL (operands[2]) == 64
7573 && INTVAL (operands[1]) > 32))
7574 && (GET_MODE (operands[0]) == SImode
7575 || GET_MODE (operands[0]) == DImode
7576 || GET_MODE (operands[0]) == HImode
7577 || GET_MODE (operands[0]) == QImode)"
7580 ;; Combine likes to form bit extractions for some tests. Humor it.
7581 (define_insn "*testqi_ext_3"
7582 [(set (reg FLAGS_REG)
7583 (compare (zero_extract:SI
7584 (match_operand 0 "nonimmediate_operand" "rm")
7585 (match_operand:SI 1 "const_int_operand" "")
7586 (match_operand:SI 2 "const_int_operand" ""))
7588 "ix86_match_ccmode (insn, CCNOmode)
7589 && INTVAL (operands[1]) > 0
7590 && INTVAL (operands[2]) >= 0
7591 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
7592 && (GET_MODE (operands[0]) == SImode
7593 || (TARGET_64BIT && GET_MODE (operands[0]) == DImode)
7594 || GET_MODE (operands[0]) == HImode
7595 || GET_MODE (operands[0]) == QImode)"
7599 [(set (match_operand 0 "flags_reg_operand" "")
7600 (match_operator 1 "compare_operator"
7602 (match_operand 2 "nonimmediate_operand" "")
7603 (match_operand 3 "const_int_operand" "")
7604 (match_operand 4 "const_int_operand" ""))
7606 "ix86_match_ccmode (insn, CCNOmode)"
7607 [(set (match_dup 0) (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
7609 rtx val = operands[2];
7610 HOST_WIDE_INT len = INTVAL (operands[3]);
7611 HOST_WIDE_INT pos = INTVAL (operands[4]);
7613 enum machine_mode mode, submode;
7615 mode = GET_MODE (val);
7618 /* ??? Combine likes to put non-volatile mem extractions in QImode
7619 no matter the size of the test. So find a mode that works. */
7620 if (! MEM_VOLATILE_P (val))
7622 mode = smallest_mode_for_size (pos + len, MODE_INT);
7623 val = adjust_address (val, mode, 0);
7626 else if (GET_CODE (val) == SUBREG
7627 && (submode = GET_MODE (SUBREG_REG (val)),
7628 GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (submode))
7629 && pos + len <= GET_MODE_BITSIZE (submode)
7630 && GET_MODE_CLASS (submode) == MODE_INT)
7632 /* Narrow a paradoxical subreg to prevent partial register stalls. */
7634 val = SUBREG_REG (val);
7636 else if (mode == HImode && pos + len <= 8)
7638 /* Small HImode tests can be converted to QImode. */
7640 val = gen_lowpart (QImode, val);
7643 if (len == HOST_BITS_PER_WIDE_INT)
7646 mask = ((HOST_WIDE_INT)1 << len) - 1;
7649 operands[2] = gen_rtx_AND (mode, val, gen_int_mode (mask, mode));
7652 ;; Convert HImode/SImode test instructions with immediate to QImode ones.
7653 ;; i386 does not allow to encode test with 8bit sign extended immediate, so
7654 ;; this is relatively important trick.
7655 ;; Do the conversion only post-reload to avoid limiting of the register class
7658 [(set (match_operand 0 "flags_reg_operand" "")
7659 (match_operator 1 "compare_operator"
7660 [(and (match_operand 2 "register_operand" "")
7661 (match_operand 3 "const_int_operand" ""))
7664 && QI_REG_P (operands[2])
7665 && GET_MODE (operands[2]) != QImode
7666 && ((ix86_match_ccmode (insn, CCZmode)
7667 && !(INTVAL (operands[3]) & ~(255 << 8)))
7668 || (ix86_match_ccmode (insn, CCNOmode)
7669 && !(INTVAL (operands[3]) & ~(127 << 8))))"
7672 [(and:SI (zero_extract:SI (match_dup 2) (const_int 8) (const_int 8))
7676 operands[2] = gen_lowpart (SImode, operands[2]);
7677 operands[3] = gen_int_mode (INTVAL (operands[3]) >> 8, SImode);
7681 [(set (match_operand 0 "flags_reg_operand" "")
7682 (match_operator 1 "compare_operator"
7683 [(and (match_operand 2 "nonimmediate_operand" "")
7684 (match_operand 3 "const_int_operand" ""))
7687 && GET_MODE (operands[2]) != QImode
7688 && (!REG_P (operands[2]) || ANY_QI_REG_P (operands[2]))
7689 && ((ix86_match_ccmode (insn, CCZmode)
7690 && !(INTVAL (operands[3]) & ~255))
7691 || (ix86_match_ccmode (insn, CCNOmode)
7692 && !(INTVAL (operands[3]) & ~127)))"
7694 (match_op_dup 1 [(and:QI (match_dup 2) (match_dup 3))
7697 operands[2] = gen_lowpart (QImode, operands[2]);
7698 operands[3] = gen_lowpart (QImode, operands[3]);
7701 ;; %%% This used to optimize known byte-wide and operations to memory,
7702 ;; and sometimes to QImode registers. If this is considered useful,
7703 ;; it should be done with splitters.
7705 (define_expand "and<mode>3"
7706 [(set (match_operand:SWIM 0 "nonimmediate_operand" "")
7707 (and:SWIM (match_operand:SWIM 1 "nonimmediate_operand" "")
7708 (match_operand:SWIM 2 "<general_szext_operand>" "")))]
7711 if (<MODE>mode == DImode
7712 && GET_CODE (operands[2]) == CONST_INT
7713 && INTVAL (operands[2]) == (HOST_WIDE_INT) 0xffffffff
7714 && REG_P (operands[1]))
7715 emit_insn (gen_zero_extendsidi2 (operands[0],
7716 gen_lowpart (SImode, operands[1])));
7718 ix86_expand_binary_operator (AND, <MODE>mode, operands);
7722 (define_insn "*anddi_1"
7723 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r")
7725 (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,qm")
7726 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,rm,L")))
7727 (clobber (reg:CC FLAGS_REG))]
7728 "TARGET_64BIT && ix86_binary_operator_ok (AND, DImode, operands)"
7730 switch (get_attr_type (insn))
7734 enum machine_mode mode;
7736 gcc_assert (CONST_INT_P (operands[2]));
7737 if (INTVAL (operands[2]) == (HOST_WIDE_INT) 0xffffffff)
7739 else if (INTVAL (operands[2]) == 0xffff)
7743 gcc_assert (INTVAL (operands[2]) == 0xff);
7747 operands[1] = gen_lowpart (mode, operands[1]);
7749 return "mov{l}\t{%1, %k0|%k0, %1}";
7750 else if (mode == HImode)
7751 return "movz{wl|x}\t{%1, %k0|%k0, %1}";
7753 return "movz{bl|x}\t{%1, %k0|%k0, %1}";
7757 gcc_assert (rtx_equal_p (operands[0], operands[1]));
7758 if (get_attr_mode (insn) == MODE_SI)
7759 return "and{l}\t{%k2, %k0|%k0, %k2}";
7761 return "and{q}\t{%2, %0|%0, %2}";
7764 [(set_attr "type" "alu,alu,alu,imovx")
7765 (set_attr "length_immediate" "*,*,*,0")
7766 (set (attr "prefix_rex")
7768 (and (eq_attr "type" "imovx")
7769 (and (match_test "INTVAL (operands[2]) == 0xff")
7770 (match_operand 1 "ext_QIreg_operand" "")))
7772 (const_string "*")))
7773 (set_attr "mode" "SI,DI,DI,SI")])
7775 (define_insn "*andsi_1"
7776 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,r")
7777 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,qm")
7778 (match_operand:SI 2 "x86_64_general_operand" "re,rm,L")))
7779 (clobber (reg:CC FLAGS_REG))]
7780 "ix86_binary_operator_ok (AND, SImode, operands)"
7782 switch (get_attr_type (insn))
7786 enum machine_mode mode;
7788 gcc_assert (CONST_INT_P (operands[2]));
7789 if (INTVAL (operands[2]) == 0xffff)
7793 gcc_assert (INTVAL (operands[2]) == 0xff);
7797 operands[1] = gen_lowpart (mode, operands[1]);
7799 return "movz{wl|x}\t{%1, %0|%0, %1}";
7801 return "movz{bl|x}\t{%1, %0|%0, %1}";
7805 gcc_assert (rtx_equal_p (operands[0], operands[1]));
7806 return "and{l}\t{%2, %0|%0, %2}";
7809 [(set_attr "type" "alu,alu,imovx")
7810 (set (attr "prefix_rex")
7812 (and (eq_attr "type" "imovx")
7813 (and (match_test "INTVAL (operands[2]) == 0xff")
7814 (match_operand 1 "ext_QIreg_operand" "")))
7816 (const_string "*")))
7817 (set_attr "length_immediate" "*,*,0")
7818 (set_attr "mode" "SI")])
7820 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
7821 (define_insn "*andsi_1_zext"
7822 [(set (match_operand:DI 0 "register_operand" "=r")
7824 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
7825 (match_operand:SI 2 "x86_64_general_operand" "rme"))))
7826 (clobber (reg:CC FLAGS_REG))]
7827 "TARGET_64BIT && ix86_binary_operator_ok (AND, SImode, operands)"
7828 "and{l}\t{%2, %k0|%k0, %2}"
7829 [(set_attr "type" "alu")
7830 (set_attr "mode" "SI")])
7832 (define_insn "*andhi_1"
7833 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
7834 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,qm")
7835 (match_operand:HI 2 "general_operand" "rn,rm,L")))
7836 (clobber (reg:CC FLAGS_REG))]
7837 "ix86_binary_operator_ok (AND, HImode, operands)"
7839 switch (get_attr_type (insn))
7842 gcc_assert (CONST_INT_P (operands[2]));
7843 gcc_assert (INTVAL (operands[2]) == 0xff);
7844 return "movz{bl|x}\t{%b1, %k0|%k0, %b1}";
7847 gcc_assert (rtx_equal_p (operands[0], operands[1]));
7849 return "and{w}\t{%2, %0|%0, %2}";
7852 [(set_attr "type" "alu,alu,imovx")
7853 (set_attr "length_immediate" "*,*,0")
7854 (set (attr "prefix_rex")
7856 (and (eq_attr "type" "imovx")
7857 (match_operand 1 "ext_QIreg_operand" ""))
7859 (const_string "*")))
7860 (set_attr "mode" "HI,HI,SI")])
7862 ;; %%% Potential partial reg stall on alternative 2. What to do?
7863 (define_insn "*andqi_1"
7864 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
7865 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
7866 (match_operand:QI 2 "general_operand" "qn,qmn,rn")))
7867 (clobber (reg:CC FLAGS_REG))]
7868 "ix86_binary_operator_ok (AND, QImode, operands)"
7870 and{b}\t{%2, %0|%0, %2}
7871 and{b}\t{%2, %0|%0, %2}
7872 and{l}\t{%k2, %k0|%k0, %k2}"
7873 [(set_attr "type" "alu")
7874 (set_attr "mode" "QI,QI,SI")])
7876 (define_insn "*andqi_1_slp"
7877 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
7878 (and:QI (match_dup 0)
7879 (match_operand:QI 1 "general_operand" "qn,qmn")))
7880 (clobber (reg:CC FLAGS_REG))]
7881 "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
7882 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
7883 "and{b}\t{%1, %0|%0, %1}"
7884 [(set_attr "type" "alu1")
7885 (set_attr "mode" "QI")])
7888 [(set (match_operand 0 "register_operand" "")
7890 (const_int -65536)))
7891 (clobber (reg:CC FLAGS_REG))]
7892 "(TARGET_FAST_PREFIX && !TARGET_PARTIAL_REG_STALL)
7893 || optimize_function_for_size_p (cfun)"
7894 [(set (strict_low_part (match_dup 1)) (const_int 0))]
7895 "operands[1] = gen_lowpart (HImode, operands[0]);")
7898 [(set (match_operand 0 "ext_register_operand" "")
7901 (clobber (reg:CC FLAGS_REG))]
7902 "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
7903 && reload_completed"
7904 [(set (strict_low_part (match_dup 1)) (const_int 0))]
7905 "operands[1] = gen_lowpart (QImode, operands[0]);")
7908 [(set (match_operand 0 "ext_register_operand" "")
7910 (const_int -65281)))
7911 (clobber (reg:CC FLAGS_REG))]
7912 "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
7913 && reload_completed"
7914 [(parallel [(set (zero_extract:SI (match_dup 0)
7918 (zero_extract:SI (match_dup 0)
7921 (zero_extract:SI (match_dup 0)
7924 (clobber (reg:CC FLAGS_REG))])]
7925 "operands[0] = gen_lowpart (SImode, operands[0]);")
7927 (define_insn "*anddi_2"
7928 [(set (reg FLAGS_REG)
7931 (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
7932 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,rem,re"))
7934 (set (match_operand:DI 0 "nonimmediate_operand" "=r,r,rm")
7935 (and:DI (match_dup 1) (match_dup 2)))]
7936 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
7937 && ix86_binary_operator_ok (AND, DImode, operands)"
7939 and{l}\t{%k2, %k0|%k0, %k2}
7940 and{q}\t{%2, %0|%0, %2}
7941 and{q}\t{%2, %0|%0, %2}"
7942 [(set_attr "type" "alu")
7943 (set_attr "mode" "SI,DI,DI")])
7945 (define_insn "*andqi_2_maybe_si"
7946 [(set (reg FLAGS_REG)
7948 (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
7949 (match_operand:QI 2 "general_operand" "qmn,qn,n"))
7951 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm,*r")
7952 (and:QI (match_dup 1) (match_dup 2)))]
7953 "ix86_binary_operator_ok (AND, QImode, operands)
7954 && ix86_match_ccmode (insn,
7955 CONST_INT_P (operands[2])
7956 && INTVAL (operands[2]) >= 0 ? CCNOmode : CCZmode)"
7958 if (which_alternative == 2)
7960 if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 0)
7961 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
7962 return "and{l}\t{%2, %k0|%k0, %2}";
7964 return "and{b}\t{%2, %0|%0, %2}";
7966 [(set_attr "type" "alu")
7967 (set_attr "mode" "QI,QI,SI")])
7969 (define_insn "*and<mode>_2"
7970 [(set (reg FLAGS_REG)
7971 (compare (and:SWI124
7972 (match_operand:SWI124 1 "nonimmediate_operand" "%0,0")
7973 (match_operand:SWI124 2 "<general_operand>" "<g>,<r><i>"))
7975 (set (match_operand:SWI124 0 "nonimmediate_operand" "=<r>,<r>m")
7976 (and:SWI124 (match_dup 1) (match_dup 2)))]
7977 "ix86_match_ccmode (insn, CCNOmode)
7978 && ix86_binary_operator_ok (AND, <MODE>mode, operands)"
7979 "and{<imodesuffix>}\t{%2, %0|%0, %2}"
7980 [(set_attr "type" "alu")
7981 (set_attr "mode" "<MODE>")])
7983 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
7984 (define_insn "*andsi_2_zext"
7985 [(set (reg FLAGS_REG)
7987 (match_operand:SI 1 "nonimmediate_operand" "%0")
7988 (match_operand:SI 2 "x86_64_general_operand" "rme"))
7990 (set (match_operand:DI 0 "register_operand" "=r")
7991 (zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))]
7992 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
7993 && ix86_binary_operator_ok (AND, SImode, operands)"
7994 "and{l}\t{%2, %k0|%k0, %2}"
7995 [(set_attr "type" "alu")
7996 (set_attr "mode" "SI")])
7998 (define_insn "*andqi_2_slp"
7999 [(set (reg FLAGS_REG)
8001 (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8002 (match_operand:QI 1 "nonimmediate_operand" "qmn,qn"))
8004 (set (strict_low_part (match_dup 0))
8005 (and:QI (match_dup 0) (match_dup 1)))]
8006 "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
8007 && ix86_match_ccmode (insn, CCNOmode)
8008 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
8009 "and{b}\t{%1, %0|%0, %1}"
8010 [(set_attr "type" "alu1")
8011 (set_attr "mode" "QI")])
8013 ;; ??? A bug in recog prevents it from recognizing a const_int as an
8014 ;; operand to zero_extend in andqi_ext_1. It was checking explicitly
8015 ;; for a QImode operand, which of course failed.
8016 (define_insn "andqi_ext_0"
8017 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8022 (match_operand 1 "ext_register_operand" "0")
8025 (match_operand 2 "const_int_operand" "n")))
8026 (clobber (reg:CC FLAGS_REG))]
8028 "and{b}\t{%2, %h0|%h0, %2}"
8029 [(set_attr "type" "alu")
8030 (set_attr "length_immediate" "1")
8031 (set_attr "modrm" "1")
8032 (set_attr "mode" "QI")])
8034 ;; Generated by peephole translating test to and. This shows up
8035 ;; often in fp comparisons.
8036 (define_insn "*andqi_ext_0_cc"
8037 [(set (reg FLAGS_REG)
8041 (match_operand 1 "ext_register_operand" "0")
8044 (match_operand 2 "const_int_operand" "n"))
8046 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8055 "ix86_match_ccmode (insn, CCNOmode)"
8056 "and{b}\t{%2, %h0|%h0, %2}"
8057 [(set_attr "type" "alu")
8058 (set_attr "length_immediate" "1")
8059 (set_attr "modrm" "1")
8060 (set_attr "mode" "QI")])
8062 (define_insn "*andqi_ext_1_rex64"
8063 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8068 (match_operand 1 "ext_register_operand" "0")
8072 (match_operand 2 "ext_register_operand" "Q"))))
8073 (clobber (reg:CC FLAGS_REG))]
8075 "and{b}\t{%2, %h0|%h0, %2}"
8076 [(set_attr "type" "alu")
8077 (set_attr "length_immediate" "0")
8078 (set_attr "mode" "QI")])
8080 (define_insn "*andqi_ext_1"
8081 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8086 (match_operand 1 "ext_register_operand" "0")
8090 (match_operand:QI 2 "general_operand" "Qm"))))
8091 (clobber (reg:CC FLAGS_REG))]
8093 "and{b}\t{%2, %h0|%h0, %2}"
8094 [(set_attr "type" "alu")
8095 (set_attr "length_immediate" "0")
8096 (set_attr "mode" "QI")])
8098 (define_insn "*andqi_ext_2"
8099 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8104 (match_operand 1 "ext_register_operand" "%0")
8108 (match_operand 2 "ext_register_operand" "Q")
8111 (clobber (reg:CC FLAGS_REG))]
8113 "and{b}\t{%h2, %h0|%h0, %h2}"
8114 [(set_attr "type" "alu")
8115 (set_attr "length_immediate" "0")
8116 (set_attr "mode" "QI")])
8118 ;; Convert wide AND instructions with immediate operand to shorter QImode
8119 ;; equivalents when possible.
8120 ;; Don't do the splitting with memory operands, since it introduces risk
8121 ;; of memory mismatch stalls. We may want to do the splitting for optimizing
8122 ;; for size, but that can (should?) be handled by generic code instead.
8124 [(set (match_operand 0 "register_operand" "")
8125 (and (match_operand 1 "register_operand" "")
8126 (match_operand 2 "const_int_operand" "")))
8127 (clobber (reg:CC FLAGS_REG))]
8129 && QI_REG_P (operands[0])
8130 && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
8131 && !(~INTVAL (operands[2]) & ~(255 << 8))
8132 && GET_MODE (operands[0]) != QImode"
8133 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
8134 (and:SI (zero_extract:SI (match_dup 1)
8135 (const_int 8) (const_int 8))
8137 (clobber (reg:CC FLAGS_REG))])]
8139 operands[0] = gen_lowpart (SImode, operands[0]);
8140 operands[1] = gen_lowpart (SImode, operands[1]);
8141 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);
8144 ;; Since AND can be encoded with sign extended immediate, this is only
8145 ;; profitable when 7th bit is not set.
8147 [(set (match_operand 0 "register_operand" "")
8148 (and (match_operand 1 "general_operand" "")
8149 (match_operand 2 "const_int_operand" "")))
8150 (clobber (reg:CC FLAGS_REG))]
8152 && ANY_QI_REG_P (operands[0])
8153 && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
8154 && !(~INTVAL (operands[2]) & ~255)
8155 && !(INTVAL (operands[2]) & 128)
8156 && GET_MODE (operands[0]) != QImode"
8157 [(parallel [(set (strict_low_part (match_dup 0))
8158 (and:QI (match_dup 1)
8160 (clobber (reg:CC FLAGS_REG))])]
8162 operands[0] = gen_lowpart (QImode, operands[0]);
8163 operands[1] = gen_lowpart (QImode, operands[1]);
8164 operands[2] = gen_lowpart (QImode, operands[2]);
8167 ;; Logical inclusive and exclusive OR instructions
8169 ;; %%% This used to optimize known byte-wide and operations to memory.
8170 ;; If this is considered useful, it should be done with splitters.
8172 (define_expand "<code><mode>3"
8173 [(set (match_operand:SWIM 0 "nonimmediate_operand" "")
8174 (any_or:SWIM (match_operand:SWIM 1 "nonimmediate_operand" "")
8175 (match_operand:SWIM 2 "<general_operand>" "")))]
8177 "ix86_expand_binary_operator (<CODE>, <MODE>mode, operands); DONE;")
8179 (define_insn "*<code><mode>_1"
8180 [(set (match_operand:SWI248 0 "nonimmediate_operand" "=r,rm")
8182 (match_operand:SWI248 1 "nonimmediate_operand" "%0,0")
8183 (match_operand:SWI248 2 "<general_operand>" "<g>,r<i>")))
8184 (clobber (reg:CC FLAGS_REG))]
8185 "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
8186 "<logic>{<imodesuffix>}\t{%2, %0|%0, %2}"
8187 [(set_attr "type" "alu")
8188 (set_attr "mode" "<MODE>")])
8190 ;; %%% Potential partial reg stall on alternative 2. What to do?
8191 (define_insn "*<code>qi_1"
8192 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
8193 (any_or:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8194 (match_operand:QI 2 "general_operand" "qmn,qn,rn")))
8195 (clobber (reg:CC FLAGS_REG))]
8196 "ix86_binary_operator_ok (<CODE>, QImode, operands)"
8198 <logic>{b}\t{%2, %0|%0, %2}
8199 <logic>{b}\t{%2, %0|%0, %2}
8200 <logic>{l}\t{%k2, %k0|%k0, %k2}"
8201 [(set_attr "type" "alu")
8202 (set_attr "mode" "QI,QI,SI")])
8204 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8205 (define_insn "*<code>si_1_zext"
8206 [(set (match_operand:DI 0 "register_operand" "=r")
8208 (any_or:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8209 (match_operand:SI 2 "x86_64_general_operand" "rme"))))
8210 (clobber (reg:CC FLAGS_REG))]
8211 "TARGET_64BIT && ix86_binary_operator_ok (<CODE>, SImode, operands)"
8212 "<logic>{l}\t{%2, %k0|%k0, %2}"
8213 [(set_attr "type" "alu")
8214 (set_attr "mode" "SI")])
8216 (define_insn "*<code>si_1_zext_imm"
8217 [(set (match_operand:DI 0 "register_operand" "=r")
8219 (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
8220 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
8221 (clobber (reg:CC FLAGS_REG))]
8222 "TARGET_64BIT && ix86_binary_operator_ok (<CODE>, SImode, operands)"
8223 "<logic>{l}\t{%2, %k0|%k0, %2}"
8224 [(set_attr "type" "alu")
8225 (set_attr "mode" "SI")])
8227 (define_insn "*<code>qi_1_slp"
8228 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+q,m"))
8229 (any_or:QI (match_dup 0)
8230 (match_operand:QI 1 "general_operand" "qmn,qn")))
8231 (clobber (reg:CC FLAGS_REG))]
8232 "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
8233 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
8234 "<logic>{b}\t{%1, %0|%0, %1}"
8235 [(set_attr "type" "alu1")
8236 (set_attr "mode" "QI")])
8238 (define_insn "*<code><mode>_2"
8239 [(set (reg FLAGS_REG)
8240 (compare (any_or:SWI
8241 (match_operand:SWI 1 "nonimmediate_operand" "%0,0")
8242 (match_operand:SWI 2 "<general_operand>" "<g>,<r><i>"))
8244 (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>,<r>m")
8245 (any_or:SWI (match_dup 1) (match_dup 2)))]
8246 "ix86_match_ccmode (insn, CCNOmode)
8247 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
8248 "<logic>{<imodesuffix>}\t{%2, %0|%0, %2}"
8249 [(set_attr "type" "alu")
8250 (set_attr "mode" "<MODE>")])
8252 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8253 ;; ??? Special case for immediate operand is missing - it is tricky.
8254 (define_insn "*<code>si_2_zext"
8255 [(set (reg FLAGS_REG)
8256 (compare (any_or:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8257 (match_operand:SI 2 "x86_64_general_operand" "rme"))
8259 (set (match_operand:DI 0 "register_operand" "=r")
8260 (zero_extend:DI (any_or:SI (match_dup 1) (match_dup 2))))]
8261 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8262 && ix86_binary_operator_ok (<CODE>, SImode, operands)"
8263 "<logic>{l}\t{%2, %k0|%k0, %2}"
8264 [(set_attr "type" "alu")
8265 (set_attr "mode" "SI")])
8267 (define_insn "*<code>si_2_zext_imm"
8268 [(set (reg FLAGS_REG)
8270 (match_operand:SI 1 "nonimmediate_operand" "%0")
8271 (match_operand:SI 2 "x86_64_zext_immediate_operand" "Z"))
8273 (set (match_operand:DI 0 "register_operand" "=r")
8274 (any_or:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
8275 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8276 && ix86_binary_operator_ok (<CODE>, SImode, operands)"
8277 "<logic>{l}\t{%2, %k0|%k0, %2}"
8278 [(set_attr "type" "alu")
8279 (set_attr "mode" "SI")])
8281 (define_insn "*<code>qi_2_slp"
8282 [(set (reg FLAGS_REG)
8283 (compare (any_or:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8284 (match_operand:QI 1 "general_operand" "qmn,qn"))
8286 (set (strict_low_part (match_dup 0))
8287 (any_or:QI (match_dup 0) (match_dup 1)))]
8288 "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
8289 && ix86_match_ccmode (insn, CCNOmode)
8290 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
8291 "<logic>{b}\t{%1, %0|%0, %1}"
8292 [(set_attr "type" "alu1")
8293 (set_attr "mode" "QI")])
8295 (define_insn "*<code><mode>_3"
8296 [(set (reg FLAGS_REG)
8297 (compare (any_or:SWI
8298 (match_operand:SWI 1 "nonimmediate_operand" "%0")
8299 (match_operand:SWI 2 "<general_operand>" "<g>"))
8301 (clobber (match_scratch:SWI 0 "=<r>"))]
8302 "ix86_match_ccmode (insn, CCNOmode)
8303 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
8304 "<logic>{<imodesuffix>}\t{%2, %0|%0, %2}"
8305 [(set_attr "type" "alu")
8306 (set_attr "mode" "<MODE>")])
8308 (define_insn "*<code>qi_ext_0"
8309 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8314 (match_operand 1 "ext_register_operand" "0")
8317 (match_operand 2 "const_int_operand" "n")))
8318 (clobber (reg:CC FLAGS_REG))]
8319 "!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)"
8320 "<logic>{b}\t{%2, %h0|%h0, %2}"
8321 [(set_attr "type" "alu")
8322 (set_attr "length_immediate" "1")
8323 (set_attr "modrm" "1")
8324 (set_attr "mode" "QI")])
8326 (define_insn "*<code>qi_ext_1_rex64"
8327 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8332 (match_operand 1 "ext_register_operand" "0")
8336 (match_operand 2 "ext_register_operand" "Q"))))
8337 (clobber (reg:CC FLAGS_REG))]
8339 && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))"
8340 "<logic>{b}\t{%2, %h0|%h0, %2}"
8341 [(set_attr "type" "alu")
8342 (set_attr "length_immediate" "0")
8343 (set_attr "mode" "QI")])
8345 (define_insn "*<code>qi_ext_1"
8346 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8351 (match_operand 1 "ext_register_operand" "0")
8355 (match_operand:QI 2 "general_operand" "Qm"))))
8356 (clobber (reg:CC FLAGS_REG))]
8358 && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))"
8359 "<logic>{b}\t{%2, %h0|%h0, %2}"
8360 [(set_attr "type" "alu")
8361 (set_attr "length_immediate" "0")
8362 (set_attr "mode" "QI")])
8364 (define_insn "*<code>qi_ext_2"
8365 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8369 (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
8372 (zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
8375 (clobber (reg:CC FLAGS_REG))]
8376 "!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)"
8377 "<logic>{b}\t{%h2, %h0|%h0, %h2}"
8378 [(set_attr "type" "alu")
8379 (set_attr "length_immediate" "0")
8380 (set_attr "mode" "QI")])
8383 [(set (match_operand 0 "register_operand" "")
8384 (any_or (match_operand 1 "register_operand" "")
8385 (match_operand 2 "const_int_operand" "")))
8386 (clobber (reg:CC FLAGS_REG))]
8388 && QI_REG_P (operands[0])
8389 && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
8390 && !(INTVAL (operands[2]) & ~(255 << 8))
8391 && GET_MODE (operands[0]) != QImode"
8392 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
8393 (any_or:SI (zero_extract:SI (match_dup 1)
8394 (const_int 8) (const_int 8))
8396 (clobber (reg:CC FLAGS_REG))])]
8398 operands[0] = gen_lowpart (SImode, operands[0]);
8399 operands[1] = gen_lowpart (SImode, operands[1]);
8400 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);
8403 ;; Since OR can be encoded with sign extended immediate, this is only
8404 ;; profitable when 7th bit is set.
8406 [(set (match_operand 0 "register_operand" "")
8407 (any_or (match_operand 1 "general_operand" "")
8408 (match_operand 2 "const_int_operand" "")))
8409 (clobber (reg:CC FLAGS_REG))]
8411 && ANY_QI_REG_P (operands[0])
8412 && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
8413 && !(INTVAL (operands[2]) & ~255)
8414 && (INTVAL (operands[2]) & 128)
8415 && GET_MODE (operands[0]) != QImode"
8416 [(parallel [(set (strict_low_part (match_dup 0))
8417 (any_or:QI (match_dup 1)
8419 (clobber (reg:CC FLAGS_REG))])]
8421 operands[0] = gen_lowpart (QImode, operands[0]);
8422 operands[1] = gen_lowpart (QImode, operands[1]);
8423 operands[2] = gen_lowpart (QImode, operands[2]);
8426 (define_expand "xorqi_cc_ext_1"
8428 (set (reg:CCNO FLAGS_REG)
8432 (match_operand 1 "ext_register_operand" "")
8435 (match_operand:QI 2 "general_operand" ""))
8437 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
8447 (define_insn "*xorqi_cc_ext_1_rex64"
8448 [(set (reg FLAGS_REG)
8452 (match_operand 1 "ext_register_operand" "0")
8455 (match_operand:QI 2 "nonmemory_operand" "Qn"))
8457 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8466 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
8467 "xor{b}\t{%2, %h0|%h0, %2}"
8468 [(set_attr "type" "alu")
8469 (set_attr "modrm" "1")
8470 (set_attr "mode" "QI")])
8472 (define_insn "*xorqi_cc_ext_1"
8473 [(set (reg FLAGS_REG)
8477 (match_operand 1 "ext_register_operand" "0")
8480 (match_operand:QI 2 "general_operand" "qmn"))
8482 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
8491 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
8492 "xor{b}\t{%2, %h0|%h0, %2}"
8493 [(set_attr "type" "alu")
8494 (set_attr "modrm" "1")
8495 (set_attr "mode" "QI")])
8497 ;; Negation instructions
8499 (define_expand "neg<mode>2"
8500 [(set (match_operand:SDWIM 0 "nonimmediate_operand" "")
8501 (neg:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand" "")))]
8503 "ix86_expand_unary_operator (NEG, <MODE>mode, operands); DONE;")
8505 (define_insn_and_split "*neg<dwi>2_doubleword"
8506 [(set (match_operand:<DWI> 0 "nonimmediate_operand" "=ro")
8507 (neg:<DWI> (match_operand:<DWI> 1 "nonimmediate_operand" "0")))
8508 (clobber (reg:CC FLAGS_REG))]
8509 "ix86_unary_operator_ok (NEG, <DWI>mode, operands)"
8513 [(set (reg:CCZ FLAGS_REG)
8514 (compare:CCZ (neg:DWIH (match_dup 1)) (const_int 0)))
8515 (set (match_dup 0) (neg:DWIH (match_dup 1)))])
8518 (plus:DWIH (match_dup 3)
8519 (plus:DWIH (ltu:DWIH (reg:CC FLAGS_REG) (const_int 0))
8521 (clobber (reg:CC FLAGS_REG))])
8524 (neg:DWIH (match_dup 2)))
8525 (clobber (reg:CC FLAGS_REG))])]
8526 "split_double_mode (<DWI>mode, &operands[0], 2, &operands[0], &operands[2]);")
8528 (define_insn "*neg<mode>2_1"
8529 [(set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m")
8530 (neg:SWI (match_operand:SWI 1 "nonimmediate_operand" "0")))
8531 (clobber (reg:CC FLAGS_REG))]
8532 "ix86_unary_operator_ok (NEG, <MODE>mode, operands)"
8533 "neg{<imodesuffix>}\t%0"
8534 [(set_attr "type" "negnot")
8535 (set_attr "mode" "<MODE>")])
8537 ;; Combine is quite creative about this pattern.
8538 (define_insn "*negsi2_1_zext"
8539 [(set (match_operand:DI 0 "register_operand" "=r")
8541 (neg:DI (ashift:DI (match_operand:DI 1 "register_operand" "0")
8544 (clobber (reg:CC FLAGS_REG))]
8545 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
8547 [(set_attr "type" "negnot")
8548 (set_attr "mode" "SI")])
8550 ;; The problem with neg is that it does not perform (compare x 0),
8551 ;; it really performs (compare 0 x), which leaves us with the zero
8552 ;; flag being the only useful item.
8554 (define_insn "*neg<mode>2_cmpz"
8555 [(set (reg:CCZ FLAGS_REG)
8557 (neg:SWI (match_operand:SWI 1 "nonimmediate_operand" "0"))
8559 (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m")
8560 (neg:SWI (match_dup 1)))]
8561 "ix86_unary_operator_ok (NEG, <MODE>mode, operands)"
8562 "neg{<imodesuffix>}\t%0"
8563 [(set_attr "type" "negnot")
8564 (set_attr "mode" "<MODE>")])
8566 (define_insn "*negsi2_cmpz_zext"
8567 [(set (reg:CCZ FLAGS_REG)
8571 (match_operand:DI 1 "register_operand" "0")
8575 (set (match_operand:DI 0 "register_operand" "=r")
8576 (lshiftrt:DI (neg:DI (ashift:DI (match_dup 1)
8579 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
8581 [(set_attr "type" "negnot")
8582 (set_attr "mode" "SI")])
8584 ;; Changing of sign for FP values is doable using integer unit too.
8586 (define_expand "<code><mode>2"
8587 [(set (match_operand:X87MODEF 0 "register_operand" "")
8588 (absneg:X87MODEF (match_operand:X87MODEF 1 "register_operand" "")))]
8589 "TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
8590 "ix86_expand_fp_absneg_operator (<CODE>, <MODE>mode, operands); DONE;")
8592 (define_insn "*absneg<mode>2_mixed"
8593 [(set (match_operand:MODEF 0 "register_operand" "=x,x,f,!r")
8594 (match_operator:MODEF 3 "absneg_operator"
8595 [(match_operand:MODEF 1 "register_operand" "0,x,0,0")]))
8596 (use (match_operand:<ssevecmode> 2 "nonimmediate_operand" "xm,0,X,X"))
8597 (clobber (reg:CC FLAGS_REG))]
8598 "TARGET_MIX_SSE_I387 && SSE_FLOAT_MODE_P (<MODE>mode)"
8601 (define_insn "*absneg<mode>2_sse"
8602 [(set (match_operand:MODEF 0 "register_operand" "=x,x,!r")
8603 (match_operator:MODEF 3 "absneg_operator"
8604 [(match_operand:MODEF 1 "register_operand" "0 ,x,0")]))
8605 (use (match_operand:<ssevecmode> 2 "register_operand" "xm,0,X"))
8606 (clobber (reg:CC FLAGS_REG))]
8607 "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
8610 (define_insn "*absneg<mode>2_i387"
8611 [(set (match_operand:X87MODEF 0 "register_operand" "=f,!r")
8612 (match_operator:X87MODEF 3 "absneg_operator"
8613 [(match_operand:X87MODEF 1 "register_operand" "0,0")]))
8614 (use (match_operand 2 "" ""))
8615 (clobber (reg:CC FLAGS_REG))]
8616 "TARGET_80387 && !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
8619 (define_expand "<code>tf2"
8620 [(set (match_operand:TF 0 "register_operand" "")
8621 (absneg:TF (match_operand:TF 1 "register_operand" "")))]
8623 "ix86_expand_fp_absneg_operator (<CODE>, TFmode, operands); DONE;")
8625 (define_insn "*absnegtf2_sse"
8626 [(set (match_operand:TF 0 "register_operand" "=x,x")
8627 (match_operator:TF 3 "absneg_operator"
8628 [(match_operand:TF 1 "register_operand" "0,x")]))
8629 (use (match_operand:TF 2 "nonimmediate_operand" "xm,0"))
8630 (clobber (reg:CC FLAGS_REG))]
8634 ;; Splitters for fp abs and neg.
8637 [(set (match_operand 0 "fp_register_operand" "")
8638 (match_operator 1 "absneg_operator" [(match_dup 0)]))
8639 (use (match_operand 2 "" ""))
8640 (clobber (reg:CC FLAGS_REG))]
8642 [(set (match_dup 0) (match_op_dup 1 [(match_dup 0)]))])
8645 [(set (match_operand 0 "register_operand" "")
8646 (match_operator 3 "absneg_operator"
8647 [(match_operand 1 "register_operand" "")]))
8648 (use (match_operand 2 "nonimmediate_operand" ""))
8649 (clobber (reg:CC FLAGS_REG))]
8650 "reload_completed && SSE_REG_P (operands[0])"
8651 [(set (match_dup 0) (match_dup 3))]
8653 enum machine_mode mode = GET_MODE (operands[0]);
8654 enum machine_mode vmode = GET_MODE (operands[2]);
8657 operands[0] = simplify_gen_subreg (vmode, operands[0], mode, 0);
8658 operands[1] = simplify_gen_subreg (vmode, operands[1], mode, 0);
8659 if (operands_match_p (operands[0], operands[2]))
8662 operands[1] = operands[2];
8665 if (GET_CODE (operands[3]) == ABS)
8666 tmp = gen_rtx_AND (vmode, operands[1], operands[2]);
8668 tmp = gen_rtx_XOR (vmode, operands[1], operands[2]);
8673 [(set (match_operand:SF 0 "register_operand" "")
8674 (match_operator:SF 1 "absneg_operator" [(match_dup 0)]))
8675 (use (match_operand:V4SF 2 "" ""))
8676 (clobber (reg:CC FLAGS_REG))]
8678 [(parallel [(set (match_dup 0) (match_dup 1))
8679 (clobber (reg:CC FLAGS_REG))])]
8682 operands[0] = gen_lowpart (SImode, operands[0]);
8683 if (GET_CODE (operands[1]) == ABS)
8685 tmp = gen_int_mode (0x7fffffff, SImode);
8686 tmp = gen_rtx_AND (SImode, operands[0], tmp);
8690 tmp = gen_int_mode (0x80000000, SImode);
8691 tmp = gen_rtx_XOR (SImode, operands[0], tmp);
8697 [(set (match_operand:DF 0 "register_operand" "")
8698 (match_operator:DF 1 "absneg_operator" [(match_dup 0)]))
8699 (use (match_operand 2 "" ""))
8700 (clobber (reg:CC FLAGS_REG))]
8702 [(parallel [(set (match_dup 0) (match_dup 1))
8703 (clobber (reg:CC FLAGS_REG))])]
8708 tmp = gen_lowpart (DImode, operands[0]);
8709 tmp = gen_rtx_ZERO_EXTRACT (DImode, tmp, const1_rtx, GEN_INT (63));
8712 if (GET_CODE (operands[1]) == ABS)
8715 tmp = gen_rtx_NOT (DImode, tmp);
8719 operands[0] = gen_highpart (SImode, operands[0]);
8720 if (GET_CODE (operands[1]) == ABS)
8722 tmp = gen_int_mode (0x7fffffff, SImode);
8723 tmp = gen_rtx_AND (SImode, operands[0], tmp);
8727 tmp = gen_int_mode (0x80000000, SImode);
8728 tmp = gen_rtx_XOR (SImode, operands[0], tmp);
8735 [(set (match_operand:XF 0 "register_operand" "")
8736 (match_operator:XF 1 "absneg_operator" [(match_dup 0)]))
8737 (use (match_operand 2 "" ""))
8738 (clobber (reg:CC FLAGS_REG))]
8740 [(parallel [(set (match_dup 0) (match_dup 1))
8741 (clobber (reg:CC FLAGS_REG))])]
8744 operands[0] = gen_rtx_REG (SImode,
8745 true_regnum (operands[0])
8746 + (TARGET_64BIT ? 1 : 2));
8747 if (GET_CODE (operands[1]) == ABS)
8749 tmp = GEN_INT (0x7fff);
8750 tmp = gen_rtx_AND (SImode, operands[0], tmp);
8754 tmp = GEN_INT (0x8000);
8755 tmp = gen_rtx_XOR (SImode, operands[0], tmp);
8760 ;; Conditionalize these after reload. If they match before reload, we
8761 ;; lose the clobber and ability to use integer instructions.
8763 (define_insn "*<code><mode>2_1"
8764 [(set (match_operand:X87MODEF 0 "register_operand" "=f")
8765 (absneg:X87MODEF (match_operand:X87MODEF 1 "register_operand" "0")))]
8767 && (reload_completed
8768 || !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH))"
8769 "f<absneg_mnemonic>"
8770 [(set_attr "type" "fsgn")
8771 (set_attr "mode" "<MODE>")])
8773 (define_insn "*<code>extendsfdf2"
8774 [(set (match_operand:DF 0 "register_operand" "=f")
8775 (absneg:DF (float_extend:DF
8776 (match_operand:SF 1 "register_operand" "0"))))]
8777 "TARGET_80387 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)"
8778 "f<absneg_mnemonic>"
8779 [(set_attr "type" "fsgn")
8780 (set_attr "mode" "DF")])
8782 (define_insn "*<code>extendsfxf2"
8783 [(set (match_operand:XF 0 "register_operand" "=f")
8784 (absneg:XF (float_extend:XF
8785 (match_operand:SF 1 "register_operand" "0"))))]
8787 "f<absneg_mnemonic>"
8788 [(set_attr "type" "fsgn")
8789 (set_attr "mode" "XF")])
8791 (define_insn "*<code>extenddfxf2"
8792 [(set (match_operand:XF 0 "register_operand" "=f")
8793 (absneg:XF (float_extend:XF
8794 (match_operand:DF 1 "register_operand" "0"))))]
8796 "f<absneg_mnemonic>"
8797 [(set_attr "type" "fsgn")
8798 (set_attr "mode" "XF")])
8800 ;; Copysign instructions
8802 (define_mode_iterator CSGNMODE [SF DF TF])
8803 (define_mode_attr CSGNVMODE [(SF "V4SF") (DF "V2DF") (TF "TF")])
8805 (define_expand "copysign<mode>3"
8806 [(match_operand:CSGNMODE 0 "register_operand" "")
8807 (match_operand:CSGNMODE 1 "nonmemory_operand" "")
8808 (match_operand:CSGNMODE 2 "register_operand" "")]
8809 "(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
8810 || (TARGET_SSE2 && (<MODE>mode == TFmode))"
8811 "ix86_expand_copysign (operands); DONE;")
8813 (define_insn_and_split "copysign<mode>3_const"
8814 [(set (match_operand:CSGNMODE 0 "register_operand" "=x")
8816 [(match_operand:<CSGNVMODE> 1 "vector_move_operand" "xmC")
8817 (match_operand:CSGNMODE 2 "register_operand" "0")
8818 (match_operand:<CSGNVMODE> 3 "nonimmediate_operand" "xm")]
8820 "(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
8821 || (TARGET_SSE2 && (<MODE>mode == TFmode))"
8823 "&& reload_completed"
8825 "ix86_split_copysign_const (operands); DONE;")
8827 (define_insn "copysign<mode>3_var"
8828 [(set (match_operand:CSGNMODE 0 "register_operand" "=x,x,x,x,x")
8830 [(match_operand:CSGNMODE 2 "register_operand" "x,0,0,x,x")
8831 (match_operand:CSGNMODE 3 "register_operand" "1,1,x,1,x")
8832 (match_operand:<CSGNVMODE> 4 "nonimmediate_operand" "X,xm,xm,0,0")
8833 (match_operand:<CSGNVMODE> 5 "nonimmediate_operand" "0,xm,1,xm,1")]
8835 (clobber (match_scratch:<CSGNVMODE> 1 "=x,x,x,x,x"))]
8836 "(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
8837 || (TARGET_SSE2 && (<MODE>mode == TFmode))"
8841 [(set (match_operand:CSGNMODE 0 "register_operand" "")
8843 [(match_operand:CSGNMODE 2 "register_operand" "")
8844 (match_operand:CSGNMODE 3 "register_operand" "")
8845 (match_operand:<CSGNVMODE> 4 "" "")
8846 (match_operand:<CSGNVMODE> 5 "" "")]
8848 (clobber (match_scratch:<CSGNVMODE> 1 ""))]
8849 "((SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
8850 || (TARGET_SSE2 && (<MODE>mode == TFmode)))
8851 && reload_completed"
8853 "ix86_split_copysign_var (operands); DONE;")
8855 ;; One complement instructions
8857 (define_expand "one_cmpl<mode>2"
8858 [(set (match_operand:SWIM 0 "nonimmediate_operand" "")
8859 (not:SWIM (match_operand:SWIM 1 "nonimmediate_operand" "")))]
8861 "ix86_expand_unary_operator (NOT, <MODE>mode, operands); DONE;")
8863 (define_insn "*one_cmpl<mode>2_1"
8864 [(set (match_operand:SWI248 0 "nonimmediate_operand" "=rm")
8865 (not:SWI248 (match_operand:SWI248 1 "nonimmediate_operand" "0")))]
8866 "ix86_unary_operator_ok (NOT, <MODE>mode, operands)"
8867 "not{<imodesuffix>}\t%0"
8868 [(set_attr "type" "negnot")
8869 (set_attr "mode" "<MODE>")])
8871 ;; %%% Potential partial reg stall on alternative 1. What to do?
8872 (define_insn "*one_cmplqi2_1"
8873 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
8874 (not:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")))]
8875 "ix86_unary_operator_ok (NOT, QImode, operands)"
8879 [(set_attr "type" "negnot")
8880 (set_attr "mode" "QI,SI")])
8882 ;; ??? Currently never generated - xor is used instead.
8883 (define_insn "*one_cmplsi2_1_zext"
8884 [(set (match_operand:DI 0 "register_operand" "=r")
8886 (not:SI (match_operand:SI 1 "register_operand" "0"))))]
8887 "TARGET_64BIT && ix86_unary_operator_ok (NOT, SImode, operands)"
8889 [(set_attr "type" "negnot")
8890 (set_attr "mode" "SI")])
8892 (define_insn "*one_cmpl<mode>2_2"
8893 [(set (reg FLAGS_REG)
8894 (compare (not:SWI (match_operand:SWI 1 "nonimmediate_operand" "0"))
8896 (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m")
8897 (not:SWI (match_dup 1)))]
8898 "ix86_match_ccmode (insn, CCNOmode)
8899 && ix86_unary_operator_ok (NOT, <MODE>mode, operands)"
8901 [(set_attr "type" "alu1")
8902 (set_attr "mode" "<MODE>")])
8905 [(set (match_operand 0 "flags_reg_operand" "")
8906 (match_operator 2 "compare_operator"
8907 [(not:SWI (match_operand:SWI 3 "nonimmediate_operand" ""))
8909 (set (match_operand:SWI 1 "nonimmediate_operand" "")
8910 (not:SWI (match_dup 3)))]
8911 "ix86_match_ccmode (insn, CCNOmode)"
8912 [(parallel [(set (match_dup 0)
8913 (match_op_dup 2 [(xor:SWI (match_dup 3) (const_int -1))
8916 (xor:SWI (match_dup 3) (const_int -1)))])])
8918 ;; ??? Currently never generated - xor is used instead.
8919 (define_insn "*one_cmplsi2_2_zext"
8920 [(set (reg FLAGS_REG)
8921 (compare (not:SI (match_operand:SI 1 "register_operand" "0"))
8923 (set (match_operand:DI 0 "register_operand" "=r")
8924 (zero_extend:DI (not:SI (match_dup 1))))]
8925 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8926 && ix86_unary_operator_ok (NOT, SImode, operands)"
8928 [(set_attr "type" "alu1")
8929 (set_attr "mode" "SI")])
8932 [(set (match_operand 0 "flags_reg_operand" "")
8933 (match_operator 2 "compare_operator"
8934 [(not:SI (match_operand:SI 3 "register_operand" ""))
8936 (set (match_operand:DI 1 "register_operand" "")
8937 (zero_extend:DI (not:SI (match_dup 3))))]
8938 "ix86_match_ccmode (insn, CCNOmode)"
8939 [(parallel [(set (match_dup 0)
8940 (match_op_dup 2 [(xor:SI (match_dup 3) (const_int -1))
8943 (zero_extend:DI (xor:SI (match_dup 3) (const_int -1))))])])
8945 ;; Shift instructions
8947 ;; DImode shifts are implemented using the i386 "shift double" opcode,
8948 ;; which is written as "sh[lr]d[lw] imm,reg,reg/mem". If the shift count
8949 ;; is variable, then the count is in %cl and the "imm" operand is dropped
8950 ;; from the assembler input.
8952 ;; This instruction shifts the target reg/mem as usual, but instead of
8953 ;; shifting in zeros, bits are shifted in from reg operand. If the insn
8954 ;; is a left shift double, bits are taken from the high order bits of
8955 ;; reg, else if the insn is a shift right double, bits are taken from the
8956 ;; low order bits of reg. So if %eax is "1234" and %edx is "5678",
8957 ;; "shldl $8,%edx,%eax" leaves %edx unchanged and sets %eax to "2345".
8959 ;; Since sh[lr]d does not change the `reg' operand, that is done
8960 ;; separately, making all shifts emit pairs of shift double and normal
8961 ;; shift. Since sh[lr]d does not shift more than 31 bits, and we wish to
8962 ;; support a 63 bit shift, each shift where the count is in a reg expands
8963 ;; to a pair of shifts, a branch, a shift by 32 and a label.
8965 ;; If the shift count is a constant, we need never emit more than one
8966 ;; shift pair, instead using moves and sign extension for counts greater
8969 (define_expand "ashl<mode>3"
8970 [(set (match_operand:SDWIM 0 "<shift_operand>" "")
8971 (ashift:SDWIM (match_operand:SDWIM 1 "<ashl_input_operand>" "")
8972 (match_operand:QI 2 "nonmemory_operand" "")))]
8974 "ix86_expand_binary_operator (ASHIFT, <MODE>mode, operands); DONE;")
8976 (define_insn "*ashl<mode>3_doubleword"
8977 [(set (match_operand:DWI 0 "register_operand" "=&r,r")
8978 (ashift:DWI (match_operand:DWI 1 "reg_or_pm1_operand" "n,0")
8979 (match_operand:QI 2 "nonmemory_operand" "<S>c,<S>c")))
8980 (clobber (reg:CC FLAGS_REG))]
8983 [(set_attr "type" "multi")])
8986 [(set (match_operand:DWI 0 "register_operand" "")
8987 (ashift:DWI (match_operand:DWI 1 "nonmemory_operand" "")
8988 (match_operand:QI 2 "nonmemory_operand" "")))
8989 (clobber (reg:CC FLAGS_REG))]
8990 "(optimize && flag_peephole2) ? epilogue_completed : reload_completed"
8992 "ix86_split_ashl (operands, NULL_RTX, <MODE>mode); DONE;")
8994 ;; By default we don't ask for a scratch register, because when DWImode
8995 ;; values are manipulated, registers are already at a premium. But if
8996 ;; we have one handy, we won't turn it away.
8999 [(match_scratch:DWIH 3 "r")
9000 (parallel [(set (match_operand:<DWI> 0 "register_operand" "")
9002 (match_operand:<DWI> 1 "nonmemory_operand" "")
9003 (match_operand:QI 2 "nonmemory_operand" "")))
9004 (clobber (reg:CC FLAGS_REG))])
9008 "ix86_split_ashl (operands, operands[3], <DWI>mode); DONE;")
9010 (define_insn "x86_64_shld"
9011 [(set (match_operand:DI 0 "nonimmediate_operand" "+r*m")
9012 (ior:DI (ashift:DI (match_dup 0)
9013 (match_operand:QI 2 "nonmemory_operand" "Jc"))
9014 (lshiftrt:DI (match_operand:DI 1 "register_operand" "r")
9015 (minus:QI (const_int 64) (match_dup 2)))))
9016 (clobber (reg:CC FLAGS_REG))]
9018 "shld{q}\t{%s2%1, %0|%0, %1, %2}"
9019 [(set_attr "type" "ishift")
9020 (set_attr "prefix_0f" "1")
9021 (set_attr "mode" "DI")
9022 (set_attr "athlon_decode" "vector")
9023 (set_attr "amdfam10_decode" "vector")
9024 (set_attr "bdver1_decode" "vector")])
9026 (define_insn "x86_shld"
9027 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m")
9028 (ior:SI (ashift:SI (match_dup 0)
9029 (match_operand:QI 2 "nonmemory_operand" "Ic"))
9030 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
9031 (minus:QI (const_int 32) (match_dup 2)))))
9032 (clobber (reg:CC FLAGS_REG))]
9034 "shld{l}\t{%s2%1, %0|%0, %1, %2}"
9035 [(set_attr "type" "ishift")
9036 (set_attr "prefix_0f" "1")
9037 (set_attr "mode" "SI")
9038 (set_attr "pent_pair" "np")
9039 (set_attr "athlon_decode" "vector")
9040 (set_attr "amdfam10_decode" "vector")
9041 (set_attr "bdver1_decode" "vector")])
9043 (define_expand "x86_shift<mode>_adj_1"
9044 [(set (reg:CCZ FLAGS_REG)
9045 (compare:CCZ (and:QI (match_operand:QI 2 "register_operand" "")
9048 (set (match_operand:SWI48 0 "register_operand" "")
9049 (if_then_else:SWI48 (ne (reg:CCZ FLAGS_REG) (const_int 0))
9050 (match_operand:SWI48 1 "register_operand" "")
9053 (if_then_else:SWI48 (ne (reg:CCZ FLAGS_REG) (const_int 0))
9054 (match_operand:SWI48 3 "register_operand" "")
9057 "operands[4] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));")
9059 (define_expand "x86_shift<mode>_adj_2"
9060 [(use (match_operand:SWI48 0 "register_operand" ""))
9061 (use (match_operand:SWI48 1 "register_operand" ""))
9062 (use (match_operand:QI 2 "register_operand" ""))]
9065 rtx label = gen_label_rtx ();
9068 emit_insn (gen_testqi_ccz_1 (operands[2],
9069 GEN_INT (GET_MODE_BITSIZE (<MODE>mode))));
9071 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
9072 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
9073 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
9074 gen_rtx_LABEL_REF (VOIDmode, label),
9076 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
9077 JUMP_LABEL (tmp) = label;
9079 emit_move_insn (operands[0], operands[1]);
9080 ix86_expand_clear (operands[1]);
9083 LABEL_NUSES (label) = 1;
9088 ;; Avoid useless masking of count operand.
9089 (define_insn "*ashl<mode>3_mask"
9090 [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm")
9092 (match_operand:SWI48 1 "nonimmediate_operand" "0")
9095 (match_operand:SI 2 "register_operand" "c")
9096 (match_operand:SI 3 "const_int_operand" "n")) 0)))
9097 (clobber (reg:CC FLAGS_REG))]
9098 "ix86_binary_operator_ok (ASHIFT, <MODE>mode, operands)
9099 && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1))
9100 == GET_MODE_BITSIZE (<MODE>mode)-1"
9102 return "sal{<imodesuffix>}\t{%b2, %0|%0, %b2}";
9104 [(set_attr "type" "ishift")
9105 (set_attr "mode" "<MODE>")])
9107 (define_insn "*bmi2_ashl<mode>3_1"
9108 [(set (match_operand:SWI48 0 "register_operand" "=r")
9109 (ashift:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "rm")
9110 (match_operand:SWI48 2 "register_operand" "r")))]
9112 "shlx\t{%2, %1, %0|%0, %1, %2}"
9113 [(set_attr "type" "ishiftx")
9114 (set_attr "mode" "<MODE>")])
9116 (define_insn "*ashl<mode>3_1"
9117 [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm,r,r")
9118 (ashift:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "0,l,rm")
9119 (match_operand:QI 2 "nonmemory_operand" "c<S>,M,r")))
9120 (clobber (reg:CC FLAGS_REG))]
9121 "ix86_binary_operator_ok (ASHIFT, <MODE>mode, operands)"
9123 switch (get_attr_type (insn))
9130 gcc_assert (operands[2] == const1_rtx);
9131 gcc_assert (rtx_equal_p (operands[0], operands[1]));
9132 return "add{<imodesuffix>}\t%0, %0";
9135 if (operands[2] == const1_rtx
9136 && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
9137 return "sal{<imodesuffix>}\t%0";
9139 return "sal{<imodesuffix>}\t{%2, %0|%0, %2}";
9142 [(set_attr "isa" "*,*,bmi2")
9144 (cond [(eq_attr "alternative" "1")
9145 (const_string "lea")
9146 (eq_attr "alternative" "2")
9147 (const_string "ishiftx")
9148 (and (and (match_test "TARGET_DOUBLE_WITH_ADD")
9149 (match_operand 0 "register_operand" ""))
9150 (match_operand 2 "const1_operand" ""))
9151 (const_string "alu")
9153 (const_string "ishift")))
9154 (set (attr "length_immediate")
9156 (ior (eq_attr "type" "alu")
9157 (and (eq_attr "type" "ishift")
9158 (and (match_operand 2 "const1_operand" "")
9159 (ior (match_test "TARGET_SHIFT1")
9160 (match_test "optimize_function_for_size_p (cfun)")))))
9162 (const_string "*")))
9163 (set_attr "mode" "<MODE>")])
9165 ;; Convert shift to the shiftx pattern to avoid flags dependency.
9167 [(set (match_operand:SWI48 0 "register_operand" "")
9168 (ashift:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "")
9169 (match_operand:QI 2 "register_operand" "")))
9170 (clobber (reg:CC FLAGS_REG))]
9171 "TARGET_BMI2 && reload_completed"
9173 (ashift:SWI48 (match_dup 1) (match_dup 2)))]
9174 "operands[2] = gen_lowpart (<MODE>mode, operands[2]);")
9176 (define_insn "*bmi2_ashlsi3_1_zext"
9177 [(set (match_operand:DI 0 "register_operand" "=r")
9179 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "rm")
9180 (match_operand:SI 2 "register_operand" "r"))))]
9181 "TARGET_64BIT && TARGET_BMI2"
9182 "shlx\t{%2, %1, %k0|%k0, %1, %2}"
9183 [(set_attr "type" "ishiftx")
9184 (set_attr "mode" "SI")])
9186 (define_insn "*ashlsi3_1_zext"
9187 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
9189 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,l,rm")
9190 (match_operand:QI 2 "nonmemory_operand" "cI,M,r"))))
9191 (clobber (reg:CC FLAGS_REG))]
9192 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
9194 switch (get_attr_type (insn))
9201 gcc_assert (operands[2] == const1_rtx);
9202 return "add{l}\t%k0, %k0";
9205 if (operands[2] == const1_rtx
9206 && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
9207 return "sal{l}\t%k0";
9209 return "sal{l}\t{%2, %k0|%k0, %2}";
9212 [(set_attr "isa" "*,*,bmi2")
9214 (cond [(eq_attr "alternative" "1")
9215 (const_string "lea")
9216 (eq_attr "alternative" "2")
9217 (const_string "ishiftx")
9218 (and (match_test "TARGET_DOUBLE_WITH_ADD")
9219 (match_operand 2 "const1_operand" ""))
9220 (const_string "alu")
9222 (const_string "ishift")))
9223 (set (attr "length_immediate")
9225 (ior (eq_attr "type" "alu")
9226 (and (eq_attr "type" "ishift")
9227 (and (match_operand 2 "const1_operand" "")
9228 (ior (match_test "TARGET_SHIFT1")
9229 (match_test "optimize_function_for_size_p (cfun)")))))
9231 (const_string "*")))
9232 (set_attr "mode" "SI")])
9234 ;; Convert shift to the shiftx pattern to avoid flags dependency.
9236 [(set (match_operand:DI 0 "register_operand" "")
9238 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "")
9239 (match_operand:QI 2 "register_operand" ""))))
9240 (clobber (reg:CC FLAGS_REG))]
9241 "TARGET_64BIT && TARGET_BMI2 && reload_completed"
9243 (zero_extend:DI (ashift:SI (match_dup 1) (match_dup 2))))]
9244 "operands[2] = gen_lowpart (SImode, operands[2]);")
9246 (define_insn "*ashlhi3_1"
9247 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,Yp")
9248 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0,l")
9249 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
9250 (clobber (reg:CC FLAGS_REG))]
9251 "ix86_binary_operator_ok (ASHIFT, HImode, operands)"
9253 switch (get_attr_type (insn))
9259 gcc_assert (operands[2] == const1_rtx);
9260 return "add{w}\t%0, %0";
9263 if (operands[2] == const1_rtx
9264 && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
9265 return "sal{w}\t%0";
9267 return "sal{w}\t{%2, %0|%0, %2}";
9271 (cond [(eq_attr "alternative" "1")
9272 (const_string "lea")
9273 (and (and (match_test "TARGET_DOUBLE_WITH_ADD")
9274 (match_operand 0 "register_operand" ""))
9275 (match_operand 2 "const1_operand" ""))
9276 (const_string "alu")
9278 (const_string "ishift")))
9279 (set (attr "length_immediate")
9281 (ior (eq_attr "type" "alu")
9282 (and (eq_attr "type" "ishift")
9283 (and (match_operand 2 "const1_operand" "")
9284 (ior (match_test "TARGET_SHIFT1")
9285 (match_test "optimize_function_for_size_p (cfun)")))))
9287 (const_string "*")))
9288 (set_attr "mode" "HI,SI")])
9290 ;; %%% Potential partial reg stall on alternative 1. What to do?
9291 (define_insn "*ashlqi3_1"
9292 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r,Yp")
9293 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,l")
9294 (match_operand:QI 2 "nonmemory_operand" "cI,cI,M")))
9295 (clobber (reg:CC FLAGS_REG))]
9296 "ix86_binary_operator_ok (ASHIFT, QImode, operands)"
9298 switch (get_attr_type (insn))
9304 gcc_assert (operands[2] == const1_rtx);
9305 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
9306 return "add{l}\t%k0, %k0";
9308 return "add{b}\t%0, %0";
9311 if (operands[2] == const1_rtx
9312 && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
9314 if (get_attr_mode (insn) == MODE_SI)
9315 return "sal{l}\t%k0";
9317 return "sal{b}\t%0";
9321 if (get_attr_mode (insn) == MODE_SI)
9322 return "sal{l}\t{%2, %k0|%k0, %2}";
9324 return "sal{b}\t{%2, %0|%0, %2}";
9329 (cond [(eq_attr "alternative" "2")
9330 (const_string "lea")
9331 (and (and (match_test "TARGET_DOUBLE_WITH_ADD")
9332 (match_operand 0 "register_operand" ""))
9333 (match_operand 2 "const1_operand" ""))
9334 (const_string "alu")
9336 (const_string "ishift")))
9337 (set (attr "length_immediate")
9339 (ior (eq_attr "type" "alu")
9340 (and (eq_attr "type" "ishift")
9341 (and (match_operand 2 "const1_operand" "")
9342 (ior (match_test "TARGET_SHIFT1")
9343 (match_test "optimize_function_for_size_p (cfun)")))))
9345 (const_string "*")))
9346 (set_attr "mode" "QI,SI,SI")])
9348 (define_insn "*ashlqi3_1_slp"
9349 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
9350 (ashift:QI (match_dup 0)
9351 (match_operand:QI 1 "nonmemory_operand" "cI")))
9352 (clobber (reg:CC FLAGS_REG))]
9353 "(optimize_function_for_size_p (cfun)
9354 || !TARGET_PARTIAL_FLAG_REG_STALL
9355 || (operands[1] == const1_rtx
9357 || (TARGET_DOUBLE_WITH_ADD && REG_P (operands[0])))))"
9359 switch (get_attr_type (insn))
9362 gcc_assert (operands[1] == const1_rtx);
9363 return "add{b}\t%0, %0";
9366 if (operands[1] == const1_rtx
9367 && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
9368 return "sal{b}\t%0";
9370 return "sal{b}\t{%1, %0|%0, %1}";
9374 (cond [(and (and (match_test "TARGET_DOUBLE_WITH_ADD")
9375 (match_operand 0 "register_operand" ""))
9376 (match_operand 1 "const1_operand" ""))
9377 (const_string "alu")
9379 (const_string "ishift1")))
9380 (set (attr "length_immediate")
9382 (ior (eq_attr "type" "alu")
9383 (and (eq_attr "type" "ishift1")
9384 (and (match_operand 1 "const1_operand" "")
9385 (ior (match_test "TARGET_SHIFT1")
9386 (match_test "optimize_function_for_size_p (cfun)")))))
9388 (const_string "*")))
9389 (set_attr "mode" "QI")])
9391 ;; Convert ashift to the lea pattern to avoid flags dependency.
9393 [(set (match_operand 0 "register_operand" "")
9394 (ashift (match_operand 1 "index_register_operand" "")
9395 (match_operand:QI 2 "const_int_operand" "")))
9396 (clobber (reg:CC FLAGS_REG))]
9397 "GET_MODE (operands[0]) == GET_MODE (operands[1])
9399 && true_regnum (operands[0]) != true_regnum (operands[1])"
9402 enum machine_mode mode = GET_MODE (operands[0]);
9405 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (SImode))
9408 operands[0] = gen_lowpart (mode, operands[0]);
9409 operands[1] = gen_lowpart (mode, operands[1]);
9412 operands[2] = gen_int_mode (1 << INTVAL (operands[2]), mode);
9414 pat = gen_rtx_MULT (mode, operands[1], operands[2]);
9416 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
9420 ;; Convert ashift to the lea pattern to avoid flags dependency.
9422 [(set (match_operand:DI 0 "register_operand" "")
9424 (ashift:SI (match_operand:SI 1 "index_register_operand" "")
9425 (match_operand:QI 2 "const_int_operand" ""))))
9426 (clobber (reg:CC FLAGS_REG))]
9427 "TARGET_64BIT && reload_completed
9428 && true_regnum (operands[0]) != true_regnum (operands[1])"
9430 (zero_extend:DI (subreg:SI (mult:DI (match_dup 1) (match_dup 2)) 0)))]
9432 operands[1] = gen_lowpart (DImode, operands[1]);
9433 operands[2] = gen_int_mode (1 << INTVAL (operands[2]), DImode);
9436 ;; This pattern can't accept a variable shift count, since shifts by
9437 ;; zero don't affect the flags. We assume that shifts by constant
9438 ;; zero are optimized away.
9439 (define_insn "*ashl<mode>3_cmp"
9440 [(set (reg FLAGS_REG)
9442 (ashift:SWI (match_operand:SWI 1 "nonimmediate_operand" "0")
9443 (match_operand:QI 2 "<shift_immediate_operand>" "<S>"))
9445 (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m")
9446 (ashift:SWI (match_dup 1) (match_dup 2)))]
9447 "(optimize_function_for_size_p (cfun)
9448 || !TARGET_PARTIAL_FLAG_REG_STALL
9449 || (operands[2] == const1_rtx
9451 || (TARGET_DOUBLE_WITH_ADD && REG_P (operands[0])))))
9452 && ix86_match_ccmode (insn, CCGOCmode)
9453 && ix86_binary_operator_ok (ASHIFT, <MODE>mode, operands)"
9455 switch (get_attr_type (insn))
9458 gcc_assert (operands[2] == const1_rtx);
9459 return "add{<imodesuffix>}\t%0, %0";
9462 if (operands[2] == const1_rtx
9463 && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
9464 return "sal{<imodesuffix>}\t%0";
9466 return "sal{<imodesuffix>}\t{%2, %0|%0, %2}";
9470 (cond [(and (and (match_test "TARGET_DOUBLE_WITH_ADD")
9471 (match_operand 0 "register_operand" ""))
9472 (match_operand 2 "const1_operand" ""))
9473 (const_string "alu")
9475 (const_string "ishift")))
9476 (set (attr "length_immediate")
9478 (ior (eq_attr "type" "alu")
9479 (and (eq_attr "type" "ishift")
9480 (and (match_operand 2 "const1_operand" "")
9481 (ior (match_test "TARGET_SHIFT1")
9482 (match_test "optimize_function_for_size_p (cfun)")))))
9484 (const_string "*")))
9485 (set_attr "mode" "<MODE>")])
9487 (define_insn "*ashlsi3_cmp_zext"
9488 [(set (reg FLAGS_REG)
9490 (ashift:SI (match_operand:SI 1 "register_operand" "0")
9491 (match_operand:QI 2 "const_1_to_31_operand" "I"))
9493 (set (match_operand:DI 0 "register_operand" "=r")
9494 (zero_extend:DI (ashift:SI (match_dup 1) (match_dup 2))))]
9496 && (optimize_function_for_size_p (cfun)
9497 || !TARGET_PARTIAL_FLAG_REG_STALL
9498 || (operands[2] == const1_rtx
9500 || TARGET_DOUBLE_WITH_ADD)))
9501 && ix86_match_ccmode (insn, CCGOCmode)
9502 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
9504 switch (get_attr_type (insn))
9507 gcc_assert (operands[2] == const1_rtx);
9508 return "add{l}\t%k0, %k0";
9511 if (operands[2] == const1_rtx
9512 && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
9513 return "sal{l}\t%k0";
9515 return "sal{l}\t{%2, %k0|%k0, %2}";
9519 (cond [(and (match_test "TARGET_DOUBLE_WITH_ADD")
9520 (match_operand 2 "const1_operand" ""))
9521 (const_string "alu")
9523 (const_string "ishift")))
9524 (set (attr "length_immediate")
9526 (ior (eq_attr "type" "alu")
9527 (and (eq_attr "type" "ishift")
9528 (and (match_operand 2 "const1_operand" "")
9529 (ior (match_test "TARGET_SHIFT1")
9530 (match_test "optimize_function_for_size_p (cfun)")))))
9532 (const_string "*")))
9533 (set_attr "mode" "SI")])
9535 (define_insn "*ashl<mode>3_cconly"
9536 [(set (reg FLAGS_REG)
9538 (ashift:SWI (match_operand:SWI 1 "register_operand" "0")
9539 (match_operand:QI 2 "<shift_immediate_operand>" "<S>"))
9541 (clobber (match_scratch:SWI 0 "=<r>"))]
9542 "(optimize_function_for_size_p (cfun)
9543 || !TARGET_PARTIAL_FLAG_REG_STALL
9544 || (operands[2] == const1_rtx
9546 || TARGET_DOUBLE_WITH_ADD)))
9547 && ix86_match_ccmode (insn, CCGOCmode)"
9549 switch (get_attr_type (insn))
9552 gcc_assert (operands[2] == const1_rtx);
9553 return "add{<imodesuffix>}\t%0, %0";
9556 if (operands[2] == const1_rtx
9557 && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
9558 return "sal{<imodesuffix>}\t%0";
9560 return "sal{<imodesuffix>}\t{%2, %0|%0, %2}";
9564 (cond [(and (and (match_test "TARGET_DOUBLE_WITH_ADD")
9565 (match_operand 0 "register_operand" ""))
9566 (match_operand 2 "const1_operand" ""))
9567 (const_string "alu")
9569 (const_string "ishift")))
9570 (set (attr "length_immediate")
9572 (ior (eq_attr "type" "alu")
9573 (and (eq_attr "type" "ishift")
9574 (and (match_operand 2 "const1_operand" "")
9575 (ior (match_test "TARGET_SHIFT1")
9576 (match_test "optimize_function_for_size_p (cfun)")))))
9578 (const_string "*")))
9579 (set_attr "mode" "<MODE>")])
9581 ;; See comment above `ashl<mode>3' about how this works.
9583 (define_expand "<shift_insn><mode>3"
9584 [(set (match_operand:SDWIM 0 "<shift_operand>" "")
9585 (any_shiftrt:SDWIM (match_operand:SDWIM 1 "<shift_operand>" "")
9586 (match_operand:QI 2 "nonmemory_operand" "")))]
9588 "ix86_expand_binary_operator (<CODE>, <MODE>mode, operands); DONE;")
9590 ;; Avoid useless masking of count operand.
9591 (define_insn "*<shift_insn><mode>3_mask"
9592 [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm")
9594 (match_operand:SWI48 1 "nonimmediate_operand" "0")
9597 (match_operand:SI 2 "register_operand" "c")
9598 (match_operand:SI 3 "const_int_operand" "n")) 0)))
9599 (clobber (reg:CC FLAGS_REG))]
9600 "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)
9601 && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1))
9602 == GET_MODE_BITSIZE (<MODE>mode)-1"
9604 return "<shift>{<imodesuffix>}\t{%b2, %0|%0, %b2}";
9606 [(set_attr "type" "ishift")
9607 (set_attr "mode" "<MODE>")])
9609 (define_insn_and_split "*<shift_insn><mode>3_doubleword"
9610 [(set (match_operand:DWI 0 "register_operand" "=r")
9611 (any_shiftrt:DWI (match_operand:DWI 1 "register_operand" "0")
9612 (match_operand:QI 2 "nonmemory_operand" "<S>c")))
9613 (clobber (reg:CC FLAGS_REG))]
9616 "(optimize && flag_peephole2) ? epilogue_completed : reload_completed"
9618 "ix86_split_<shift_insn> (operands, NULL_RTX, <MODE>mode); DONE;"
9619 [(set_attr "type" "multi")])
9621 ;; By default we don't ask for a scratch register, because when DWImode
9622 ;; values are manipulated, registers are already at a premium. But if
9623 ;; we have one handy, we won't turn it away.
9626 [(match_scratch:DWIH 3 "r")
9627 (parallel [(set (match_operand:<DWI> 0 "register_operand" "")
9629 (match_operand:<DWI> 1 "register_operand" "")
9630 (match_operand:QI 2 "nonmemory_operand" "")))
9631 (clobber (reg:CC FLAGS_REG))])
9635 "ix86_split_<shift_insn> (operands, operands[3], <DWI>mode); DONE;")
9637 (define_insn "x86_64_shrd"
9638 [(set (match_operand:DI 0 "nonimmediate_operand" "+r*m")
9639 (ior:DI (ashiftrt:DI (match_dup 0)
9640 (match_operand:QI 2 "nonmemory_operand" "Jc"))
9641 (ashift:DI (match_operand:DI 1 "register_operand" "r")
9642 (minus:QI (const_int 64) (match_dup 2)))))
9643 (clobber (reg:CC FLAGS_REG))]
9645 "shrd{q}\t{%s2%1, %0|%0, %1, %2}"
9646 [(set_attr "type" "ishift")
9647 (set_attr "prefix_0f" "1")
9648 (set_attr "mode" "DI")
9649 (set_attr "athlon_decode" "vector")
9650 (set_attr "amdfam10_decode" "vector")
9651 (set_attr "bdver1_decode" "vector")])
9653 (define_insn "x86_shrd"
9654 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m")
9655 (ior:SI (ashiftrt:SI (match_dup 0)
9656 (match_operand:QI 2 "nonmemory_operand" "Ic"))
9657 (ashift:SI (match_operand:SI 1 "register_operand" "r")
9658 (minus:QI (const_int 32) (match_dup 2)))))
9659 (clobber (reg:CC FLAGS_REG))]
9661 "shrd{l}\t{%s2%1, %0|%0, %1, %2}"
9662 [(set_attr "type" "ishift")
9663 (set_attr "prefix_0f" "1")
9664 (set_attr "mode" "SI")
9665 (set_attr "pent_pair" "np")
9666 (set_attr "athlon_decode" "vector")
9667 (set_attr "amdfam10_decode" "vector")
9668 (set_attr "bdver1_decode" "vector")])
9670 (define_insn "ashrdi3_cvt"
9671 [(set (match_operand:DI 0 "nonimmediate_operand" "=*d,rm")
9672 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "*a,0")
9673 (match_operand:QI 2 "const_int_operand" "")))
9674 (clobber (reg:CC FLAGS_REG))]
9675 "TARGET_64BIT && INTVAL (operands[2]) == 63
9676 && (TARGET_USE_CLTD || optimize_function_for_size_p (cfun))
9677 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
9680 sar{q}\t{%2, %0|%0, %2}"
9681 [(set_attr "type" "imovx,ishift")
9682 (set_attr "prefix_0f" "0,*")
9683 (set_attr "length_immediate" "0,*")
9684 (set_attr "modrm" "0,1")
9685 (set_attr "mode" "DI")])
9687 (define_insn "ashrsi3_cvt"
9688 [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm")
9689 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0")
9690 (match_operand:QI 2 "const_int_operand" "")))
9691 (clobber (reg:CC FLAGS_REG))]
9692 "INTVAL (operands[2]) == 31
9693 && (TARGET_USE_CLTD || optimize_function_for_size_p (cfun))
9694 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
9697 sar{l}\t{%2, %0|%0, %2}"
9698 [(set_attr "type" "imovx,ishift")
9699 (set_attr "prefix_0f" "0,*")
9700 (set_attr "length_immediate" "0,*")
9701 (set_attr "modrm" "0,1")
9702 (set_attr "mode" "SI")])
9704 (define_insn "*ashrsi3_cvt_zext"
9705 [(set (match_operand:DI 0 "register_operand" "=*d,r")
9707 (ashiftrt:SI (match_operand:SI 1 "register_operand" "*a,0")
9708 (match_operand:QI 2 "const_int_operand" ""))))
9709 (clobber (reg:CC FLAGS_REG))]
9710 "TARGET_64BIT && INTVAL (operands[2]) == 31
9711 && (TARGET_USE_CLTD || optimize_function_for_size_p (cfun))
9712 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
9715 sar{l}\t{%2, %k0|%k0, %2}"
9716 [(set_attr "type" "imovx,ishift")
9717 (set_attr "prefix_0f" "0,*")
9718 (set_attr "length_immediate" "0,*")
9719 (set_attr "modrm" "0,1")
9720 (set_attr "mode" "SI")])
9722 (define_expand "x86_shift<mode>_adj_3"
9723 [(use (match_operand:SWI48 0 "register_operand" ""))
9724 (use (match_operand:SWI48 1 "register_operand" ""))
9725 (use (match_operand:QI 2 "register_operand" ""))]
9728 rtx label = gen_label_rtx ();
9731 emit_insn (gen_testqi_ccz_1 (operands[2],
9732 GEN_INT (GET_MODE_BITSIZE (<MODE>mode))));
9734 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
9735 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
9736 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
9737 gen_rtx_LABEL_REF (VOIDmode, label),
9739 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
9740 JUMP_LABEL (tmp) = label;
9742 emit_move_insn (operands[0], operands[1]);
9743 emit_insn (gen_ashr<mode>3_cvt (operands[1], operands[1],
9744 GEN_INT (GET_MODE_BITSIZE (<MODE>mode)-1)));
9746 LABEL_NUSES (label) = 1;
9751 (define_insn "*bmi2_<shift_insn><mode>3_1"
9752 [(set (match_operand:SWI48 0 "register_operand" "=r")
9753 (any_shiftrt:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "rm")
9754 (match_operand:SWI48 2 "register_operand" "r")))]
9756 "<shift>x\t{%2, %1, %0|%0, %1, %2}"
9757 [(set_attr "type" "ishiftx")
9758 (set_attr "mode" "<MODE>")])
9760 (define_insn "*<shift_insn><mode>3_1"
9761 [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm,r")
9763 (match_operand:SWI48 1 "nonimmediate_operand" "0,rm")
9764 (match_operand:QI 2 "nonmemory_operand" "c<S>,r")))
9765 (clobber (reg:CC FLAGS_REG))]
9766 "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
9768 switch (get_attr_type (insn))
9774 if (operands[2] == const1_rtx
9775 && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
9776 return "<shift>{<imodesuffix>}\t%0";
9778 return "<shift>{<imodesuffix>}\t{%2, %0|%0, %2}";
9781 [(set_attr "isa" "*,bmi2")
9782 (set_attr "type" "ishift,ishiftx")
9783 (set (attr "length_immediate")
9785 (and (match_operand 2 "const1_operand" "")
9786 (ior (match_test "TARGET_SHIFT1")
9787 (match_test "optimize_function_for_size_p (cfun)")))
9789 (const_string "*")))
9790 (set_attr "mode" "<MODE>")])
9792 ;; Convert shift to the shiftx pattern to avoid flags dependency.
9794 [(set (match_operand:SWI48 0 "register_operand" "")
9795 (any_shiftrt:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "")
9796 (match_operand:QI 2 "register_operand" "")))
9797 (clobber (reg:CC FLAGS_REG))]
9798 "TARGET_BMI2 && reload_completed"
9800 (any_shiftrt:SWI48 (match_dup 1) (match_dup 2)))]
9801 "operands[2] = gen_lowpart (<MODE>mode, operands[2]);")
9803 (define_insn "*bmi2_<shift_insn>si3_1_zext"
9804 [(set (match_operand:DI 0 "register_operand" "=r")
9806 (any_shiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "rm")
9807 (match_operand:SI 2 "register_operand" "r"))))]
9808 "TARGET_64BIT && TARGET_BMI2"
9809 "<shift>x\t{%2, %1, %k0|%k0, %1, %2}"
9810 [(set_attr "type" "ishiftx")
9811 (set_attr "mode" "SI")])
9813 (define_insn "*<shift_insn>si3_1_zext"
9814 [(set (match_operand:DI 0 "register_operand" "=r,r")
9816 (any_shiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,rm")
9817 (match_operand:QI 2 "nonmemory_operand" "cI,r"))))
9818 (clobber (reg:CC FLAGS_REG))]
9819 "TARGET_64BIT && ix86_binary_operator_ok (<CODE>, SImode, operands)"
9821 switch (get_attr_type (insn))
9827 if (operands[2] == const1_rtx
9828 && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
9829 return "<shift>{l}\t%k0";
9831 return "<shift>{l}\t{%2, %k0|%k0, %2}";
9834 [(set_attr "isa" "*,bmi2")
9835 (set_attr "type" "ishift,ishiftx")
9836 (set (attr "length_immediate")
9838 (and (match_operand 2 "const1_operand" "")
9839 (ior (match_test "TARGET_SHIFT1")
9840 (match_test "optimize_function_for_size_p (cfun)")))
9842 (const_string "*")))
9843 (set_attr "mode" "SI")])
9845 ;; Convert shift to the shiftx pattern to avoid flags dependency.
9847 [(set (match_operand:DI 0 "register_operand" "")
9849 (any_shiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
9850 (match_operand:QI 2 "register_operand" ""))))
9851 (clobber (reg:CC FLAGS_REG))]
9852 "TARGET_64BIT && TARGET_BMI2 && reload_completed"
9854 (zero_extend:DI (any_shiftrt:SI (match_dup 1) (match_dup 2))))]
9855 "operands[2] = gen_lowpart (SImode, operands[2]);")
9857 (define_insn "*<shift_insn><mode>3_1"
9858 [(set (match_operand:SWI12 0 "nonimmediate_operand" "=<r>m")
9860 (match_operand:SWI12 1 "nonimmediate_operand" "0")
9861 (match_operand:QI 2 "nonmemory_operand" "c<S>")))
9862 (clobber (reg:CC FLAGS_REG))]
9863 "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
9865 if (operands[2] == const1_rtx
9866 && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
9867 return "<shift>{<imodesuffix>}\t%0";
9869 return "<shift>{<imodesuffix>}\t{%2, %0|%0, %2}";
9871 [(set_attr "type" "ishift")
9872 (set (attr "length_immediate")
9874 (and (match_operand 2 "const1_operand" "")
9875 (ior (match_test "TARGET_SHIFT1")
9876 (match_test "optimize_function_for_size_p (cfun)")))
9878 (const_string "*")))
9879 (set_attr "mode" "<MODE>")])
9881 (define_insn "*<shift_insn>qi3_1_slp"
9882 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
9883 (any_shiftrt:QI (match_dup 0)
9884 (match_operand:QI 1 "nonmemory_operand" "cI")))
9885 (clobber (reg:CC FLAGS_REG))]
9886 "(optimize_function_for_size_p (cfun)
9887 || !TARGET_PARTIAL_REG_STALL
9888 || (operands[1] == const1_rtx
9891 if (operands[1] == const1_rtx
9892 && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
9893 return "<shift>{b}\t%0";
9895 return "<shift>{b}\t{%1, %0|%0, %1}";
9897 [(set_attr "type" "ishift1")
9898 (set (attr "length_immediate")
9900 (and (match_operand 1 "const1_operand" "")
9901 (ior (match_test "TARGET_SHIFT1")
9902 (match_test "optimize_function_for_size_p (cfun)")))
9904 (const_string "*")))
9905 (set_attr "mode" "QI")])
9907 ;; This pattern can't accept a variable shift count, since shifts by
9908 ;; zero don't affect the flags. We assume that shifts by constant
9909 ;; zero are optimized away.
9910 (define_insn "*<shift_insn><mode>3_cmp"
9911 [(set (reg FLAGS_REG)
9914 (match_operand:SWI 1 "nonimmediate_operand" "0")
9915 (match_operand:QI 2 "<shift_immediate_operand>" "<S>"))
9917 (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m")
9918 (any_shiftrt:SWI (match_dup 1) (match_dup 2)))]
9919 "(optimize_function_for_size_p (cfun)
9920 || !TARGET_PARTIAL_FLAG_REG_STALL
9921 || (operands[2] == const1_rtx
9923 && ix86_match_ccmode (insn, CCGOCmode)
9924 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
9926 if (operands[2] == const1_rtx
9927 && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
9928 return "<shift>{<imodesuffix>}\t%0";
9930 return "<shift>{<imodesuffix>}\t{%2, %0|%0, %2}";
9932 [(set_attr "type" "ishift")
9933 (set (attr "length_immediate")
9935 (and (match_operand 2 "const1_operand" "")
9936 (ior (match_test "TARGET_SHIFT1")
9937 (match_test "optimize_function_for_size_p (cfun)")))
9939 (const_string "*")))
9940 (set_attr "mode" "<MODE>")])
9942 (define_insn "*<shift_insn>si3_cmp_zext"
9943 [(set (reg FLAGS_REG)
9945 (any_shiftrt:SI (match_operand:SI 1 "register_operand" "0")
9946 (match_operand:QI 2 "const_1_to_31_operand" "I"))
9948 (set (match_operand:DI 0 "register_operand" "=r")
9949 (zero_extend:DI (any_shiftrt:SI (match_dup 1) (match_dup 2))))]
9951 && (optimize_function_for_size_p (cfun)
9952 || !TARGET_PARTIAL_FLAG_REG_STALL
9953 || (operands[2] == const1_rtx
9955 && ix86_match_ccmode (insn, CCGOCmode)
9956 && ix86_binary_operator_ok (<CODE>, SImode, operands)"
9958 if (operands[2] == const1_rtx
9959 && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
9960 return "<shift>{l}\t%k0";
9962 return "<shift>{l}\t{%2, %k0|%k0, %2}";
9964 [(set_attr "type" "ishift")
9965 (set (attr "length_immediate")
9967 (and (match_operand 2 "const1_operand" "")
9968 (ior (match_test "TARGET_SHIFT1")
9969 (match_test "optimize_function_for_size_p (cfun)")))
9971 (const_string "*")))
9972 (set_attr "mode" "SI")])
9974 (define_insn "*<shift_insn><mode>3_cconly"
9975 [(set (reg FLAGS_REG)
9978 (match_operand:SWI 1 "register_operand" "0")
9979 (match_operand:QI 2 "<shift_immediate_operand>" "<S>"))
9981 (clobber (match_scratch:SWI 0 "=<r>"))]
9982 "(optimize_function_for_size_p (cfun)
9983 || !TARGET_PARTIAL_FLAG_REG_STALL
9984 || (operands[2] == const1_rtx
9986 && ix86_match_ccmode (insn, CCGOCmode)"
9988 if (operands[2] == const1_rtx
9989 && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
9990 return "<shift>{<imodesuffix>}\t%0";
9992 return "<shift>{<imodesuffix>}\t{%2, %0|%0, %2}";
9994 [(set_attr "type" "ishift")
9995 (set (attr "length_immediate")
9997 (and (match_operand 2 "const1_operand" "")
9998 (ior (match_test "TARGET_SHIFT1")
9999 (match_test "optimize_function_for_size_p (cfun)")))
10001 (const_string "*")))
10002 (set_attr "mode" "<MODE>")])
10004 ;; Rotate instructions
10006 (define_expand "<rotate_insn>ti3"
10007 [(set (match_operand:TI 0 "register_operand" "")
10008 (any_rotate:TI (match_operand:TI 1 "register_operand" "")
10009 (match_operand:QI 2 "nonmemory_operand" "")))]
10012 if (const_1_to_63_operand (operands[2], VOIDmode))
10013 emit_insn (gen_ix86_<rotate_insn>ti3_doubleword
10014 (operands[0], operands[1], operands[2]));
10021 (define_expand "<rotate_insn>di3"
10022 [(set (match_operand:DI 0 "shiftdi_operand" "")
10023 (any_rotate:DI (match_operand:DI 1 "shiftdi_operand" "")
10024 (match_operand:QI 2 "nonmemory_operand" "")))]
10028 ix86_expand_binary_operator (<CODE>, DImode, operands);
10029 else if (const_1_to_31_operand (operands[2], VOIDmode))
10030 emit_insn (gen_ix86_<rotate_insn>di3_doubleword
10031 (operands[0], operands[1], operands[2]));
10038 (define_expand "<rotate_insn><mode>3"
10039 [(set (match_operand:SWIM124 0 "nonimmediate_operand" "")
10040 (any_rotate:SWIM124 (match_operand:SWIM124 1 "nonimmediate_operand" "")
10041 (match_operand:QI 2 "nonmemory_operand" "")))]
10043 "ix86_expand_binary_operator (<CODE>, <MODE>mode, operands); DONE;")
10045 ;; Avoid useless masking of count operand.
10046 (define_insn "*<rotate_insn><mode>3_mask"
10047 [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm")
10049 (match_operand:SWI48 1 "nonimmediate_operand" "0")
10052 (match_operand:SI 2 "register_operand" "c")
10053 (match_operand:SI 3 "const_int_operand" "n")) 0)))
10054 (clobber (reg:CC FLAGS_REG))]
10055 "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)
10056 && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1))
10057 == GET_MODE_BITSIZE (<MODE>mode)-1"
10059 return "<rotate>{<imodesuffix>}\t{%b2, %0|%0, %b2}";
10061 [(set_attr "type" "rotate")
10062 (set_attr "mode" "<MODE>")])
10064 ;; Implement rotation using two double-precision
10065 ;; shift instructions and a scratch register.
10067 (define_insn_and_split "ix86_rotl<dwi>3_doubleword"
10068 [(set (match_operand:<DWI> 0 "register_operand" "=r")
10069 (rotate:<DWI> (match_operand:<DWI> 1 "register_operand" "0")
10070 (match_operand:QI 2 "<shift_immediate_operand>" "<S>")))
10071 (clobber (reg:CC FLAGS_REG))
10072 (clobber (match_scratch:DWIH 3 "=&r"))]
10076 [(set (match_dup 3) (match_dup 4))
10078 [(set (match_dup 4)
10079 (ior:DWIH (ashift:DWIH (match_dup 4) (match_dup 2))
10080 (lshiftrt:DWIH (match_dup 5)
10081 (minus:QI (match_dup 6) (match_dup 2)))))
10082 (clobber (reg:CC FLAGS_REG))])
10084 [(set (match_dup 5)
10085 (ior:DWIH (ashift:DWIH (match_dup 5) (match_dup 2))
10086 (lshiftrt:DWIH (match_dup 3)
10087 (minus:QI (match_dup 6) (match_dup 2)))))
10088 (clobber (reg:CC FLAGS_REG))])]
10090 operands[6] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
10092 split_double_mode (<DWI>mode, &operands[0], 1, &operands[4], &operands[5]);
10095 (define_insn_and_split "ix86_rotr<dwi>3_doubleword"
10096 [(set (match_operand:<DWI> 0 "register_operand" "=r")
10097 (rotatert:<DWI> (match_operand:<DWI> 1 "register_operand" "0")
10098 (match_operand:QI 2 "<shift_immediate_operand>" "<S>")))
10099 (clobber (reg:CC FLAGS_REG))
10100 (clobber (match_scratch:DWIH 3 "=&r"))]
10104 [(set (match_dup 3) (match_dup 4))
10106 [(set (match_dup 4)
10107 (ior:DWIH (ashiftrt:DWIH (match_dup 4) (match_dup 2))
10108 (ashift:DWIH (match_dup 5)
10109 (minus:QI (match_dup 6) (match_dup 2)))))
10110 (clobber (reg:CC FLAGS_REG))])
10112 [(set (match_dup 5)
10113 (ior:DWIH (ashiftrt:DWIH (match_dup 5) (match_dup 2))
10114 (ashift:DWIH (match_dup 3)
10115 (minus:QI (match_dup 6) (match_dup 2)))))
10116 (clobber (reg:CC FLAGS_REG))])]
10118 operands[6] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
10120 split_double_mode (<DWI>mode, &operands[0], 1, &operands[4], &operands[5]);
10123 (define_insn "*bmi2_rorx<mode>3_1"
10124 [(set (match_operand:SWI48 0 "register_operand" "=r")
10125 (rotatert:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "rm")
10126 (match_operand:QI 2 "immediate_operand" "<S>")))]
10128 "rorx\t{%2, %1, %0|%0, %1, %2}"
10129 [(set_attr "type" "rotatex")
10130 (set_attr "mode" "<MODE>")])
10132 (define_insn "*<rotate_insn><mode>3_1"
10133 [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm,r")
10135 (match_operand:SWI48 1 "nonimmediate_operand" "0,rm")
10136 (match_operand:QI 2 "nonmemory_operand" "c<S>,<S>")))
10137 (clobber (reg:CC FLAGS_REG))]
10138 "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
10140 switch (get_attr_type (insn))
10146 if (operands[2] == const1_rtx
10147 && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
10148 return "<rotate>{<imodesuffix>}\t%0";
10150 return "<rotate>{<imodesuffix>}\t{%2, %0|%0, %2}";
10153 [(set_attr "isa" "*,bmi2")
10154 (set_attr "type" "rotate,rotatex")
10155 (set (attr "length_immediate")
10157 (and (eq_attr "type" "rotate")
10158 (and (match_operand 2 "const1_operand" "")
10159 (ior (match_test "TARGET_SHIFT1")
10160 (match_test "optimize_function_for_size_p (cfun)"))))
10162 (const_string "*")))
10163 (set_attr "mode" "<MODE>")])
10165 ;; Convert rotate to the rotatex pattern to avoid flags dependency.
10167 [(set (match_operand:SWI48 0 "register_operand" "")
10168 (rotate:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "")
10169 (match_operand:QI 2 "immediate_operand" "")))
10170 (clobber (reg:CC FLAGS_REG))]
10171 "TARGET_BMI2 && reload_completed"
10172 [(set (match_dup 0)
10173 (rotatert:SWI48 (match_dup 1) (match_dup 2)))]
10176 = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - INTVAL (operands[2]));
10180 [(set (match_operand:SWI48 0 "register_operand" "")
10181 (rotatert:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "")
10182 (match_operand:QI 2 "immediate_operand" "")))
10183 (clobber (reg:CC FLAGS_REG))]
10184 "TARGET_BMI2 && reload_completed"
10185 [(set (match_dup 0)
10186 (rotatert:SWI48 (match_dup 1) (match_dup 2)))])
10188 (define_insn "*bmi2_rorxsi3_1_zext"
10189 [(set (match_operand:DI 0 "register_operand" "=r")
10191 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "rm")
10192 (match_operand:QI 2 "immediate_operand" "I"))))]
10193 "TARGET_64BIT && TARGET_BMI2"
10194 "rorx\t{%2, %1, %k0|%k0, %1, %2}"
10195 [(set_attr "type" "rotatex")
10196 (set_attr "mode" "SI")])
10198 (define_insn "*<rotate_insn>si3_1_zext"
10199 [(set (match_operand:DI 0 "register_operand" "=r,r")
10201 (any_rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0,rm")
10202 (match_operand:QI 2 "nonmemory_operand" "cI,I"))))
10203 (clobber (reg:CC FLAGS_REG))]
10204 "TARGET_64BIT && ix86_binary_operator_ok (<CODE>, SImode, operands)"
10206 switch (get_attr_type (insn))
10212 if (operands[2] == const1_rtx
10213 && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
10214 return "<rotate>{l}\t%k0";
10216 return "<rotate>{l}\t{%2, %k0|%k0, %2}";
10219 [(set_attr "isa" "*,bmi2")
10220 (set_attr "type" "rotate,rotatex")
10221 (set (attr "length_immediate")
10223 (and (eq_attr "type" "rotate")
10224 (and (match_operand 2 "const1_operand" "")
10225 (ior (match_test "TARGET_SHIFT1")
10226 (match_test "optimize_function_for_size_p (cfun)"))))
10228 (const_string "*")))
10229 (set_attr "mode" "SI")])
10231 ;; Convert rotate to the rotatex pattern to avoid flags dependency.
10233 [(set (match_operand:DI 0 "register_operand" "")
10235 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "")
10236 (match_operand:QI 2 "immediate_operand" ""))))
10237 (clobber (reg:CC FLAGS_REG))]
10238 "TARGET_64BIT && TARGET_BMI2 && reload_completed"
10239 [(set (match_dup 0)
10240 (zero_extend:DI (rotatert:SI (match_dup 1) (match_dup 2))))]
10243 = GEN_INT (GET_MODE_BITSIZE (SImode) - INTVAL (operands[2]));
10247 [(set (match_operand:DI 0 "register_operand" "")
10249 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "")
10250 (match_operand:QI 2 "immediate_operand" ""))))
10251 (clobber (reg:CC FLAGS_REG))]
10252 "TARGET_64BIT && TARGET_BMI2 && reload_completed"
10253 [(set (match_dup 0)
10254 (zero_extend:DI (rotatert:SI (match_dup 1) (match_dup 2))))])
10256 (define_insn "*<rotate_insn><mode>3_1"
10257 [(set (match_operand:SWI12 0 "nonimmediate_operand" "=<r>m")
10258 (any_rotate:SWI12 (match_operand:SWI12 1 "nonimmediate_operand" "0")
10259 (match_operand:QI 2 "nonmemory_operand" "c<S>")))
10260 (clobber (reg:CC FLAGS_REG))]
10261 "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
10263 if (operands[2] == const1_rtx
10264 && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
10265 return "<rotate>{<imodesuffix>}\t%0";
10267 return "<rotate>{<imodesuffix>}\t{%2, %0|%0, %2}";
10269 [(set_attr "type" "rotate")
10270 (set (attr "length_immediate")
10272 (and (match_operand 2 "const1_operand" "")
10273 (ior (match_test "TARGET_SHIFT1")
10274 (match_test "optimize_function_for_size_p (cfun)")))
10276 (const_string "*")))
10277 (set_attr "mode" "<MODE>")])
10279 (define_insn "*<rotate_insn>qi3_1_slp"
10280 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
10281 (any_rotate:QI (match_dup 0)
10282 (match_operand:QI 1 "nonmemory_operand" "cI")))
10283 (clobber (reg:CC FLAGS_REG))]
10284 "(optimize_function_for_size_p (cfun)
10285 || !TARGET_PARTIAL_REG_STALL
10286 || (operands[1] == const1_rtx
10287 && TARGET_SHIFT1))"
10289 if (operands[1] == const1_rtx
10290 && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
10291 return "<rotate>{b}\t%0";
10293 return "<rotate>{b}\t{%1, %0|%0, %1}";
10295 [(set_attr "type" "rotate1")
10296 (set (attr "length_immediate")
10298 (and (match_operand 1 "const1_operand" "")
10299 (ior (match_test "TARGET_SHIFT1")
10300 (match_test "optimize_function_for_size_p (cfun)")))
10302 (const_string "*")))
10303 (set_attr "mode" "QI")])
10306 [(set (match_operand:HI 0 "register_operand" "")
10307 (any_rotate:HI (match_dup 0) (const_int 8)))
10308 (clobber (reg:CC FLAGS_REG))]
10310 && (TARGET_USE_XCHGB || optimize_function_for_size_p (cfun))"
10311 [(parallel [(set (strict_low_part (match_dup 0))
10312 (bswap:HI (match_dup 0)))
10313 (clobber (reg:CC FLAGS_REG))])])
10315 ;; Bit set / bit test instructions
10317 (define_expand "extv"
10318 [(set (match_operand:SI 0 "register_operand" "")
10319 (sign_extract:SI (match_operand:SI 1 "register_operand" "")
10320 (match_operand:SI 2 "const8_operand" "")
10321 (match_operand:SI 3 "const8_operand" "")))]
10324 /* Handle extractions from %ah et al. */
10325 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
10328 /* From mips.md: extract_bit_field doesn't verify that our source
10329 matches the predicate, so check it again here. */
10330 if (! ext_register_operand (operands[1], VOIDmode))
10334 (define_expand "extzv"
10335 [(set (match_operand:SI 0 "register_operand" "")
10336 (zero_extract:SI (match_operand 1 "ext_register_operand" "")
10337 (match_operand:SI 2 "const8_operand" "")
10338 (match_operand:SI 3 "const8_operand" "")))]
10341 /* Handle extractions from %ah et al. */
10342 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
10345 /* From mips.md: extract_bit_field doesn't verify that our source
10346 matches the predicate, so check it again here. */
10347 if (! ext_register_operand (operands[1], VOIDmode))
10351 (define_expand "insv"
10352 [(set (zero_extract (match_operand 0 "register_operand" "")
10353 (match_operand 1 "const_int_operand" "")
10354 (match_operand 2 "const_int_operand" ""))
10355 (match_operand 3 "register_operand" ""))]
10358 rtx (*gen_mov_insv_1) (rtx, rtx);
10360 if (ix86_expand_pinsr (operands))
10363 /* Handle insertions to %ah et al. */
10364 if (INTVAL (operands[1]) != 8 || INTVAL (operands[2]) != 8)
10367 /* From mips.md: insert_bit_field doesn't verify that our source
10368 matches the predicate, so check it again here. */
10369 if (! ext_register_operand (operands[0], VOIDmode))
10372 gen_mov_insv_1 = (TARGET_64BIT
10373 ? gen_movdi_insv_1 : gen_movsi_insv_1);
10375 emit_insn (gen_mov_insv_1 (operands[0], operands[3]));
10379 ;; %%% bts, btr, btc, bt.
10380 ;; In general these instructions are *slow* when applied to memory,
10381 ;; since they enforce atomic operation. When applied to registers,
10382 ;; it depends on the cpu implementation. They're never faster than
10383 ;; the corresponding and/ior/xor operations, so with 32-bit there's
10384 ;; no point. But in 64-bit, we can't hold the relevant immediates
10385 ;; within the instruction itself, so operating on bits in the high
10386 ;; 32-bits of a register becomes easier.
10388 ;; These are slow on Nocona, but fast on Athlon64. We do require the use
10389 ;; of btrq and btcq for corner cases of post-reload expansion of absdf and
10390 ;; negdf respectively, so they can never be disabled entirely.
10392 (define_insn "*btsq"
10393 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
10395 (match_operand:DI 1 "const_0_to_63_operand" ""))
10397 (clobber (reg:CC FLAGS_REG))]
10398 "TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
10399 "bts{q}\t{%1, %0|%0, %1}"
10400 [(set_attr "type" "alu1")
10401 (set_attr "prefix_0f" "1")
10402 (set_attr "mode" "DI")])
10404 (define_insn "*btrq"
10405 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
10407 (match_operand:DI 1 "const_0_to_63_operand" ""))
10409 (clobber (reg:CC FLAGS_REG))]
10410 "TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
10411 "btr{q}\t{%1, %0|%0, %1}"
10412 [(set_attr "type" "alu1")
10413 (set_attr "prefix_0f" "1")
10414 (set_attr "mode" "DI")])
10416 (define_insn "*btcq"
10417 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
10419 (match_operand:DI 1 "const_0_to_63_operand" ""))
10420 (not:DI (zero_extract:DI (match_dup 0) (const_int 1) (match_dup 1))))
10421 (clobber (reg:CC FLAGS_REG))]
10422 "TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
10423 "btc{q}\t{%1, %0|%0, %1}"
10424 [(set_attr "type" "alu1")
10425 (set_attr "prefix_0f" "1")
10426 (set_attr "mode" "DI")])
10428 ;; Allow Nocona to avoid these instructions if a register is available.
10431 [(match_scratch:DI 2 "r")
10432 (parallel [(set (zero_extract:DI
10433 (match_operand:DI 0 "register_operand" "")
10435 (match_operand:DI 1 "const_0_to_63_operand" ""))
10437 (clobber (reg:CC FLAGS_REG))])]
10438 "TARGET_64BIT && !TARGET_USE_BT"
10441 HOST_WIDE_INT i = INTVAL (operands[1]), hi, lo;
10444 if (HOST_BITS_PER_WIDE_INT >= 64)
10445 lo = (HOST_WIDE_INT)1 << i, hi = 0;
10446 else if (i < HOST_BITS_PER_WIDE_INT)
10447 lo = (HOST_WIDE_INT)1 << i, hi = 0;
10449 lo = 0, hi = (HOST_WIDE_INT)1 << (i - HOST_BITS_PER_WIDE_INT);
10451 op1 = immed_double_const (lo, hi, DImode);
10454 emit_move_insn (operands[2], op1);
10458 emit_insn (gen_iordi3 (operands[0], operands[0], op1));
10463 [(match_scratch:DI 2 "r")
10464 (parallel [(set (zero_extract:DI
10465 (match_operand:DI 0 "register_operand" "")
10467 (match_operand:DI 1 "const_0_to_63_operand" ""))
10469 (clobber (reg:CC FLAGS_REG))])]
10470 "TARGET_64BIT && !TARGET_USE_BT"
10473 HOST_WIDE_INT i = INTVAL (operands[1]), hi, lo;
10476 if (HOST_BITS_PER_WIDE_INT >= 64)
10477 lo = (HOST_WIDE_INT)1 << i, hi = 0;
10478 else if (i < HOST_BITS_PER_WIDE_INT)
10479 lo = (HOST_WIDE_INT)1 << i, hi = 0;
10481 lo = 0, hi = (HOST_WIDE_INT)1 << (i - HOST_BITS_PER_WIDE_INT);
10483 op1 = immed_double_const (~lo, ~hi, DImode);
10486 emit_move_insn (operands[2], op1);
10490 emit_insn (gen_anddi3 (operands[0], operands[0], op1));
10495 [(match_scratch:DI 2 "r")
10496 (parallel [(set (zero_extract:DI
10497 (match_operand:DI 0 "register_operand" "")
10499 (match_operand:DI 1 "const_0_to_63_operand" ""))
10500 (not:DI (zero_extract:DI
10501 (match_dup 0) (const_int 1) (match_dup 1))))
10502 (clobber (reg:CC FLAGS_REG))])]
10503 "TARGET_64BIT && !TARGET_USE_BT"
10506 HOST_WIDE_INT i = INTVAL (operands[1]), hi, lo;
10509 if (HOST_BITS_PER_WIDE_INT >= 64)
10510 lo = (HOST_WIDE_INT)1 << i, hi = 0;
10511 else if (i < HOST_BITS_PER_WIDE_INT)
10512 lo = (HOST_WIDE_INT)1 << i, hi = 0;
10514 lo = 0, hi = (HOST_WIDE_INT)1 << (i - HOST_BITS_PER_WIDE_INT);
10516 op1 = immed_double_const (lo, hi, DImode);
10519 emit_move_insn (operands[2], op1);
10523 emit_insn (gen_xordi3 (operands[0], operands[0], op1));
10527 (define_insn "*bt<mode>"
10528 [(set (reg:CCC FLAGS_REG)
10530 (zero_extract:SWI48
10531 (match_operand:SWI48 0 "register_operand" "r")
10533 (match_operand:SWI48 1 "x86_64_nonmemory_operand" "rN"))
10535 "TARGET_USE_BT || optimize_function_for_size_p (cfun)"
10536 "bt{<imodesuffix>}\t{%1, %0|%0, %1}"
10537 [(set_attr "type" "alu1")
10538 (set_attr "prefix_0f" "1")
10539 (set_attr "mode" "<MODE>")])
10541 ;; Store-flag instructions.
10543 ;; For all sCOND expanders, also expand the compare or test insn that
10544 ;; generates cc0. Generate an equality comparison if `seq' or `sne'.
10546 (define_insn_and_split "*setcc_di_1"
10547 [(set (match_operand:DI 0 "register_operand" "=q")
10548 (match_operator:DI 1 "ix86_comparison_operator"
10549 [(reg FLAGS_REG) (const_int 0)]))]
10550 "TARGET_64BIT && !TARGET_PARTIAL_REG_STALL"
10552 "&& reload_completed"
10553 [(set (match_dup 2) (match_dup 1))
10554 (set (match_dup 0) (zero_extend:DI (match_dup 2)))]
10556 PUT_MODE (operands[1], QImode);
10557 operands[2] = gen_lowpart (QImode, operands[0]);
10560 (define_insn_and_split "*setcc_si_1_and"
10561 [(set (match_operand:SI 0 "register_operand" "=q")
10562 (match_operator:SI 1 "ix86_comparison_operator"
10563 [(reg FLAGS_REG) (const_int 0)]))
10564 (clobber (reg:CC FLAGS_REG))]
10565 "!TARGET_PARTIAL_REG_STALL
10566 && TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun)"
10568 "&& reload_completed"
10569 [(set (match_dup 2) (match_dup 1))
10570 (parallel [(set (match_dup 0) (zero_extend:SI (match_dup 2)))
10571 (clobber (reg:CC FLAGS_REG))])]
10573 PUT_MODE (operands[1], QImode);
10574 operands[2] = gen_lowpart (QImode, operands[0]);
10577 (define_insn_and_split "*setcc_si_1_movzbl"
10578 [(set (match_operand:SI 0 "register_operand" "=q")
10579 (match_operator:SI 1 "ix86_comparison_operator"
10580 [(reg FLAGS_REG) (const_int 0)]))]
10581 "!TARGET_PARTIAL_REG_STALL
10582 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_function_for_size_p (cfun))"
10584 "&& reload_completed"
10585 [(set (match_dup 2) (match_dup 1))
10586 (set (match_dup 0) (zero_extend:SI (match_dup 2)))]
10588 PUT_MODE (operands[1], QImode);
10589 operands[2] = gen_lowpart (QImode, operands[0]);
10592 (define_insn "*setcc_qi"
10593 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
10594 (match_operator:QI 1 "ix86_comparison_operator"
10595 [(reg FLAGS_REG) (const_int 0)]))]
10598 [(set_attr "type" "setcc")
10599 (set_attr "mode" "QI")])
10601 (define_insn "*setcc_qi_slp"
10602 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
10603 (match_operator:QI 1 "ix86_comparison_operator"
10604 [(reg FLAGS_REG) (const_int 0)]))]
10607 [(set_attr "type" "setcc")
10608 (set_attr "mode" "QI")])
10610 ;; In general it is not safe to assume too much about CCmode registers,
10611 ;; so simplify-rtx stops when it sees a second one. Under certain
10612 ;; conditions this is safe on x86, so help combine not create
10619 [(set (match_operand:QI 0 "nonimmediate_operand" "")
10620 (ne:QI (match_operator 1 "ix86_comparison_operator"
10621 [(reg FLAGS_REG) (const_int 0)])
10624 [(set (match_dup 0) (match_dup 1))]
10625 "PUT_MODE (operands[1], QImode);")
10628 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
10629 (ne:QI (match_operator 1 "ix86_comparison_operator"
10630 [(reg FLAGS_REG) (const_int 0)])
10633 [(set (match_dup 0) (match_dup 1))]
10634 "PUT_MODE (operands[1], QImode);")
10637 [(set (match_operand:QI 0 "nonimmediate_operand" "")
10638 (eq:QI (match_operator 1 "ix86_comparison_operator"
10639 [(reg FLAGS_REG) (const_int 0)])
10642 [(set (match_dup 0) (match_dup 1))]
10644 rtx new_op1 = copy_rtx (operands[1]);
10645 operands[1] = new_op1;
10646 PUT_MODE (new_op1, QImode);
10647 PUT_CODE (new_op1, ix86_reverse_condition (GET_CODE (new_op1),
10648 GET_MODE (XEXP (new_op1, 0))));
10650 /* Make sure that (a) the CCmode we have for the flags is strong
10651 enough for the reversed compare or (b) we have a valid FP compare. */
10652 if (! ix86_comparison_operator (new_op1, VOIDmode))
10657 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
10658 (eq:QI (match_operator 1 "ix86_comparison_operator"
10659 [(reg FLAGS_REG) (const_int 0)])
10662 [(set (match_dup 0) (match_dup 1))]
10664 rtx new_op1 = copy_rtx (operands[1]);
10665 operands[1] = new_op1;
10666 PUT_MODE (new_op1, QImode);
10667 PUT_CODE (new_op1, ix86_reverse_condition (GET_CODE (new_op1),
10668 GET_MODE (XEXP (new_op1, 0))));
10670 /* Make sure that (a) the CCmode we have for the flags is strong
10671 enough for the reversed compare or (b) we have a valid FP compare. */
10672 if (! ix86_comparison_operator (new_op1, VOIDmode))
10676 ;; The SSE store flag instructions saves 0 or 0xffffffff to the result.
10677 ;; subsequent logical operations are used to imitate conditional moves.
10678 ;; 0xffffffff is NaN, but not in normalized form, so we can't represent
10681 (define_insn "setcc_<mode>_sse"
10682 [(set (match_operand:MODEF 0 "register_operand" "=x,x")
10683 (match_operator:MODEF 3 "sse_comparison_operator"
10684 [(match_operand:MODEF 1 "register_operand" "0,x")
10685 (match_operand:MODEF 2 "nonimmediate_operand" "xm,xm")]))]
10686 "SSE_FLOAT_MODE_P (<MODE>mode)"
10688 cmp%D3<ssemodesuffix>\t{%2, %0|%0, %2}
10689 vcmp%D3<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
10690 [(set_attr "isa" "noavx,avx")
10691 (set_attr "type" "ssecmp")
10692 (set_attr "length_immediate" "1")
10693 (set_attr "prefix" "orig,vex")
10694 (set_attr "mode" "<MODE>")])
10696 ;; Basic conditional jump instructions.
10697 ;; We ignore the overflow flag for signed branch instructions.
10699 (define_insn "*jcc_1"
10701 (if_then_else (match_operator 1 "ix86_comparison_operator"
10702 [(reg FLAGS_REG) (const_int 0)])
10703 (label_ref (match_operand 0 "" ""))
10707 [(set_attr "type" "ibr")
10708 (set_attr "modrm" "0")
10709 (set (attr "length")
10710 (if_then_else (and (ge (minus (match_dup 0) (pc))
10712 (lt (minus (match_dup 0) (pc))
10717 (define_insn "*jcc_2"
10719 (if_then_else (match_operator 1 "ix86_comparison_operator"
10720 [(reg FLAGS_REG) (const_int 0)])
10722 (label_ref (match_operand 0 "" ""))))]
10725 [(set_attr "type" "ibr")
10726 (set_attr "modrm" "0")
10727 (set (attr "length")
10728 (if_then_else (and (ge (minus (match_dup 0) (pc))
10730 (lt (minus (match_dup 0) (pc))
10735 ;; In general it is not safe to assume too much about CCmode registers,
10736 ;; so simplify-rtx stops when it sees a second one. Under certain
10737 ;; conditions this is safe on x86, so help combine not create
10745 (if_then_else (ne (match_operator 0 "ix86_comparison_operator"
10746 [(reg FLAGS_REG) (const_int 0)])
10748 (label_ref (match_operand 1 "" ""))
10752 (if_then_else (match_dup 0)
10753 (label_ref (match_dup 1))
10755 "PUT_MODE (operands[0], VOIDmode);")
10759 (if_then_else (eq (match_operator 0 "ix86_comparison_operator"
10760 [(reg FLAGS_REG) (const_int 0)])
10762 (label_ref (match_operand 1 "" ""))
10766 (if_then_else (match_dup 0)
10767 (label_ref (match_dup 1))
10770 rtx new_op0 = copy_rtx (operands[0]);
10771 operands[0] = new_op0;
10772 PUT_MODE (new_op0, VOIDmode);
10773 PUT_CODE (new_op0, ix86_reverse_condition (GET_CODE (new_op0),
10774 GET_MODE (XEXP (new_op0, 0))));
10776 /* Make sure that (a) the CCmode we have for the flags is strong
10777 enough for the reversed compare or (b) we have a valid FP compare. */
10778 if (! ix86_comparison_operator (new_op0, VOIDmode))
10782 ;; zero_extend in SImode is correct also for DImode, since this is what combine
10783 ;; pass generates from shift insn with QImode operand. Actually, the mode
10784 ;; of operand 2 (bit offset operand) doesn't matter since bt insn takes
10785 ;; appropriate modulo of the bit offset value.
10787 (define_insn_and_split "*jcc_bt<mode>"
10789 (if_then_else (match_operator 0 "bt_comparison_operator"
10790 [(zero_extract:SWI48
10791 (match_operand:SWI48 1 "register_operand" "r")
10794 (match_operand:QI 2 "register_operand" "r")))
10796 (label_ref (match_operand 3 "" ""))
10798 (clobber (reg:CC FLAGS_REG))]
10799 "TARGET_USE_BT || optimize_function_for_size_p (cfun)"
10802 [(set (reg:CCC FLAGS_REG)
10804 (zero_extract:SWI48
10810 (if_then_else (match_op_dup 0 [(reg:CCC FLAGS_REG) (const_int 0)])
10811 (label_ref (match_dup 3))
10814 operands[2] = simplify_gen_subreg (<MODE>mode, operands[2], QImode, 0);
10816 PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0])));
10819 ;; Avoid useless masking of bit offset operand. "and" in SImode is correct
10820 ;; also for DImode, this is what combine produces.
10821 (define_insn_and_split "*jcc_bt<mode>_mask"
10823 (if_then_else (match_operator 0 "bt_comparison_operator"
10824 [(zero_extract:SWI48
10825 (match_operand:SWI48 1 "register_operand" "r")
10828 (match_operand:SI 2 "register_operand" "r")
10829 (match_operand:SI 3 "const_int_operand" "n")))])
10830 (label_ref (match_operand 4 "" ""))
10832 (clobber (reg:CC FLAGS_REG))]
10833 "(TARGET_USE_BT || optimize_function_for_size_p (cfun))
10834 && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1))
10835 == GET_MODE_BITSIZE (<MODE>mode)-1"
10838 [(set (reg:CCC FLAGS_REG)
10840 (zero_extract:SWI48
10846 (if_then_else (match_op_dup 0 [(reg:CCC FLAGS_REG) (const_int 0)])
10847 (label_ref (match_dup 4))
10850 operands[2] = simplify_gen_subreg (<MODE>mode, operands[2], SImode, 0);
10852 PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0])));
10855 (define_insn_and_split "*jcc_btsi_1"
10857 (if_then_else (match_operator 0 "bt_comparison_operator"
10860 (match_operand:SI 1 "register_operand" "r")
10861 (match_operand:QI 2 "register_operand" "r"))
10864 (label_ref (match_operand 3 "" ""))
10866 (clobber (reg:CC FLAGS_REG))]
10867 "TARGET_USE_BT || optimize_function_for_size_p (cfun)"
10870 [(set (reg:CCC FLAGS_REG)
10878 (if_then_else (match_op_dup 0 [(reg:CCC FLAGS_REG) (const_int 0)])
10879 (label_ref (match_dup 3))
10882 operands[2] = simplify_gen_subreg (SImode, operands[2], QImode, 0);
10884 PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0])));
10887 ;; avoid useless masking of bit offset operand
10888 (define_insn_and_split "*jcc_btsi_mask_1"
10891 (match_operator 0 "bt_comparison_operator"
10894 (match_operand:SI 1 "register_operand" "r")
10897 (match_operand:SI 2 "register_operand" "r")
10898 (match_operand:SI 3 "const_int_operand" "n")) 0))
10901 (label_ref (match_operand 4 "" ""))
10903 (clobber (reg:CC FLAGS_REG))]
10904 "(TARGET_USE_BT || optimize_function_for_size_p (cfun))
10905 && (INTVAL (operands[3]) & 0x1f) == 0x1f"
10908 [(set (reg:CCC FLAGS_REG)
10916 (if_then_else (match_op_dup 0 [(reg:CCC FLAGS_REG) (const_int 0)])
10917 (label_ref (match_dup 4))
10919 "PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0])));")
10921 ;; Define combination compare-and-branch fp compare instructions to help
10924 (define_insn "*fp_jcc_1_387"
10926 (if_then_else (match_operator 0 "ix86_fp_comparison_operator"
10927 [(match_operand 1 "register_operand" "f")
10928 (match_operand 2 "nonimmediate_operand" "fm")])
10929 (label_ref (match_operand 3 "" ""))
10931 (clobber (reg:CCFP FPSR_REG))
10932 (clobber (reg:CCFP FLAGS_REG))
10933 (clobber (match_scratch:HI 4 "=a"))]
10935 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
10936 && GET_MODE (operands[1]) == GET_MODE (operands[2])
10937 && SELECT_CC_MODE (GET_CODE (operands[0]),
10938 operands[1], operands[2]) == CCFPmode
10942 (define_insn "*fp_jcc_1r_387"
10944 (if_then_else (match_operator 0 "ix86_fp_comparison_operator"
10945 [(match_operand 1 "register_operand" "f")
10946 (match_operand 2 "nonimmediate_operand" "fm")])
10948 (label_ref (match_operand 3 "" ""))))
10949 (clobber (reg:CCFP FPSR_REG))
10950 (clobber (reg:CCFP FLAGS_REG))
10951 (clobber (match_scratch:HI 4 "=a"))]
10953 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
10954 && GET_MODE (operands[1]) == GET_MODE (operands[2])
10955 && SELECT_CC_MODE (GET_CODE (operands[0]),
10956 operands[1], operands[2]) == CCFPmode
10960 (define_insn "*fp_jcc_2_387"
10962 (if_then_else (match_operator 0 "ix86_fp_comparison_operator"
10963 [(match_operand 1 "register_operand" "f")
10964 (match_operand 2 "register_operand" "f")])
10965 (label_ref (match_operand 3 "" ""))
10967 (clobber (reg:CCFP FPSR_REG))
10968 (clobber (reg:CCFP FLAGS_REG))
10969 (clobber (match_scratch:HI 4 "=a"))]
10970 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
10971 && GET_MODE (operands[1]) == GET_MODE (operands[2])
10975 (define_insn "*fp_jcc_2r_387"
10977 (if_then_else (match_operator 0 "ix86_fp_comparison_operator"
10978 [(match_operand 1 "register_operand" "f")
10979 (match_operand 2 "register_operand" "f")])
10981 (label_ref (match_operand 3 "" ""))))
10982 (clobber (reg:CCFP FPSR_REG))
10983 (clobber (reg:CCFP FLAGS_REG))
10984 (clobber (match_scratch:HI 4 "=a"))]
10985 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
10986 && GET_MODE (operands[1]) == GET_MODE (operands[2])
10990 (define_insn "*fp_jcc_3_387"
10992 (if_then_else (match_operator 0 "ix86_fp_comparison_operator"
10993 [(match_operand 1 "register_operand" "f")
10994 (match_operand 2 "const0_operand" "")])
10995 (label_ref (match_operand 3 "" ""))
10997 (clobber (reg:CCFP FPSR_REG))
10998 (clobber (reg:CCFP FLAGS_REG))
10999 (clobber (match_scratch:HI 4 "=a"))]
11000 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
11001 && GET_MODE (operands[1]) == GET_MODE (operands[2])
11002 && SELECT_CC_MODE (GET_CODE (operands[0]),
11003 operands[1], operands[2]) == CCFPmode
11009 (if_then_else (match_operator 0 "ix86_fp_comparison_operator"
11010 [(match_operand 1 "register_operand" "")
11011 (match_operand 2 "nonimmediate_operand" "")])
11012 (match_operand 3 "" "")
11013 (match_operand 4 "" "")))
11014 (clobber (reg:CCFP FPSR_REG))
11015 (clobber (reg:CCFP FLAGS_REG))]
11019 ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2],
11020 operands[3], operands[4], NULL_RTX, NULL_RTX);
11026 (if_then_else (match_operator 0 "ix86_fp_comparison_operator"
11027 [(match_operand 1 "register_operand" "")
11028 (match_operand 2 "general_operand" "")])
11029 (match_operand 3 "" "")
11030 (match_operand 4 "" "")))
11031 (clobber (reg:CCFP FPSR_REG))
11032 (clobber (reg:CCFP FLAGS_REG))
11033 (clobber (match_scratch:HI 5 "=a"))]
11037 ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2],
11038 operands[3], operands[4], operands[5], NULL_RTX);
11042 ;; The order of operands in *fp_jcc_4_387 is forced by combine in
11043 ;; simplify_comparison () function. Float operator is treated as RTX_OBJ
11044 ;; with a precedence over other operators and is always put in the first
11045 ;; place. Swap condition and operands to match ficom instruction.
11047 (define_insn "*fp_jcc_4_<mode>_387"
11050 (match_operator 0 "ix86_swapped_fp_comparison_operator"
11051 [(match_operator 1 "float_operator"
11052 [(match_operand:SWI24 2 "nonimmediate_operand" "m,?r")])
11053 (match_operand 3 "register_operand" "f,f")])
11054 (label_ref (match_operand 4 "" ""))
11056 (clobber (reg:CCFP FPSR_REG))
11057 (clobber (reg:CCFP FLAGS_REG))
11058 (clobber (match_scratch:HI 5 "=a,a"))]
11059 "X87_FLOAT_MODE_P (GET_MODE (operands[3]))
11060 && (TARGET_USE_<MODE>MODE_FIOP || optimize_function_for_size_p (cfun))
11061 && GET_MODE (operands[1]) == GET_MODE (operands[3])
11062 && ix86_fp_compare_mode (swap_condition (GET_CODE (operands[0]))) == CCFPmode
11069 (match_operator 0 "ix86_swapped_fp_comparison_operator"
11070 [(match_operator 1 "float_operator"
11071 [(match_operand:SWI24 2 "memory_operand" "")])
11072 (match_operand 3 "register_operand" "")])
11073 (match_operand 4 "" "")
11074 (match_operand 5 "" "")))
11075 (clobber (reg:CCFP FPSR_REG))
11076 (clobber (reg:CCFP FLAGS_REG))
11077 (clobber (match_scratch:HI 6 "=a"))]
11081 operands[7] = gen_rtx_FLOAT (GET_MODE (operands[1]), operands[2]);
11083 ix86_split_fp_branch (swap_condition (GET_CODE (operands[0])),
11084 operands[3], operands[7],
11085 operands[4], operands[5], operands[6], NULL_RTX);
11089 ;; %%% Kill this when reload knows how to do it.
11093 (match_operator 0 "ix86_swapped_fp_comparison_operator"
11094 [(match_operator 1 "float_operator"
11095 [(match_operand:SWI24 2 "register_operand" "")])
11096 (match_operand 3 "register_operand" "")])
11097 (match_operand 4 "" "")
11098 (match_operand 5 "" "")))
11099 (clobber (reg:CCFP FPSR_REG))
11100 (clobber (reg:CCFP FLAGS_REG))
11101 (clobber (match_scratch:HI 6 "=a"))]
11105 operands[7] = ix86_force_to_memory (GET_MODE (operands[2]), operands[2]);
11106 operands[7] = gen_rtx_FLOAT (GET_MODE (operands[1]), operands[7]);
11108 ix86_split_fp_branch (swap_condition (GET_CODE (operands[0])),
11109 operands[3], operands[7],
11110 operands[4], operands[5], operands[6], operands[2]);
11114 ;; Unconditional and other jump instructions
11116 (define_insn "jump"
11118 (label_ref (match_operand 0 "" "")))]
11121 [(set_attr "type" "ibr")
11122 (set (attr "length")
11123 (if_then_else (and (ge (minus (match_dup 0) (pc))
11125 (lt (minus (match_dup 0) (pc))
11129 (set_attr "modrm" "0")])
11131 (define_expand "indirect_jump"
11132 [(set (pc) (match_operand 0 "indirect_branch_operand" ""))])
11134 (define_insn "*indirect_jump"
11135 [(set (pc) (match_operand:P 0 "indirect_branch_operand" "rw"))]
11138 [(set_attr "type" "ibr")
11139 (set_attr "length_immediate" "0")])
11141 (define_expand "tablejump"
11142 [(parallel [(set (pc) (match_operand 0 "indirect_branch_operand" ""))
11143 (use (label_ref (match_operand 1 "" "")))])]
11146 /* In PIC mode, the table entries are stored GOT (32-bit) or PC (64-bit)
11147 relative. Convert the relative address to an absolute address. */
11151 enum rtx_code code;
11153 /* We can't use @GOTOFF for text labels on VxWorks;
11154 see gotoff_operand. */
11155 if (TARGET_64BIT || TARGET_VXWORKS_RTP)
11159 op1 = gen_rtx_LABEL_REF (Pmode, operands[1]);
11161 else if (TARGET_MACHO || HAVE_AS_GOTOFF_IN_DATA)
11165 op1 = pic_offset_table_rtx;
11170 op0 = pic_offset_table_rtx;
11174 operands[0] = expand_simple_binop (Pmode, code, op0, op1, NULL_RTX, 0,
11177 else if (TARGET_X32)
11178 operands[0] = convert_memory_address (Pmode, operands[0]);
11181 (define_insn "*tablejump_1"
11182 [(set (pc) (match_operand:P 0 "indirect_branch_operand" "rw"))
11183 (use (label_ref (match_operand 1 "" "")))]
11186 [(set_attr "type" "ibr")
11187 (set_attr "length_immediate" "0")])
11189 ;; Convert setcc + movzbl to xor + setcc if operands don't overlap.
11192 [(set (reg FLAGS_REG) (match_operand 0 "" ""))
11193 (set (match_operand:QI 1 "register_operand" "")
11194 (match_operator:QI 2 "ix86_comparison_operator"
11195 [(reg FLAGS_REG) (const_int 0)]))
11196 (set (match_operand 3 "q_regs_operand" "")
11197 (zero_extend (match_dup 1)))]
11198 "(peep2_reg_dead_p (3, operands[1])
11199 || operands_match_p (operands[1], operands[3]))
11200 && ! reg_overlap_mentioned_p (operands[3], operands[0])"
11201 [(set (match_dup 4) (match_dup 0))
11202 (set (strict_low_part (match_dup 5))
11205 operands[4] = gen_rtx_REG (GET_MODE (operands[0]), FLAGS_REG);
11206 operands[5] = gen_lowpart (QImode, operands[3]);
11207 ix86_expand_clear (operands[3]);
11210 ;; Similar, but match zero_extendhisi2_and, which adds a clobber.
11213 [(set (reg FLAGS_REG) (match_operand 0 "" ""))
11214 (set (match_operand:QI 1 "register_operand" "")
11215 (match_operator:QI 2 "ix86_comparison_operator"
11216 [(reg FLAGS_REG) (const_int 0)]))
11217 (parallel [(set (match_operand 3 "q_regs_operand" "")
11218 (zero_extend (match_dup 1)))
11219 (clobber (reg:CC FLAGS_REG))])]
11220 "(peep2_reg_dead_p (3, operands[1])
11221 || operands_match_p (operands[1], operands[3]))
11222 && ! reg_overlap_mentioned_p (operands[3], operands[0])"
11223 [(set (match_dup 4) (match_dup 0))
11224 (set (strict_low_part (match_dup 5))
11227 operands[4] = gen_rtx_REG (GET_MODE (operands[0]), FLAGS_REG);
11228 operands[5] = gen_lowpart (QImode, operands[3]);
11229 ix86_expand_clear (operands[3]);
11232 ;; Call instructions.
11234 ;; The predicates normally associated with named expanders are not properly
11235 ;; checked for calls. This is a bug in the generic code, but it isn't that
11236 ;; easy to fix. Ignore it for now and be prepared to fix things up.
11238 ;; P6 processors will jump to the address after the decrement when %esp
11239 ;; is used as a call operand, so they will execute return address as a code.
11240 ;; See Pentium Pro errata 70, Pentium 2 errata A33 and Pentium 3 errata E17.
11242 ;; Register constraint for call instruction.
11243 (define_mode_attr c [(SI "l") (DI "r")])
11245 ;; Call subroutine returning no value.
11247 (define_expand "call"
11248 [(call (match_operand:QI 0 "" "")
11249 (match_operand 1 "" ""))
11250 (use (match_operand 2 "" ""))]
11253 ix86_expand_call (NULL, operands[0], operands[1],
11254 operands[2], NULL, false);
11258 (define_expand "sibcall"
11259 [(call (match_operand:QI 0 "" "")
11260 (match_operand 1 "" ""))
11261 (use (match_operand 2 "" ""))]
11264 ix86_expand_call (NULL, operands[0], operands[1],
11265 operands[2], NULL, true);
11269 (define_insn_and_split "*call_vzeroupper"
11270 [(call (mem:QI (match_operand:P 0 "call_insn_operand" "<c>zw"))
11271 (match_operand 1 "" ""))
11272 (unspec [(match_operand 2 "const_int_operand" "")]
11273 UNSPEC_CALL_NEEDS_VZEROUPPER)]
11274 "TARGET_VZEROUPPER && !SIBLING_CALL_P (insn)"
11276 "&& reload_completed"
11278 "ix86_split_call_vzeroupper (curr_insn, operands[2]); DONE;"
11279 [(set_attr "type" "call")])
11281 (define_insn "*call"
11282 [(call (mem:QI (match_operand:P 0 "call_insn_operand" "<c>zw"))
11283 (match_operand 1 "" ""))]
11284 "!SIBLING_CALL_P (insn)"
11285 "* return ix86_output_call_insn (insn, operands[0]);"
11286 [(set_attr "type" "call")])
11288 (define_insn_and_split "*call_rex64_ms_sysv_vzeroupper"
11289 [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rzw"))
11290 (match_operand 1 "" ""))
11291 (unspec [(const_int 0)] UNSPEC_MS_TO_SYSV_CALL)
11292 (clobber (reg:TI XMM6_REG))
11293 (clobber (reg:TI XMM7_REG))
11294 (clobber (reg:TI XMM8_REG))
11295 (clobber (reg:TI XMM9_REG))
11296 (clobber (reg:TI XMM10_REG))
11297 (clobber (reg:TI XMM11_REG))
11298 (clobber (reg:TI XMM12_REG))
11299 (clobber (reg:TI XMM13_REG))
11300 (clobber (reg:TI XMM14_REG))
11301 (clobber (reg:TI XMM15_REG))
11302 (clobber (reg:DI SI_REG))
11303 (clobber (reg:DI DI_REG))
11304 (unspec [(match_operand 2 "const_int_operand" "")]
11305 UNSPEC_CALL_NEEDS_VZEROUPPER)]
11306 "TARGET_VZEROUPPER && TARGET_64BIT && !SIBLING_CALL_P (insn)"
11308 "&& reload_completed"
11310 "ix86_split_call_vzeroupper (curr_insn, operands[2]); DONE;"
11311 [(set_attr "type" "call")])
11313 (define_insn "*call_rex64_ms_sysv"
11314 [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rzw"))
11315 (match_operand 1 "" ""))
11316 (unspec [(const_int 0)] UNSPEC_MS_TO_SYSV_CALL)
11317 (clobber (reg:TI XMM6_REG))
11318 (clobber (reg:TI XMM7_REG))
11319 (clobber (reg:TI XMM8_REG))
11320 (clobber (reg:TI XMM9_REG))
11321 (clobber (reg:TI XMM10_REG))
11322 (clobber (reg:TI XMM11_REG))
11323 (clobber (reg:TI XMM12_REG))
11324 (clobber (reg:TI XMM13_REG))
11325 (clobber (reg:TI XMM14_REG))
11326 (clobber (reg:TI XMM15_REG))
11327 (clobber (reg:DI SI_REG))
11328 (clobber (reg:DI DI_REG))]
11329 "TARGET_64BIT && !SIBLING_CALL_P (insn)"
11330 "* return ix86_output_call_insn (insn, operands[0]);"
11331 [(set_attr "type" "call")])
11333 (define_insn_and_split "*sibcall_vzeroupper"
11334 [(call (mem:QI (match_operand:P 0 "sibcall_insn_operand" "Uz"))
11335 (match_operand 1 "" ""))
11336 (unspec [(match_operand 2 "const_int_operand" "")]
11337 UNSPEC_CALL_NEEDS_VZEROUPPER)]
11338 "TARGET_VZEROUPPER && SIBLING_CALL_P (insn)"
11340 "&& reload_completed"
11342 "ix86_split_call_vzeroupper (curr_insn, operands[2]); DONE;"
11343 [(set_attr "type" "call")])
11345 (define_insn "*sibcall"
11346 [(call (mem:QI (match_operand:P 0 "sibcall_insn_operand" "Uz"))
11347 (match_operand 1 "" ""))]
11348 "SIBLING_CALL_P (insn)"
11349 "* return ix86_output_call_insn (insn, operands[0]);"
11350 [(set_attr "type" "call")])
11352 (define_expand "call_pop"
11353 [(parallel [(call (match_operand:QI 0 "" "")
11354 (match_operand:SI 1 "" ""))
11355 (set (reg:SI SP_REG)
11356 (plus:SI (reg:SI SP_REG)
11357 (match_operand:SI 3 "" "")))])]
11360 ix86_expand_call (NULL, operands[0], operands[1],
11361 operands[2], operands[3], false);
11365 (define_insn_and_split "*call_pop_vzeroupper"
11366 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "lzm"))
11367 (match_operand:SI 1 "" ""))
11368 (set (reg:SI SP_REG)
11369 (plus:SI (reg:SI SP_REG)
11370 (match_operand:SI 2 "immediate_operand" "i")))
11371 (unspec [(match_operand 3 "const_int_operand" "")]
11372 UNSPEC_CALL_NEEDS_VZEROUPPER)]
11373 "TARGET_VZEROUPPER && !TARGET_64BIT && !SIBLING_CALL_P (insn)"
11375 "&& reload_completed"
11377 "ix86_split_call_vzeroupper (curr_insn, operands[3]); DONE;"
11378 [(set_attr "type" "call")])
11380 (define_insn "*call_pop"
11381 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "lzm"))
11382 (match_operand 1 "" ""))
11383 (set (reg:SI SP_REG)
11384 (plus:SI (reg:SI SP_REG)
11385 (match_operand:SI 2 "immediate_operand" "i")))]
11386 "!TARGET_64BIT && !SIBLING_CALL_P (insn)"
11387 "* return ix86_output_call_insn (insn, operands[0]);"
11388 [(set_attr "type" "call")])
11390 (define_insn_and_split "*sibcall_pop_vzeroupper"
11391 [(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "Uz"))
11392 (match_operand 1 "" ""))
11393 (set (reg:SI SP_REG)
11394 (plus:SI (reg:SI SP_REG)
11395 (match_operand:SI 2 "immediate_operand" "i")))
11396 (unspec [(match_operand 3 "const_int_operand" "")]
11397 UNSPEC_CALL_NEEDS_VZEROUPPER)]
11398 "TARGET_VZEROUPPER && !TARGET_64BIT && SIBLING_CALL_P (insn)"
11400 "&& reload_completed"
11402 "ix86_split_call_vzeroupper (curr_insn, operands[3]); DONE;"
11403 [(set_attr "type" "call")])
11405 (define_insn "*sibcall_pop"
11406 [(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "Uz"))
11407 (match_operand 1 "" ""))
11408 (set (reg:SI SP_REG)
11409 (plus:SI (reg:SI SP_REG)
11410 (match_operand:SI 2 "immediate_operand" "i")))]
11411 "!TARGET_64BIT && SIBLING_CALL_P (insn)"
11412 "* return ix86_output_call_insn (insn, operands[0]);"
11413 [(set_attr "type" "call")])
11415 ;; Call subroutine, returning value in operand 0
11417 (define_expand "call_value"
11418 [(set (match_operand 0 "" "")
11419 (call (match_operand:QI 1 "" "")
11420 (match_operand 2 "" "")))
11421 (use (match_operand 3 "" ""))]
11424 ix86_expand_call (operands[0], operands[1], operands[2],
11425 operands[3], NULL, false);
11429 (define_expand "sibcall_value"
11430 [(set (match_operand 0 "" "")
11431 (call (match_operand:QI 1 "" "")
11432 (match_operand 2 "" "")))
11433 (use (match_operand 3 "" ""))]
11436 ix86_expand_call (operands[0], operands[1], operands[2],
11437 operands[3], NULL, true);
11441 (define_insn_and_split "*call_value_vzeroupper"
11442 [(set (match_operand 0 "" "")
11443 (call (mem:QI (match_operand:P 1 "call_insn_operand" "<c>zw"))
11444 (match_operand 2 "" "")))
11445 (unspec [(match_operand 3 "const_int_operand" "")]
11446 UNSPEC_CALL_NEEDS_VZEROUPPER)]
11447 "TARGET_VZEROUPPER && !SIBLING_CALL_P (insn)"
11449 "&& reload_completed"
11451 "ix86_split_call_vzeroupper (curr_insn, operands[3]); DONE;"
11452 [(set_attr "type" "callv")])
11454 (define_insn "*call_value"
11455 [(set (match_operand 0 "" "")
11456 (call (mem:QI (match_operand:P 1 "call_insn_operand" "<c>zw"))
11457 (match_operand 2 "" "")))]
11458 "!SIBLING_CALL_P (insn)"
11459 "* return ix86_output_call_insn (insn, operands[1]);"
11460 [(set_attr "type" "callv")])
11462 (define_insn_and_split "*sibcall_value_vzeroupper"
11463 [(set (match_operand 0 "" "")
11464 (call (mem:QI (match_operand:P 1 "sibcall_insn_operand" "Uz"))
11465 (match_operand 2 "" "")))
11466 (unspec [(match_operand 3 "const_int_operand" "")]
11467 UNSPEC_CALL_NEEDS_VZEROUPPER)]
11468 "TARGET_VZEROUPPER && SIBLING_CALL_P (insn)"
11470 "&& reload_completed"
11472 "ix86_split_call_vzeroupper (curr_insn, operands[3]); DONE;"
11473 [(set_attr "type" "callv")])
11475 (define_insn "*sibcall_value"
11476 [(set (match_operand 0 "" "")
11477 (call (mem:QI (match_operand:P 1 "sibcall_insn_operand" "Uz"))
11478 (match_operand 2 "" "")))]
11479 "SIBLING_CALL_P (insn)"
11480 "* return ix86_output_call_insn (insn, operands[1]);"
11481 [(set_attr "type" "callv")])
11483 (define_insn_and_split "*call_value_rex64_ms_sysv_vzeroupper"
11484 [(set (match_operand 0 "" "")
11485 (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rzw"))
11486 (match_operand 2 "" "")))
11487 (unspec [(const_int 0)] UNSPEC_MS_TO_SYSV_CALL)
11488 (clobber (reg:TI XMM6_REG))
11489 (clobber (reg:TI XMM7_REG))
11490 (clobber (reg:TI XMM8_REG))
11491 (clobber (reg:TI XMM9_REG))
11492 (clobber (reg:TI XMM10_REG))
11493 (clobber (reg:TI XMM11_REG))
11494 (clobber (reg:TI XMM12_REG))
11495 (clobber (reg:TI XMM13_REG))
11496 (clobber (reg:TI XMM14_REG))
11497 (clobber (reg:TI XMM15_REG))
11498 (clobber (reg:DI SI_REG))
11499 (clobber (reg:DI DI_REG))
11500 (unspec [(match_operand 3 "const_int_operand" "")]
11501 UNSPEC_CALL_NEEDS_VZEROUPPER)]
11502 "TARGET_VZEROUPPER && TARGET_64BIT && !SIBLING_CALL_P (insn)"
11504 "&& reload_completed"
11506 "ix86_split_call_vzeroupper (curr_insn, operands[3]); DONE;"
11507 [(set_attr "type" "callv")])
11509 (define_insn "*call_value_rex64_ms_sysv"
11510 [(set (match_operand 0 "" "")
11511 (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rzw"))
11512 (match_operand 2 "" "")))
11513 (unspec [(const_int 0)] UNSPEC_MS_TO_SYSV_CALL)
11514 (clobber (reg:TI XMM6_REG))
11515 (clobber (reg:TI XMM7_REG))
11516 (clobber (reg:TI XMM8_REG))
11517 (clobber (reg:TI XMM9_REG))
11518 (clobber (reg:TI XMM10_REG))
11519 (clobber (reg:TI XMM11_REG))
11520 (clobber (reg:TI XMM12_REG))
11521 (clobber (reg:TI XMM13_REG))
11522 (clobber (reg:TI XMM14_REG))
11523 (clobber (reg:TI XMM15_REG))
11524 (clobber (reg:DI SI_REG))
11525 (clobber (reg:DI DI_REG))]
11526 "TARGET_64BIT && !SIBLING_CALL_P (insn)"
11527 "* return ix86_output_call_insn (insn, operands[1]);"
11528 [(set_attr "type" "callv")])
11530 (define_expand "call_value_pop"
11531 [(parallel [(set (match_operand 0 "" "")
11532 (call (match_operand:QI 1 "" "")
11533 (match_operand:SI 2 "" "")))
11534 (set (reg:SI SP_REG)
11535 (plus:SI (reg:SI SP_REG)
11536 (match_operand:SI 4 "" "")))])]
11539 ix86_expand_call (operands[0], operands[1], operands[2],
11540 operands[3], operands[4], false);
11544 (define_insn_and_split "*call_value_pop_vzeroupper"
11545 [(set (match_operand 0 "" "")
11546 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "lzm"))
11547 (match_operand 2 "" "")))
11548 (set (reg:SI SP_REG)
11549 (plus:SI (reg:SI SP_REG)
11550 (match_operand:SI 3 "immediate_operand" "i")))
11551 (unspec [(match_operand 4 "const_int_operand" "")]
11552 UNSPEC_CALL_NEEDS_VZEROUPPER)]
11553 "TARGET_VZEROUPPER && !TARGET_64BIT && !SIBLING_CALL_P (insn)"
11555 "&& reload_completed"
11557 "ix86_split_call_vzeroupper (curr_insn, operands[4]); DONE;"
11558 [(set_attr "type" "callv")])
11560 (define_insn "*call_value_pop"
11561 [(set (match_operand 0 "" "")
11562 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "lzm"))
11563 (match_operand 2 "" "")))
11564 (set (reg:SI SP_REG)
11565 (plus:SI (reg:SI SP_REG)
11566 (match_operand:SI 3 "immediate_operand" "i")))]
11567 "!TARGET_64BIT && !SIBLING_CALL_P (insn)"
11568 "* return ix86_output_call_insn (insn, operands[1]);"
11569 [(set_attr "type" "callv")])
11571 (define_insn_and_split "*sibcall_value_pop_vzeroupper"
11572 [(set (match_operand 0 "" "")
11573 (call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "Uz"))
11574 (match_operand 2 "" "")))
11575 (set (reg:SI SP_REG)
11576 (plus:SI (reg:SI SP_REG)
11577 (match_operand:SI 3 "immediate_operand" "i")))
11578 (unspec [(match_operand 4 "const_int_operand" "")]
11579 UNSPEC_CALL_NEEDS_VZEROUPPER)]
11580 "TARGET_VZEROUPPER && !TARGET_64BIT && SIBLING_CALL_P (insn)"
11582 "&& reload_completed"
11584 "ix86_split_call_vzeroupper (curr_insn, operands[4]); DONE;"
11585 [(set_attr "type" "callv")])
11587 (define_insn "*sibcall_value_pop"
11588 [(set (match_operand 0 "" "")
11589 (call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "Uz"))
11590 (match_operand 2 "" "")))
11591 (set (reg:SI SP_REG)
11592 (plus:SI (reg:SI SP_REG)
11593 (match_operand:SI 3 "immediate_operand" "i")))]
11594 "!TARGET_64BIT && SIBLING_CALL_P (insn)"
11595 "* return ix86_output_call_insn (insn, operands[1]);"
11596 [(set_attr "type" "callv")])
11598 ;; Call subroutine returning any type.
11600 (define_expand "untyped_call"
11601 [(parallel [(call (match_operand 0 "" "")
11603 (match_operand 1 "" "")
11604 (match_operand 2 "" "")])]
11609 /* In order to give reg-stack an easier job in validating two
11610 coprocessor registers as containing a possible return value,
11611 simply pretend the untyped call returns a complex long double
11614 We can't use SSE_REGPARM_MAX here since callee is unprototyped
11615 and should have the default ABI. */
11617 ix86_expand_call ((TARGET_FLOAT_RETURNS_IN_80387
11618 ? gen_rtx_REG (XCmode, FIRST_FLOAT_REG) : NULL),
11619 operands[0], const0_rtx,
11620 GEN_INT ((TARGET_64BIT
11621 ? (ix86_abi == SYSV_ABI
11622 ? X86_64_SSE_REGPARM_MAX
11623 : X86_64_MS_SSE_REGPARM_MAX)
11624 : X86_32_SSE_REGPARM_MAX)
11628 for (i = 0; i < XVECLEN (operands[2], 0); i++)
11630 rtx set = XVECEXP (operands[2], 0, i);
11631 emit_move_insn (SET_DEST (set), SET_SRC (set));
11634 /* The optimizer does not know that the call sets the function value
11635 registers we stored in the result block. We avoid problems by
11636 claiming that all hard registers are used and clobbered at this
11638 emit_insn (gen_blockage ());
11643 ;; Prologue and epilogue instructions
11645 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
11646 ;; all of memory. This blocks insns from being moved across this point.
11648 (define_insn "blockage"
11649 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
11652 [(set_attr "length" "0")])
11654 ;; Do not schedule instructions accessing memory across this point.
11656 (define_expand "memory_blockage"
11657 [(set (match_dup 0)
11658 (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BLOCKAGE))]
11661 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
11662 MEM_VOLATILE_P (operands[0]) = 1;
11665 (define_insn "*memory_blockage"
11666 [(set (match_operand:BLK 0 "" "")
11667 (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BLOCKAGE))]
11670 [(set_attr "length" "0")])
11672 ;; As USE insns aren't meaningful after reload, this is used instead
11673 ;; to prevent deleting instructions setting registers for PIC code
11674 (define_insn "prologue_use"
11675 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_PROLOGUE_USE)]
11678 [(set_attr "length" "0")])
11680 ;; Insn emitted into the body of a function to return from a function.
11681 ;; This is only done if the function's epilogue is known to be simple.
11682 ;; See comments for ix86_can_use_return_insn_p in i386.c.
11684 (define_expand "return"
11686 "ix86_can_use_return_insn_p ()"
11688 ix86_maybe_emit_epilogue_vzeroupper ();
11689 if (crtl->args.pops_args)
11691 rtx popc = GEN_INT (crtl->args.pops_args);
11692 emit_jump_insn (gen_simple_return_pop_internal (popc));
11697 ;; We need to disable this for TARGET_SEH, as otherwise
11698 ;; shrink-wrapped prologue gets enabled too. This might exceed
11699 ;; the maximum size of prologue in unwind information.
11701 (define_expand "simple_return"
11705 ix86_maybe_emit_epilogue_vzeroupper ();
11706 if (crtl->args.pops_args)
11708 rtx popc = GEN_INT (crtl->args.pops_args);
11709 emit_jump_insn (gen_simple_return_pop_internal (popc));
11714 (define_insn "simple_return_internal"
11718 [(set_attr "length" "1")
11719 (set_attr "atom_unit" "jeu")
11720 (set_attr "length_immediate" "0")
11721 (set_attr "modrm" "0")])
11723 ;; Used by x86_machine_dependent_reorg to avoid penalty on single byte RET
11724 ;; instruction Athlon and K8 have.
11726 (define_insn "simple_return_internal_long"
11728 (unspec [(const_int 0)] UNSPEC_REP)]
11731 [(set_attr "length" "2")
11732 (set_attr "atom_unit" "jeu")
11733 (set_attr "length_immediate" "0")
11734 (set_attr "prefix_rep" "1")
11735 (set_attr "modrm" "0")])
11737 (define_insn "simple_return_pop_internal"
11739 (use (match_operand:SI 0 "const_int_operand" ""))]
11742 [(set_attr "length" "3")
11743 (set_attr "atom_unit" "jeu")
11744 (set_attr "length_immediate" "2")
11745 (set_attr "modrm" "0")])
11747 (define_insn "simple_return_indirect_internal"
11749 (use (match_operand:SI 0 "register_operand" "r"))]
11752 [(set_attr "type" "ibr")
11753 (set_attr "length_immediate" "0")])
11759 [(set_attr "length" "1")
11760 (set_attr "length_immediate" "0")
11761 (set_attr "modrm" "0")])
11763 ;; Generate nops. Operand 0 is the number of nops, up to 8.
11764 (define_insn "nops"
11765 [(unspec_volatile [(match_operand 0 "const_int_operand" "")]
11769 int num = INTVAL (operands[0]);
11771 gcc_assert (num >= 1 && num <= 8);
11774 fputs ("\tnop\n", asm_out_file);
11778 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))
11779 (set_attr "length_immediate" "0")
11780 (set_attr "modrm" "0")])
11782 ;; Pad to 16-byte boundary, max skip in op0. Used to avoid
11783 ;; branch prediction penalty for the third jump in a 16-byte
11787 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_ALIGN)]
11790 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
11791 ASM_OUTPUT_MAX_SKIP_PAD (asm_out_file, 4, (int)INTVAL (operands[0]));
11793 /* It is tempting to use ASM_OUTPUT_ALIGN here, but we don't want to do that.
11794 The align insn is used to avoid 3 jump instructions in the row to improve
11795 branch prediction and the benefits hardly outweigh the cost of extra 8
11796 nops on the average inserted by full alignment pseudo operation. */
11800 [(set_attr "length" "16")])
11802 (define_expand "prologue"
11805 "ix86_expand_prologue (); DONE;")
11807 (define_insn "set_got"
11808 [(set (match_operand:SI 0 "register_operand" "=r")
11809 (unspec:SI [(const_int 0)] UNSPEC_SET_GOT))
11810 (clobber (reg:CC FLAGS_REG))]
11812 "* return output_set_got (operands[0], NULL_RTX);"
11813 [(set_attr "type" "multi")
11814 (set_attr "length" "12")])
11816 (define_insn "set_got_labelled"
11817 [(set (match_operand:SI 0 "register_operand" "=r")
11818 (unspec:SI [(label_ref (match_operand 1 "" ""))]
11820 (clobber (reg:CC FLAGS_REG))]
11822 "* return output_set_got (operands[0], operands[1]);"
11823 [(set_attr "type" "multi")
11824 (set_attr "length" "12")])
11826 (define_insn "set_got_rex64"
11827 [(set (match_operand:DI 0 "register_operand" "=r")
11828 (unspec:DI [(const_int 0)] UNSPEC_SET_GOT))]
11830 "lea{q}\t{_GLOBAL_OFFSET_TABLE_(%%rip), %0|%0, _GLOBAL_OFFSET_TABLE_[rip]}"
11831 [(set_attr "type" "lea")
11832 (set_attr "length_address" "4")
11833 (set_attr "mode" "DI")])
11835 (define_insn "set_rip_rex64"
11836 [(set (match_operand:DI 0 "register_operand" "=r")
11837 (unspec:DI [(label_ref (match_operand 1 "" ""))] UNSPEC_SET_RIP))]
11839 "lea{q}\t{%l1(%%rip), %0|%0, %l1[rip]}"
11840 [(set_attr "type" "lea")
11841 (set_attr "length_address" "4")
11842 (set_attr "mode" "DI")])
11844 (define_insn "set_got_offset_rex64"
11845 [(set (match_operand:DI 0 "register_operand" "=r")
11847 [(label_ref (match_operand 1 "" ""))]
11848 UNSPEC_SET_GOT_OFFSET))]
11850 "movabs{q}\t{$_GLOBAL_OFFSET_TABLE_-%l1, %0|%0, OFFSET FLAT:_GLOBAL_OFFSET_TABLE_-%l1}"
11851 [(set_attr "type" "imov")
11852 (set_attr "length_immediate" "0")
11853 (set_attr "length_address" "8")
11854 (set_attr "mode" "DI")])
11856 (define_expand "epilogue"
11859 "ix86_expand_epilogue (1); DONE;")
11861 (define_expand "sibcall_epilogue"
11864 "ix86_expand_epilogue (0); DONE;")
11866 (define_expand "eh_return"
11867 [(use (match_operand 0 "register_operand" ""))]
11870 rtx tmp, sa = EH_RETURN_STACKADJ_RTX, ra = operands[0];
11872 /* Tricky bit: we write the address of the handler to which we will
11873 be returning into someone else's stack frame, one word below the
11874 stack address we wish to restore. */
11875 tmp = gen_rtx_PLUS (Pmode, arg_pointer_rtx, sa);
11876 tmp = plus_constant (tmp, -UNITS_PER_WORD);
11877 tmp = gen_rtx_MEM (Pmode, tmp);
11878 emit_move_insn (tmp, ra);
11880 emit_jump_insn (gen_eh_return_internal ());
11885 (define_insn_and_split "eh_return_internal"
11889 "epilogue_completed"
11891 "ix86_expand_epilogue (2); DONE;")
11893 (define_insn "leave"
11894 [(set (reg:SI SP_REG) (plus:SI (reg:SI BP_REG) (const_int 4)))
11895 (set (reg:SI BP_REG) (mem:SI (reg:SI BP_REG)))
11896 (clobber (mem:BLK (scratch)))]
11899 [(set_attr "type" "leave")])
11901 (define_insn "leave_rex64"
11902 [(set (reg:DI SP_REG) (plus:DI (reg:DI BP_REG) (const_int 8)))
11903 (set (reg:DI BP_REG) (mem:DI (reg:DI BP_REG)))
11904 (clobber (mem:BLK (scratch)))]
11907 [(set_attr "type" "leave")])
11909 ;; Handle -fsplit-stack.
11911 (define_expand "split_stack_prologue"
11915 ix86_expand_split_stack_prologue ();
11919 ;; In order to support the call/return predictor, we use a return
11920 ;; instruction which the middle-end doesn't see.
11921 (define_insn "split_stack_return"
11922 [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "")]
11923 UNSPECV_SPLIT_STACK_RETURN)]
11926 if (operands[0] == const0_rtx)
11931 [(set_attr "atom_unit" "jeu")
11932 (set_attr "modrm" "0")
11933 (set (attr "length")
11934 (if_then_else (match_operand:SI 0 "const0_operand" "")
11937 (set (attr "length_immediate")
11938 (if_then_else (match_operand:SI 0 "const0_operand" "")
11942 ;; If there are operand 0 bytes available on the stack, jump to
11945 (define_expand "split_stack_space_check"
11946 [(set (pc) (if_then_else
11947 (ltu (minus (reg SP_REG)
11948 (match_operand 0 "register_operand" ""))
11949 (unspec [(const_int 0)] UNSPEC_STACK_CHECK))
11950 (label_ref (match_operand 1 "" ""))
11954 rtx reg, size, limit;
11956 reg = gen_reg_rtx (Pmode);
11957 size = force_reg (Pmode, operands[0]);
11958 emit_insn (gen_sub3_insn (reg, stack_pointer_rtx, size));
11959 limit = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
11960 UNSPEC_STACK_CHECK);
11961 limit = gen_rtx_MEM (Pmode, gen_rtx_CONST (Pmode, limit));
11962 ix86_expand_branch (GEU, reg, limit, operands[1]);
11967 ;; Bit manipulation instructions.
11969 (define_expand "ffs<mode>2"
11970 [(set (match_dup 2) (const_int -1))
11971 (parallel [(set (reg:CCZ FLAGS_REG)
11973 (match_operand:SWI48 1 "nonimmediate_operand" "")
11975 (set (match_operand:SWI48 0 "register_operand" "")
11976 (ctz:SWI48 (match_dup 1)))])
11977 (set (match_dup 0) (if_then_else:SWI48
11978 (eq (reg:CCZ FLAGS_REG) (const_int 0))
11981 (parallel [(set (match_dup 0) (plus:SWI48 (match_dup 0) (const_int 1)))
11982 (clobber (reg:CC FLAGS_REG))])]
11985 if (<MODE>mode == SImode && !TARGET_CMOVE)
11987 emit_insn (gen_ffssi2_no_cmove (operands[0], operands [1]));
11990 operands[2] = gen_reg_rtx (<MODE>mode);
11993 (define_insn_and_split "ffssi2_no_cmove"
11994 [(set (match_operand:SI 0 "register_operand" "=r")
11995 (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
11996 (clobber (match_scratch:SI 2 "=&q"))
11997 (clobber (reg:CC FLAGS_REG))]
12000 "&& reload_completed"
12001 [(parallel [(set (reg:CCZ FLAGS_REG)
12002 (compare:CCZ (match_dup 1) (const_int 0)))
12003 (set (match_dup 0) (ctz:SI (match_dup 1)))])
12004 (set (strict_low_part (match_dup 3))
12005 (eq:QI (reg:CCZ FLAGS_REG) (const_int 0)))
12006 (parallel [(set (match_dup 2) (neg:SI (match_dup 2)))
12007 (clobber (reg:CC FLAGS_REG))])
12008 (parallel [(set (match_dup 0) (ior:SI (match_dup 0) (match_dup 2)))
12009 (clobber (reg:CC FLAGS_REG))])
12010 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
12011 (clobber (reg:CC FLAGS_REG))])]
12013 operands[3] = gen_lowpart (QImode, operands[2]);
12014 ix86_expand_clear (operands[2]);
12017 (define_insn "*ffs<mode>_1"
12018 [(set (reg:CCZ FLAGS_REG)
12019 (compare:CCZ (match_operand:SWI48 1 "nonimmediate_operand" "rm")
12021 (set (match_operand:SWI48 0 "register_operand" "=r")
12022 (ctz:SWI48 (match_dup 1)))]
12024 "bsf{<imodesuffix>}\t{%1, %0|%0, %1}"
12025 [(set_attr "type" "alu1")
12026 (set_attr "prefix_0f" "1")
12027 (set_attr "mode" "<MODE>")])
12029 (define_insn "ctz<mode>2"
12030 [(set (match_operand:SWI248 0 "register_operand" "=r")
12031 (ctz:SWI248 (match_operand:SWI248 1 "nonimmediate_operand" "rm")))
12032 (clobber (reg:CC FLAGS_REG))]
12036 return "tzcnt{<imodesuffix>}\t{%1, %0|%0, %1}";
12038 return "bsf{<imodesuffix>}\t{%1, %0|%0, %1}";
12040 [(set_attr "type" "alu1")
12041 (set_attr "prefix_0f" "1")
12042 (set (attr "prefix_rep") (symbol_ref "TARGET_BMI"))
12043 (set_attr "mode" "<MODE>")])
12045 (define_expand "clz<mode>2"
12047 [(set (match_operand:SWI248 0 "register_operand" "")
12050 (clz:SWI248 (match_operand:SWI248 1 "nonimmediate_operand" ""))))
12051 (clobber (reg:CC FLAGS_REG))])
12053 [(set (match_dup 0) (xor:SWI248 (match_dup 0) (match_dup 2)))
12054 (clobber (reg:CC FLAGS_REG))])]
12059 emit_insn (gen_clz<mode>2_lzcnt (operands[0], operands[1]));
12062 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode)-1);
12065 (define_insn "clz<mode>2_lzcnt"
12066 [(set (match_operand:SWI248 0 "register_operand" "=r")
12067 (clz:SWI248 (match_operand:SWI248 1 "nonimmediate_operand" "rm")))
12068 (clobber (reg:CC FLAGS_REG))]
12070 "lzcnt{<imodesuffix>}\t{%1, %0|%0, %1}"
12071 [(set_attr "prefix_rep" "1")
12072 (set_attr "type" "bitmanip")
12073 (set_attr "mode" "<MODE>")])
12075 ;; BMI instructions.
12076 (define_insn "*bmi_andn_<mode>"
12077 [(set (match_operand:SWI48 0 "register_operand" "=r")
12080 (match_operand:SWI48 1 "register_operand" "r"))
12081 (match_operand:SWI48 2 "nonimmediate_operand" "rm")))
12082 (clobber (reg:CC FLAGS_REG))]
12084 "andn\t{%2, %1, %0|%0, %1, %2}"
12085 [(set_attr "type" "bitmanip")
12086 (set_attr "mode" "<MODE>")])
12088 (define_insn "bmi_bextr_<mode>"
12089 [(set (match_operand:SWI48 0 "register_operand" "=r")
12090 (unspec:SWI48 [(match_operand:SWI48 1 "register_operand" "r")
12091 (match_operand:SWI48 2 "nonimmediate_operand" "rm")]
12093 (clobber (reg:CC FLAGS_REG))]
12095 "bextr\t{%2, %1, %0|%0, %1, %2}"
12096 [(set_attr "type" "bitmanip")
12097 (set_attr "mode" "<MODE>")])
12099 (define_insn "*bmi_blsi_<mode>"
12100 [(set (match_operand:SWI48 0 "register_operand" "=r")
12103 (match_operand:SWI48 1 "nonimmediate_operand" "rm"))
12105 (clobber (reg:CC FLAGS_REG))]
12107 "blsi\t{%1, %0|%0, %1}"
12108 [(set_attr "type" "bitmanip")
12109 (set_attr "mode" "<MODE>")])
12111 (define_insn "*bmi_blsmsk_<mode>"
12112 [(set (match_operand:SWI48 0 "register_operand" "=r")
12115 (match_operand:SWI48 1 "nonimmediate_operand" "rm")
12118 (clobber (reg:CC FLAGS_REG))]
12120 "blsmsk\t{%1, %0|%0, %1}"
12121 [(set_attr "type" "bitmanip")
12122 (set_attr "mode" "<MODE>")])
12124 (define_insn "*bmi_blsr_<mode>"
12125 [(set (match_operand:SWI48 0 "register_operand" "=r")
12128 (match_operand:SWI48 1 "nonimmediate_operand" "rm")
12131 (clobber (reg:CC FLAGS_REG))]
12133 "blsr\t{%1, %0|%0, %1}"
12134 [(set_attr "type" "bitmanip")
12135 (set_attr "mode" "<MODE>")])
12137 ;; BMI2 instructions.
12138 (define_insn "bmi2_bzhi_<mode>3"
12139 [(set (match_operand:SWI48 0 "register_operand" "=r")
12140 (and:SWI48 (match_operand:SWI48 1 "register_operand" "r")
12141 (lshiftrt:SWI48 (const_int -1)
12142 (match_operand:SWI48 2 "nonimmediate_operand" "rm"))))
12143 (clobber (reg:CC FLAGS_REG))]
12145 "bzhi\t{%2, %1, %0|%0, %1, %2}"
12146 [(set_attr "type" "bitmanip")
12147 (set_attr "prefix" "vex")
12148 (set_attr "mode" "<MODE>")])
12150 (define_insn "bmi2_pdep_<mode>3"
12151 [(set (match_operand:SWI48 0 "register_operand" "=r")
12152 (unspec:SWI48 [(match_operand:SWI48 1 "register_operand" "r")
12153 (match_operand:SWI48 2 "nonimmediate_operand" "rm")]
12156 "pdep\t{%2, %1, %0|%0, %1, %2}"
12157 [(set_attr "type" "bitmanip")
12158 (set_attr "prefix" "vex")
12159 (set_attr "mode" "<MODE>")])
12161 (define_insn "bmi2_pext_<mode>3"
12162 [(set (match_operand:SWI48 0 "register_operand" "=r")
12163 (unspec:SWI48 [(match_operand:SWI48 1 "register_operand" "r")
12164 (match_operand:SWI48 2 "nonimmediate_operand" "rm")]
12167 "pext\t{%2, %1, %0|%0, %1, %2}"
12168 [(set_attr "type" "bitmanip")
12169 (set_attr "prefix" "vex")
12170 (set_attr "mode" "<MODE>")])
12172 ;; TBM instructions.
12173 (define_insn "tbm_bextri_<mode>"
12174 [(set (match_operand:SWI48 0 "register_operand" "=r")
12175 (zero_extract:SWI48
12176 (match_operand:SWI48 1 "nonimmediate_operand" "rm")
12177 (match_operand:SWI48 2 "const_0_to_255_operand" "n")
12178 (match_operand:SWI48 3 "const_0_to_255_operand" "n")))
12179 (clobber (reg:CC FLAGS_REG))]
12182 operands[2] = GEN_INT (INTVAL (operands[2]) << 8 | INTVAL (operands[3]));
12183 return "bextr\t{%2, %1, %0|%0, %1, %2}";
12185 [(set_attr "type" "bitmanip")
12186 (set_attr "mode" "<MODE>")])
12188 (define_insn "*tbm_blcfill_<mode>"
12189 [(set (match_operand:SWI48 0 "register_operand" "=r")
12192 (match_operand:SWI48 1 "nonimmediate_operand" "rm")
12195 (clobber (reg:CC FLAGS_REG))]
12197 "blcfill\t{%1, %0|%0, %1}"
12198 [(set_attr "type" "bitmanip")
12199 (set_attr "mode" "<MODE>")])
12201 (define_insn "*tbm_blci_<mode>"
12202 [(set (match_operand:SWI48 0 "register_operand" "=r")
12206 (match_operand:SWI48 1 "nonimmediate_operand" "rm")
12209 (clobber (reg:CC FLAGS_REG))]
12211 "blci\t{%1, %0|%0, %1}"
12212 [(set_attr "type" "bitmanip")
12213 (set_attr "mode" "<MODE>")])
12215 (define_insn "*tbm_blcic_<mode>"
12216 [(set (match_operand:SWI48 0 "register_operand" "=r")
12219 (match_operand:SWI48 1 "nonimmediate_operand" "rm")
12223 (clobber (reg:CC FLAGS_REG))]
12225 "blcic\t{%1, %0|%0, %1}"
12226 [(set_attr "type" "bitmanip")
12227 (set_attr "mode" "<MODE>")])
12229 (define_insn "*tbm_blcmsk_<mode>"
12230 [(set (match_operand:SWI48 0 "register_operand" "=r")
12233 (match_operand:SWI48 1 "nonimmediate_operand" "rm")
12236 (clobber (reg:CC FLAGS_REG))]
12238 "blcmsk\t{%1, %0|%0, %1}"
12239 [(set_attr "type" "bitmanip")
12240 (set_attr "mode" "<MODE>")])
12242 (define_insn "*tbm_blcs_<mode>"
12243 [(set (match_operand:SWI48 0 "register_operand" "=r")
12246 (match_operand:SWI48 1 "nonimmediate_operand" "rm")
12249 (clobber (reg:CC FLAGS_REG))]
12251 "blcs\t{%1, %0|%0, %1}"
12252 [(set_attr "type" "bitmanip")
12253 (set_attr "mode" "<MODE>")])
12255 (define_insn "*tbm_blsfill_<mode>"
12256 [(set (match_operand:SWI48 0 "register_operand" "=r")
12259 (match_operand:SWI48 1 "nonimmediate_operand" "rm")
12262 (clobber (reg:CC FLAGS_REG))]
12264 "blsfill\t{%1, %0|%0, %1}"
12265 [(set_attr "type" "bitmanip")
12266 (set_attr "mode" "<MODE>")])
12268 (define_insn "*tbm_blsic_<mode>"
12269 [(set (match_operand:SWI48 0 "register_operand" "=r")
12272 (match_operand:SWI48 1 "nonimmediate_operand" "rm")
12276 (clobber (reg:CC FLAGS_REG))]
12278 "blsic\t{%1, %0|%0, %1}"
12279 [(set_attr "type" "bitmanip")
12280 (set_attr "mode" "<MODE>")])
12282 (define_insn "*tbm_t1mskc_<mode>"
12283 [(set (match_operand:SWI48 0 "register_operand" "=r")
12286 (match_operand:SWI48 1 "nonimmediate_operand" "rm")
12290 (clobber (reg:CC FLAGS_REG))]
12292 "t1mskc\t{%1, %0|%0, %1}"
12293 [(set_attr "type" "bitmanip")
12294 (set_attr "mode" "<MODE>")])
12296 (define_insn "*tbm_tzmsk_<mode>"
12297 [(set (match_operand:SWI48 0 "register_operand" "=r")
12300 (match_operand:SWI48 1 "nonimmediate_operand" "rm")
12304 (clobber (reg:CC FLAGS_REG))]
12306 "tzmsk\t{%1, %0|%0, %1}"
12307 [(set_attr "type" "bitmanip")
12308 (set_attr "mode" "<MODE>")])
12310 (define_insn "bsr_rex64"
12311 [(set (match_operand:DI 0 "register_operand" "=r")
12312 (minus:DI (const_int 63)
12313 (clz:DI (match_operand:DI 1 "nonimmediate_operand" "rm"))))
12314 (clobber (reg:CC FLAGS_REG))]
12316 "bsr{q}\t{%1, %0|%0, %1}"
12317 [(set_attr "type" "alu1")
12318 (set_attr "prefix_0f" "1")
12319 (set_attr "mode" "DI")])
12322 [(set (match_operand:SI 0 "register_operand" "=r")
12323 (minus:SI (const_int 31)
12324 (clz:SI (match_operand:SI 1 "nonimmediate_operand" "rm"))))
12325 (clobber (reg:CC FLAGS_REG))]
12327 "bsr{l}\t{%1, %0|%0, %1}"
12328 [(set_attr "type" "alu1")
12329 (set_attr "prefix_0f" "1")
12330 (set_attr "mode" "SI")])
12332 (define_insn "*bsrhi"
12333 [(set (match_operand:HI 0 "register_operand" "=r")
12334 (minus:HI (const_int 15)
12335 (clz:HI (match_operand:HI 1 "nonimmediate_operand" "rm"))))
12336 (clobber (reg:CC FLAGS_REG))]
12338 "bsr{w}\t{%1, %0|%0, %1}"
12339 [(set_attr "type" "alu1")
12340 (set_attr "prefix_0f" "1")
12341 (set_attr "mode" "HI")])
12343 (define_insn "popcount<mode>2"
12344 [(set (match_operand:SWI248 0 "register_operand" "=r")
12346 (match_operand:SWI248 1 "nonimmediate_operand" "rm")))
12347 (clobber (reg:CC FLAGS_REG))]
12351 return "popcnt\t{%1, %0|%0, %1}";
12353 return "popcnt{<imodesuffix>}\t{%1, %0|%0, %1}";
12356 [(set_attr "prefix_rep" "1")
12357 (set_attr "type" "bitmanip")
12358 (set_attr "mode" "<MODE>")])
12360 (define_insn "*popcount<mode>2_cmp"
12361 [(set (reg FLAGS_REG)
12364 (match_operand:SWI248 1 "nonimmediate_operand" "rm"))
12366 (set (match_operand:SWI248 0 "register_operand" "=r")
12367 (popcount:SWI248 (match_dup 1)))]
12368 "TARGET_POPCNT && ix86_match_ccmode (insn, CCZmode)"
12371 return "popcnt\t{%1, %0|%0, %1}";
12373 return "popcnt{<imodesuffix>}\t{%1, %0|%0, %1}";
12376 [(set_attr "prefix_rep" "1")
12377 (set_attr "type" "bitmanip")
12378 (set_attr "mode" "<MODE>")])
12380 (define_insn "*popcountsi2_cmp_zext"
12381 [(set (reg FLAGS_REG)
12383 (popcount:SI (match_operand:SI 1 "nonimmediate_operand" "rm"))
12385 (set (match_operand:DI 0 "register_operand" "=r")
12386 (zero_extend:DI(popcount:SI (match_dup 1))))]
12387 "TARGET_64BIT && TARGET_POPCNT && ix86_match_ccmode (insn, CCZmode)"
12390 return "popcnt\t{%1, %0|%0, %1}";
12392 return "popcnt{l}\t{%1, %0|%0, %1}";
12395 [(set_attr "prefix_rep" "1")
12396 (set_attr "type" "bitmanip")
12397 (set_attr "mode" "SI")])
12399 (define_expand "bswap<mode>2"
12400 [(set (match_operand:SWI48 0 "register_operand" "")
12401 (bswap:SWI48 (match_operand:SWI48 1 "register_operand" "")))]
12404 if (<MODE>mode == SImode && !(TARGET_BSWAP || TARGET_MOVBE))
12406 rtx x = operands[0];
12408 emit_move_insn (x, operands[1]);
12409 emit_insn (gen_bswaphi_lowpart (gen_lowpart (HImode, x)));
12410 emit_insn (gen_rotlsi3 (x, x, GEN_INT (16)));
12411 emit_insn (gen_bswaphi_lowpart (gen_lowpart (HImode, x)));
12416 (define_insn "*bswap<mode>2_movbe"
12417 [(set (match_operand:SWI48 0 "nonimmediate_operand" "=r,r,m")
12418 (bswap:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "0,m,r")))]
12420 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
12423 movbe\t{%1, %0|%0, %1}
12424 movbe\t{%1, %0|%0, %1}"
12425 [(set_attr "type" "bitmanip,imov,imov")
12426 (set_attr "modrm" "0,1,1")
12427 (set_attr "prefix_0f" "*,1,1")
12428 (set_attr "prefix_extra" "*,1,1")
12429 (set_attr "mode" "<MODE>")])
12431 (define_insn "*bswap<mode>2_1"
12432 [(set (match_operand:SWI48 0 "register_operand" "=r")
12433 (bswap:SWI48 (match_operand:SWI48 1 "register_operand" "0")))]
12436 [(set_attr "type" "bitmanip")
12437 (set_attr "modrm" "0")
12438 (set_attr "mode" "<MODE>")])
12440 (define_insn "*bswaphi_lowpart_1"
12441 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+Q,r"))
12442 (bswap:HI (match_dup 0)))
12443 (clobber (reg:CC FLAGS_REG))]
12444 "TARGET_USE_XCHGB || optimize_function_for_size_p (cfun)"
12446 xchg{b}\t{%h0, %b0|%b0, %h0}
12447 rol{w}\t{$8, %0|%0, 8}"
12448 [(set_attr "length" "2,4")
12449 (set_attr "mode" "QI,HI")])
12451 (define_insn "bswaphi_lowpart"
12452 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
12453 (bswap:HI (match_dup 0)))
12454 (clobber (reg:CC FLAGS_REG))]
12456 "rol{w}\t{$8, %0|%0, 8}"
12457 [(set_attr "length" "4")
12458 (set_attr "mode" "HI")])
12460 (define_expand "paritydi2"
12461 [(set (match_operand:DI 0 "register_operand" "")
12462 (parity:DI (match_operand:DI 1 "register_operand" "")))]
12465 rtx scratch = gen_reg_rtx (QImode);
12468 emit_insn (gen_paritydi2_cmp (NULL_RTX, NULL_RTX,
12469 NULL_RTX, operands[1]));
12471 cond = gen_rtx_fmt_ee (ORDERED, QImode,
12472 gen_rtx_REG (CCmode, FLAGS_REG),
12474 emit_insn (gen_rtx_SET (VOIDmode, scratch, cond));
12477 emit_insn (gen_zero_extendqidi2 (operands[0], scratch));
12480 rtx tmp = gen_reg_rtx (SImode);
12482 emit_insn (gen_zero_extendqisi2 (tmp, scratch));
12483 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
12488 (define_expand "paritysi2"
12489 [(set (match_operand:SI 0 "register_operand" "")
12490 (parity:SI (match_operand:SI 1 "register_operand" "")))]
12493 rtx scratch = gen_reg_rtx (QImode);
12496 emit_insn (gen_paritysi2_cmp (NULL_RTX, NULL_RTX, operands[1]));
12498 cond = gen_rtx_fmt_ee (ORDERED, QImode,
12499 gen_rtx_REG (CCmode, FLAGS_REG),
12501 emit_insn (gen_rtx_SET (VOIDmode, scratch, cond));
12503 emit_insn (gen_zero_extendqisi2 (operands[0], scratch));
12507 (define_insn_and_split "paritydi2_cmp"
12508 [(set (reg:CC FLAGS_REG)
12509 (unspec:CC [(match_operand:DI 3 "register_operand" "0")]
12511 (clobber (match_scratch:DI 0 "=r"))
12512 (clobber (match_scratch:SI 1 "=&r"))
12513 (clobber (match_scratch:HI 2 "=Q"))]
12516 "&& reload_completed"
12518 [(set (match_dup 1)
12519 (xor:SI (match_dup 1) (match_dup 4)))
12520 (clobber (reg:CC FLAGS_REG))])
12522 [(set (reg:CC FLAGS_REG)
12523 (unspec:CC [(match_dup 1)] UNSPEC_PARITY))
12524 (clobber (match_dup 1))
12525 (clobber (match_dup 2))])]
12527 operands[4] = gen_lowpart (SImode, operands[3]);
12531 emit_move_insn (operands[1], gen_lowpart (SImode, operands[3]));
12532 emit_insn (gen_lshrdi3 (operands[3], operands[3], GEN_INT (32)));
12535 operands[1] = gen_highpart (SImode, operands[3]);
12538 (define_insn_and_split "paritysi2_cmp"
12539 [(set (reg:CC FLAGS_REG)
12540 (unspec:CC [(match_operand:SI 2 "register_operand" "0")]
12542 (clobber (match_scratch:SI 0 "=r"))
12543 (clobber (match_scratch:HI 1 "=&Q"))]
12546 "&& reload_completed"
12548 [(set (match_dup 1)
12549 (xor:HI (match_dup 1) (match_dup 3)))
12550 (clobber (reg:CC FLAGS_REG))])
12552 [(set (reg:CC FLAGS_REG)
12553 (unspec:CC [(match_dup 1)] UNSPEC_PARITY))
12554 (clobber (match_dup 1))])]
12556 operands[3] = gen_lowpart (HImode, operands[2]);
12558 emit_move_insn (operands[1], gen_lowpart (HImode, operands[2]));
12559 emit_insn (gen_lshrsi3 (operands[2], operands[2], GEN_INT (16)));
12562 (define_insn "*parityhi2_cmp"
12563 [(set (reg:CC FLAGS_REG)
12564 (unspec:CC [(match_operand:HI 1 "register_operand" "0")]
12566 (clobber (match_scratch:HI 0 "=Q"))]
12568 "xor{b}\t{%h0, %b0|%b0, %h0}"
12569 [(set_attr "length" "2")
12570 (set_attr "mode" "HI")])
12573 ;; Thread-local storage patterns for ELF.
12575 ;; Note that these code sequences must appear exactly as shown
12576 ;; in order to allow linker relaxation.
12578 (define_insn "*tls_global_dynamic_32_gnu"
12579 [(set (match_operand:SI 0 "register_operand" "=a")
12581 [(match_operand:SI 1 "register_operand" "b")
12582 (match_operand:SI 2 "tls_symbolic_operand" "")
12583 (match_operand:SI 3 "constant_call_address_operand" "z")]
12585 (clobber (match_scratch:SI 4 "=d"))
12586 (clobber (match_scratch:SI 5 "=c"))
12587 (clobber (reg:CC FLAGS_REG))]
12588 "!TARGET_64BIT && TARGET_GNU_TLS"
12591 ("lea{l}\t{%E2@tlsgd(,%1,1), %0|%0, %E2@tlsgd[%1*1]}", operands);
12592 if (TARGET_SUN_TLS)
12593 #ifdef HAVE_AS_IX86_TLSGDPLT
12594 return "call\t%a2@tlsgdplt";
12596 return "call\t%p3@plt";
12598 return "call\t%P3";
12600 [(set_attr "type" "multi")
12601 (set_attr "length" "12")])
12603 (define_expand "tls_global_dynamic_32"
12605 [(set (match_operand:SI 0 "register_operand" "")
12606 (unspec:SI [(match_operand:SI 2 "register_operand" "")
12607 (match_operand:SI 1 "tls_symbolic_operand" "")
12608 (match_operand:SI 3 "constant_call_address_operand" "")]
12610 (clobber (match_scratch:SI 4 ""))
12611 (clobber (match_scratch:SI 5 ""))
12612 (clobber (reg:CC FLAGS_REG))])])
12614 (define_insn "*tls_global_dynamic_64"
12615 [(set (match_operand:DI 0 "register_operand" "=a")
12617 (mem:QI (match_operand:DI 2 "constant_call_address_operand" "z"))
12618 (match_operand:DI 3 "" "")))
12619 (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
12624 fputs (ASM_BYTE "0x66\n", asm_out_file);
12626 ("lea{q}\t{%E1@tlsgd(%%rip), %%rdi|rdi, %E1@tlsgd[rip]}", operands);
12627 fputs (ASM_SHORT "0x6666\n", asm_out_file);
12628 fputs ("\trex64\n", asm_out_file);
12629 if (TARGET_SUN_TLS)
12630 return "call\t%p2@plt";
12631 return "call\t%P2";
12633 [(set_attr "type" "multi")
12634 (set (attr "length")
12635 (symbol_ref "TARGET_X32 ? 15 : 16"))])
12637 (define_expand "tls_global_dynamic_64"
12639 [(set (match_operand:DI 0 "register_operand" "")
12641 (mem:QI (match_operand:DI 2 "constant_call_address_operand" ""))
12643 (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
12646 (define_insn "*tls_local_dynamic_base_32_gnu"
12647 [(set (match_operand:SI 0 "register_operand" "=a")
12649 [(match_operand:SI 1 "register_operand" "b")
12650 (match_operand:SI 2 "constant_call_address_operand" "z")]
12651 UNSPEC_TLS_LD_BASE))
12652 (clobber (match_scratch:SI 3 "=d"))
12653 (clobber (match_scratch:SI 4 "=c"))
12654 (clobber (reg:CC FLAGS_REG))]
12655 "!TARGET_64BIT && TARGET_GNU_TLS"
12658 ("lea{l}\t{%&@tlsldm(%1), %0|%0, %&@tlsldm[%1]}", operands);
12659 if (TARGET_SUN_TLS)
12660 #ifdef HAVE_AS_IX86_TLSLDMPLT
12661 return "call\t%&@tlsldmplt";
12663 return "call\t%p2@plt";
12665 return "call\t%P2";
12667 [(set_attr "type" "multi")
12668 (set_attr "length" "11")])
12670 (define_expand "tls_local_dynamic_base_32"
12672 [(set (match_operand:SI 0 "register_operand" "")
12674 [(match_operand:SI 1 "register_operand" "")
12675 (match_operand:SI 2 "constant_call_address_operand" "")]
12676 UNSPEC_TLS_LD_BASE))
12677 (clobber (match_scratch:SI 3 ""))
12678 (clobber (match_scratch:SI 4 ""))
12679 (clobber (reg:CC FLAGS_REG))])])
12681 (define_insn "*tls_local_dynamic_base_64"
12682 [(set (match_operand:DI 0 "register_operand" "=a")
12684 (mem:QI (match_operand:DI 1 "constant_call_address_operand" "z"))
12685 (match_operand:DI 2 "" "")))
12686 (unspec:DI [(const_int 0)] UNSPEC_TLS_LD_BASE)]
12690 ("lea{q}\t{%&@tlsld(%%rip), %%rdi|rdi, %&@tlsld[rip]}", operands);
12691 if (TARGET_SUN_TLS)
12692 return "call\t%p1@plt";
12693 return "call\t%P1";
12695 [(set_attr "type" "multi")
12696 (set_attr "length" "12")])
12698 (define_expand "tls_local_dynamic_base_64"
12700 [(set (match_operand:DI 0 "register_operand" "")
12702 (mem:QI (match_operand:DI 1 "constant_call_address_operand" ""))
12704 (unspec:DI [(const_int 0)] UNSPEC_TLS_LD_BASE)])])
12706 ;; Local dynamic of a single variable is a lose. Show combine how
12707 ;; to convert that back to global dynamic.
12709 (define_insn_and_split "*tls_local_dynamic_32_once"
12710 [(set (match_operand:SI 0 "register_operand" "=a")
12712 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
12713 (match_operand:SI 2 "constant_call_address_operand" "z")]
12714 UNSPEC_TLS_LD_BASE)
12715 (const:SI (unspec:SI
12716 [(match_operand:SI 3 "tls_symbolic_operand" "")]
12718 (clobber (match_scratch:SI 4 "=d"))
12719 (clobber (match_scratch:SI 5 "=c"))
12720 (clobber (reg:CC FLAGS_REG))]
12725 [(set (match_dup 0)
12726 (unspec:SI [(match_dup 1) (match_dup 3) (match_dup 2)]
12728 (clobber (match_dup 4))
12729 (clobber (match_dup 5))
12730 (clobber (reg:CC FLAGS_REG))])])
12732 ;; Segment register for the thread base ptr load
12733 (define_mode_attr tp_seg [(SI "gs") (DI "fs")])
12735 ;; Load and add the thread base pointer from %<tp_seg>:0.
12736 (define_insn "*load_tp_x32"
12737 [(set (match_operand:SI 0 "register_operand" "=r")
12738 (unspec:SI [(const_int 0)] UNSPEC_TP))]
12740 "mov{l}\t{%%fs:0, %0|%0, DWORD PTR fs:0}"
12741 [(set_attr "type" "imov")
12742 (set_attr "modrm" "0")
12743 (set_attr "length" "7")
12744 (set_attr "memory" "load")
12745 (set_attr "imm_disp" "false")])
12747 (define_insn "*load_tp_x32_zext"
12748 [(set (match_operand:DI 0 "register_operand" "=r")
12749 (zero_extend:DI (unspec:SI [(const_int 0)] UNSPEC_TP)))]
12751 "mov{l}\t{%%fs:0, %k0|%k0, DWORD PTR fs:0}"
12752 [(set_attr "type" "imov")
12753 (set_attr "modrm" "0")
12754 (set_attr "length" "7")
12755 (set_attr "memory" "load")
12756 (set_attr "imm_disp" "false")])
12758 (define_insn "*load_tp_<mode>"
12759 [(set (match_operand:P 0 "register_operand" "=r")
12760 (unspec:P [(const_int 0)] UNSPEC_TP))]
12762 "mov{<imodesuffix>}\t{%%<tp_seg>:0, %0|%0, <iptrsize> PTR <tp_seg>:0}"
12763 [(set_attr "type" "imov")
12764 (set_attr "modrm" "0")
12765 (set_attr "length" "7")
12766 (set_attr "memory" "load")
12767 (set_attr "imm_disp" "false")])
12769 (define_insn "*add_tp_x32"
12770 [(set (match_operand:SI 0 "register_operand" "=r")
12771 (plus:SI (unspec:SI [(const_int 0)] UNSPEC_TP)
12772 (match_operand:SI 1 "register_operand" "0")))
12773 (clobber (reg:CC FLAGS_REG))]
12775 "add{l}\t{%%fs:0, %0|%0, DWORD PTR fs:0}"
12776 [(set_attr "type" "alu")
12777 (set_attr "modrm" "0")
12778 (set_attr "length" "7")
12779 (set_attr "memory" "load")
12780 (set_attr "imm_disp" "false")])
12782 (define_insn "*add_tp_x32_zext"
12783 [(set (match_operand:DI 0 "register_operand" "=r")
12785 (plus:SI (unspec:SI [(const_int 0)] UNSPEC_TP)
12786 (match_operand:SI 1 "register_operand" "0"))))
12787 (clobber (reg:CC FLAGS_REG))]
12789 "add{l}\t{%%fs:0, %k0|%k0, DWORD PTR fs:0}"
12790 [(set_attr "type" "alu")
12791 (set_attr "modrm" "0")
12792 (set_attr "length" "7")
12793 (set_attr "memory" "load")
12794 (set_attr "imm_disp" "false")])
12796 (define_insn "*add_tp_<mode>"
12797 [(set (match_operand:P 0 "register_operand" "=r")
12798 (plus:P (unspec:P [(const_int 0)] UNSPEC_TP)
12799 (match_operand:P 1 "register_operand" "0")))
12800 (clobber (reg:CC FLAGS_REG))]
12802 "add{<imodesuffix>}\t{%%<tp_seg>:0, %0|%0, <iptrsize> PTR <tp_seg>:0}"
12803 [(set_attr "type" "alu")
12804 (set_attr "modrm" "0")
12805 (set_attr "length" "7")
12806 (set_attr "memory" "load")
12807 (set_attr "imm_disp" "false")])
12809 ;; The Sun linker took the AMD64 TLS spec literally and can only handle
12810 ;; %rax as destination of the initial executable code sequence.
12811 (define_insn "tls_initial_exec_64_sun"
12812 [(set (match_operand:DI 0 "register_operand" "=a")
12814 [(match_operand:DI 1 "tls_symbolic_operand" "")]
12815 UNSPEC_TLS_IE_SUN))
12816 (clobber (reg:CC FLAGS_REG))]
12817 "TARGET_64BIT && TARGET_SUN_TLS"
12820 ("mov{q}\t{%%fs:0, %0|%0, QWORD PTR fs:0}", operands);
12821 return "add{q}\t{%a1@gottpoff(%%rip), %0|%0, %a1@gottpoff[rip]}";
12823 [(set_attr "type" "multi")])
12825 ;; GNU2 TLS patterns can be split.
12827 (define_expand "tls_dynamic_gnu2_32"
12828 [(set (match_dup 3)
12829 (plus:SI (match_operand:SI 2 "register_operand" "")
12831 (unspec:SI [(match_operand:SI 1 "tls_symbolic_operand" "")]
12834 [(set (match_operand:SI 0 "register_operand" "")
12835 (unspec:SI [(match_dup 1) (match_dup 3)
12836 (match_dup 2) (reg:SI SP_REG)]
12838 (clobber (reg:CC FLAGS_REG))])]
12839 "!TARGET_64BIT && TARGET_GNU2_TLS"
12841 operands[3] = can_create_pseudo_p () ? gen_reg_rtx (Pmode) : operands[0];
12842 ix86_tls_descriptor_calls_expanded_in_cfun = true;
12845 (define_insn "*tls_dynamic_gnu2_lea_32"
12846 [(set (match_operand:SI 0 "register_operand" "=r")
12847 (plus:SI (match_operand:SI 1 "register_operand" "b")
12849 (unspec:SI [(match_operand:SI 2 "tls_symbolic_operand" "")]
12850 UNSPEC_TLSDESC))))]
12851 "!TARGET_64BIT && TARGET_GNU2_TLS"
12852 "lea{l}\t{%E2@TLSDESC(%1), %0|%0, %E2@TLSDESC[%1]}"
12853 [(set_attr "type" "lea")
12854 (set_attr "mode" "SI")
12855 (set_attr "length" "6")
12856 (set_attr "length_address" "4")])
12858 (define_insn "*tls_dynamic_gnu2_call_32"
12859 [(set (match_operand:SI 0 "register_operand" "=a")
12860 (unspec:SI [(match_operand:SI 1 "tls_symbolic_operand" "")
12861 (match_operand:SI 2 "register_operand" "0")
12862 ;; we have to make sure %ebx still points to the GOT
12863 (match_operand:SI 3 "register_operand" "b")
12866 (clobber (reg:CC FLAGS_REG))]
12867 "!TARGET_64BIT && TARGET_GNU2_TLS"
12868 "call\t{*%a1@TLSCALL(%2)|[DWORD PTR [%2+%a1@TLSCALL]]}"
12869 [(set_attr "type" "call")
12870 (set_attr "length" "2")
12871 (set_attr "length_address" "0")])
12873 (define_insn_and_split "*tls_dynamic_gnu2_combine_32"
12874 [(set (match_operand:SI 0 "register_operand" "=&a")
12876 (unspec:SI [(match_operand:SI 3 "tls_modbase_operand" "")
12877 (match_operand:SI 4 "" "")
12878 (match_operand:SI 2 "register_operand" "b")
12881 (const:SI (unspec:SI
12882 [(match_operand:SI 1 "tls_symbolic_operand" "")]
12884 (clobber (reg:CC FLAGS_REG))]
12885 "!TARGET_64BIT && TARGET_GNU2_TLS"
12888 [(set (match_dup 0) (match_dup 5))]
12890 operands[5] = can_create_pseudo_p () ? gen_reg_rtx (Pmode) : operands[0];
12891 emit_insn (gen_tls_dynamic_gnu2_32 (operands[5], operands[1], operands[2]));
12894 (define_expand "tls_dynamic_gnu2_64"
12895 [(set (match_dup 2)
12896 (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
12899 [(set (match_operand:DI 0 "register_operand" "")
12900 (unspec:DI [(match_dup 1) (match_dup 2) (reg:DI SP_REG)]
12902 (clobber (reg:CC FLAGS_REG))])]
12903 "TARGET_64BIT && TARGET_GNU2_TLS"
12905 operands[2] = can_create_pseudo_p () ? gen_reg_rtx (Pmode) : operands[0];
12906 ix86_tls_descriptor_calls_expanded_in_cfun = true;
12909 (define_insn "*tls_dynamic_gnu2_lea_64"
12910 [(set (match_operand:DI 0 "register_operand" "=r")
12911 (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
12913 "TARGET_64BIT && TARGET_GNU2_TLS"
12914 "lea{q}\t{%E1@TLSDESC(%%rip), %0|%0, %E1@TLSDESC[rip]}"
12915 [(set_attr "type" "lea")
12916 (set_attr "mode" "DI")
12917 (set_attr "length" "7")
12918 (set_attr "length_address" "4")])
12920 (define_insn "*tls_dynamic_gnu2_call_64"
12921 [(set (match_operand:DI 0 "register_operand" "=a")
12922 (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")
12923 (match_operand:DI 2 "register_operand" "0")
12926 (clobber (reg:CC FLAGS_REG))]
12927 "TARGET_64BIT && TARGET_GNU2_TLS"
12928 "call\t{*%a1@TLSCALL(%2)|[QWORD PTR [%2+%a1@TLSCALL]]}"
12929 [(set_attr "type" "call")
12930 (set_attr "length" "2")
12931 (set_attr "length_address" "0")])
12933 (define_insn_and_split "*tls_dynamic_gnu2_combine_64"
12934 [(set (match_operand:DI 0 "register_operand" "=&a")
12936 (unspec:DI [(match_operand:DI 2 "tls_modbase_operand" "")
12937 (match_operand:DI 3 "" "")
12940 (const:DI (unspec:DI
12941 [(match_operand 1 "tls_symbolic_operand" "")]
12943 (clobber (reg:CC FLAGS_REG))]
12944 "TARGET_64BIT && TARGET_GNU2_TLS"
12947 [(set (match_dup 0) (match_dup 4))]
12949 operands[4] = can_create_pseudo_p () ? gen_reg_rtx (Pmode) : operands[0];
12950 emit_insn (gen_tls_dynamic_gnu2_64 (operands[4], operands[1]));
12953 ;; These patterns match the binary 387 instructions for addM3, subM3,
12954 ;; mulM3 and divM3. There are three patterns for each of DFmode and
12955 ;; SFmode. The first is the normal insn, the second the same insn but
12956 ;; with one operand a conversion, and the third the same insn but with
12957 ;; the other operand a conversion. The conversion may be SFmode or
12958 ;; SImode if the target mode DFmode, but only SImode if the target mode
12961 ;; Gcc is slightly more smart about handling normal two address instructions
12962 ;; so use special patterns for add and mull.
12964 (define_insn "*fop_<mode>_comm_mixed"
12965 [(set (match_operand:MODEF 0 "register_operand" "=f,x,x")
12966 (match_operator:MODEF 3 "binary_fp_operator"
12967 [(match_operand:MODEF 1 "nonimmediate_operand" "%0,0,x")
12968 (match_operand:MODEF 2 "nonimmediate_operand" "fm,xm,xm")]))]
12969 "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_MIX_SSE_I387
12970 && COMMUTATIVE_ARITH_P (operands[3])
12971 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
12972 "* return output_387_binary_op (insn, operands);"
12973 [(set (attr "type")
12974 (if_then_else (eq_attr "alternative" "1,2")
12975 (if_then_else (match_operand:MODEF 3 "mult_operator" "")
12976 (const_string "ssemul")
12977 (const_string "sseadd"))
12978 (if_then_else (match_operand:MODEF 3 "mult_operator" "")
12979 (const_string "fmul")
12980 (const_string "fop"))))
12981 (set_attr "isa" "*,noavx,avx")
12982 (set_attr "prefix" "orig,orig,vex")
12983 (set_attr "mode" "<MODE>")])
12985 (define_insn "*fop_<mode>_comm_sse"
12986 [(set (match_operand:MODEF 0 "register_operand" "=x,x")
12987 (match_operator:MODEF 3 "binary_fp_operator"
12988 [(match_operand:MODEF 1 "nonimmediate_operand" "%0,x")
12989 (match_operand:MODEF 2 "nonimmediate_operand" "xm,xm")]))]
12990 "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
12991 && COMMUTATIVE_ARITH_P (operands[3])
12992 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
12993 "* return output_387_binary_op (insn, operands);"
12994 [(set (attr "type")
12995 (if_then_else (match_operand:MODEF 3 "mult_operator" "")
12996 (const_string "ssemul")
12997 (const_string "sseadd")))
12998 (set_attr "isa" "noavx,avx")
12999 (set_attr "prefix" "orig,vex")
13000 (set_attr "mode" "<MODE>")])
13002 (define_insn "*fop_<mode>_comm_i387"
13003 [(set (match_operand:MODEF 0 "register_operand" "=f")
13004 (match_operator:MODEF 3 "binary_fp_operator"
13005 [(match_operand:MODEF 1 "nonimmediate_operand" "%0")
13006 (match_operand:MODEF 2 "nonimmediate_operand" "fm")]))]
13007 "TARGET_80387 && X87_ENABLE_ARITH (<MODE>mode)
13008 && COMMUTATIVE_ARITH_P (operands[3])
13009 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
13010 "* return output_387_binary_op (insn, operands);"
13011 [(set (attr "type")
13012 (if_then_else (match_operand:MODEF 3 "mult_operator" "")
13013 (const_string "fmul")
13014 (const_string "fop")))
13015 (set_attr "mode" "<MODE>")])
13017 (define_insn "*fop_<mode>_1_mixed"
13018 [(set (match_operand:MODEF 0 "register_operand" "=f,f,x,x")
13019 (match_operator:MODEF 3 "binary_fp_operator"
13020 [(match_operand:MODEF 1 "nonimmediate_operand" "0,fm,0,x")
13021 (match_operand:MODEF 2 "nonimmediate_operand" "fm,0,xm,xm")]))]
13022 "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_MIX_SSE_I387
13023 && !COMMUTATIVE_ARITH_P (operands[3])
13024 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
13025 "* return output_387_binary_op (insn, operands);"
13026 [(set (attr "type")
13027 (cond [(and (eq_attr "alternative" "2,3")
13028 (match_operand:MODEF 3 "mult_operator" ""))
13029 (const_string "ssemul")
13030 (and (eq_attr "alternative" "2,3")
13031 (match_operand:MODEF 3 "div_operator" ""))
13032 (const_string "ssediv")
13033 (eq_attr "alternative" "2,3")
13034 (const_string "sseadd")
13035 (match_operand:MODEF 3 "mult_operator" "")
13036 (const_string "fmul")
13037 (match_operand:MODEF 3 "div_operator" "")
13038 (const_string "fdiv")
13040 (const_string "fop")))
13041 (set_attr "isa" "*,*,noavx,avx")
13042 (set_attr "prefix" "orig,orig,orig,vex")
13043 (set_attr "mode" "<MODE>")])
13045 (define_insn "*rcpsf2_sse"
13046 [(set (match_operand:SF 0 "register_operand" "=x")
13047 (unspec:SF [(match_operand:SF 1 "nonimmediate_operand" "xm")]
13050 "%vrcpss\t{%1, %d0|%d0, %1}"
13051 [(set_attr "type" "sse")
13052 (set_attr "atom_sse_attr" "rcp")
13053 (set_attr "prefix" "maybe_vex")
13054 (set_attr "mode" "SF")])
13056 (define_insn "*fop_<mode>_1_sse"
13057 [(set (match_operand:MODEF 0 "register_operand" "=x,x")
13058 (match_operator:MODEF 3 "binary_fp_operator"
13059 [(match_operand:MODEF 1 "register_operand" "0,x")
13060 (match_operand:MODEF 2 "nonimmediate_operand" "xm,xm")]))]
13061 "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
13062 && !COMMUTATIVE_ARITH_P (operands[3])"
13063 "* return output_387_binary_op (insn, operands);"
13064 [(set (attr "type")
13065 (cond [(match_operand:MODEF 3 "mult_operator" "")
13066 (const_string "ssemul")
13067 (match_operand:MODEF 3 "div_operator" "")
13068 (const_string "ssediv")
13070 (const_string "sseadd")))
13071 (set_attr "isa" "noavx,avx")
13072 (set_attr "prefix" "orig,vex")
13073 (set_attr "mode" "<MODE>")])
13075 ;; This pattern is not fully shadowed by the pattern above.
13076 (define_insn "*fop_<mode>_1_i387"
13077 [(set (match_operand:MODEF 0 "register_operand" "=f,f")
13078 (match_operator:MODEF 3 "binary_fp_operator"
13079 [(match_operand:MODEF 1 "nonimmediate_operand" "0,fm")
13080 (match_operand:MODEF 2 "nonimmediate_operand" "fm,0")]))]
13081 "TARGET_80387 && X87_ENABLE_ARITH (<MODE>mode)
13082 && !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
13083 && !COMMUTATIVE_ARITH_P (operands[3])
13084 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
13085 "* return output_387_binary_op (insn, operands);"
13086 [(set (attr "type")
13087 (cond [(match_operand:MODEF 3 "mult_operator" "")
13088 (const_string "fmul")
13089 (match_operand:MODEF 3 "div_operator" "")
13090 (const_string "fdiv")
13092 (const_string "fop")))
13093 (set_attr "mode" "<MODE>")])
13095 ;; ??? Add SSE splitters for these!
13096 (define_insn "*fop_<MODEF:mode>_2_i387"
13097 [(set (match_operand:MODEF 0 "register_operand" "=f,f")
13098 (match_operator:MODEF 3 "binary_fp_operator"
13100 (match_operand:SWI24 1 "nonimmediate_operand" "m,?r"))
13101 (match_operand:MODEF 2 "register_operand" "0,0")]))]
13102 "TARGET_80387 && X87_ENABLE_FLOAT (<MODEF:MODE>mode, <SWI24:MODE>mode)
13103 && !(SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH)
13104 && (TARGET_USE_<SWI24:MODE>MODE_FIOP || optimize_function_for_size_p (cfun))"
13105 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
13106 [(set (attr "type")
13107 (cond [(match_operand:MODEF 3 "mult_operator" "")
13108 (const_string "fmul")
13109 (match_operand:MODEF 3 "div_operator" "")
13110 (const_string "fdiv")
13112 (const_string "fop")))
13113 (set_attr "fp_int_src" "true")
13114 (set_attr "mode" "<SWI24:MODE>")])
13116 (define_insn "*fop_<MODEF:mode>_3_i387"
13117 [(set (match_operand:MODEF 0 "register_operand" "=f,f")
13118 (match_operator:MODEF 3 "binary_fp_operator"
13119 [(match_operand:MODEF 1 "register_operand" "0,0")
13121 (match_operand:SWI24 2 "nonimmediate_operand" "m,?r"))]))]
13122 "TARGET_80387 && X87_ENABLE_FLOAT (<MODEF:MODE>mode, <SWI24:MODE>mode)
13123 && !(SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH)
13124 && (TARGET_USE_<SWI24:MODE>MODE_FIOP || optimize_function_for_size_p (cfun))"
13125 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
13126 [(set (attr "type")
13127 (cond [(match_operand:MODEF 3 "mult_operator" "")
13128 (const_string "fmul")
13129 (match_operand:MODEF 3 "div_operator" "")
13130 (const_string "fdiv")
13132 (const_string "fop")))
13133 (set_attr "fp_int_src" "true")
13134 (set_attr "mode" "<MODE>")])
13136 (define_insn "*fop_df_4_i387"
13137 [(set (match_operand:DF 0 "register_operand" "=f,f")
13138 (match_operator:DF 3 "binary_fp_operator"
13140 (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
13141 (match_operand:DF 2 "register_operand" "0,f")]))]
13142 "TARGET_80387 && X87_ENABLE_ARITH (DFmode)
13143 && !(TARGET_SSE2 && TARGET_SSE_MATH)
13144 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
13145 "* return output_387_binary_op (insn, operands);"
13146 [(set (attr "type")
13147 (cond [(match_operand:DF 3 "mult_operator" "")
13148 (const_string "fmul")
13149 (match_operand:DF 3 "div_operator" "")
13150 (const_string "fdiv")
13152 (const_string "fop")))
13153 (set_attr "mode" "SF")])
13155 (define_insn "*fop_df_5_i387"
13156 [(set (match_operand:DF 0 "register_operand" "=f,f")
13157 (match_operator:DF 3 "binary_fp_operator"
13158 [(match_operand:DF 1 "register_operand" "0,f")
13160 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
13161 "TARGET_80387 && X87_ENABLE_ARITH (DFmode)
13162 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
13163 "* return output_387_binary_op (insn, operands);"
13164 [(set (attr "type")
13165 (cond [(match_operand:DF 3 "mult_operator" "")
13166 (const_string "fmul")
13167 (match_operand:DF 3 "div_operator" "")
13168 (const_string "fdiv")
13170 (const_string "fop")))
13171 (set_attr "mode" "SF")])
13173 (define_insn "*fop_df_6_i387"
13174 [(set (match_operand:DF 0 "register_operand" "=f,f")
13175 (match_operator:DF 3 "binary_fp_operator"
13177 (match_operand:SF 1 "register_operand" "0,f"))
13179 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
13180 "TARGET_80387 && X87_ENABLE_ARITH (DFmode)
13181 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
13182 "* return output_387_binary_op (insn, operands);"
13183 [(set (attr "type")
13184 (cond [(match_operand:DF 3 "mult_operator" "")
13185 (const_string "fmul")
13186 (match_operand:DF 3 "div_operator" "")
13187 (const_string "fdiv")
13189 (const_string "fop")))
13190 (set_attr "mode" "SF")])
13192 (define_insn "*fop_xf_comm_i387"
13193 [(set (match_operand:XF 0 "register_operand" "=f")
13194 (match_operator:XF 3 "binary_fp_operator"
13195 [(match_operand:XF 1 "register_operand" "%0")
13196 (match_operand:XF 2 "register_operand" "f")]))]
13198 && COMMUTATIVE_ARITH_P (operands[3])"
13199 "* return output_387_binary_op (insn, operands);"
13200 [(set (attr "type")
13201 (if_then_else (match_operand:XF 3 "mult_operator" "")
13202 (const_string "fmul")
13203 (const_string "fop")))
13204 (set_attr "mode" "XF")])
13206 (define_insn "*fop_xf_1_i387"
13207 [(set (match_operand:XF 0 "register_operand" "=f,f")
13208 (match_operator:XF 3 "binary_fp_operator"
13209 [(match_operand:XF 1 "register_operand" "0,f")
13210 (match_operand:XF 2 "register_operand" "f,0")]))]
13212 && !COMMUTATIVE_ARITH_P (operands[3])"
13213 "* return output_387_binary_op (insn, operands);"
13214 [(set (attr "type")
13215 (cond [(match_operand:XF 3 "mult_operator" "")
13216 (const_string "fmul")
13217 (match_operand:XF 3 "div_operator" "")
13218 (const_string "fdiv")
13220 (const_string "fop")))
13221 (set_attr "mode" "XF")])
13223 (define_insn "*fop_xf_2_i387"
13224 [(set (match_operand:XF 0 "register_operand" "=f,f")
13225 (match_operator:XF 3 "binary_fp_operator"
13227 (match_operand:SWI24 1 "nonimmediate_operand" "m,?r"))
13228 (match_operand:XF 2 "register_operand" "0,0")]))]
13229 "TARGET_80387 && (TARGET_USE_<MODE>MODE_FIOP || optimize_function_for_size_p (cfun))"
13230 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
13231 [(set (attr "type")
13232 (cond [(match_operand:XF 3 "mult_operator" "")
13233 (const_string "fmul")
13234 (match_operand:XF 3 "div_operator" "")
13235 (const_string "fdiv")
13237 (const_string "fop")))
13238 (set_attr "fp_int_src" "true")
13239 (set_attr "mode" "<MODE>")])
13241 (define_insn "*fop_xf_3_i387"
13242 [(set (match_operand:XF 0 "register_operand" "=f,f")
13243 (match_operator:XF 3 "binary_fp_operator"
13244 [(match_operand:XF 1 "register_operand" "0,0")
13246 (match_operand:SWI24 2 "nonimmediate_operand" "m,?r"))]))]
13247 "TARGET_80387 && (TARGET_USE_<MODE>MODE_FIOP || optimize_function_for_size_p (cfun))"
13248 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
13249 [(set (attr "type")
13250 (cond [(match_operand:XF 3 "mult_operator" "")
13251 (const_string "fmul")
13252 (match_operand:XF 3 "div_operator" "")
13253 (const_string "fdiv")
13255 (const_string "fop")))
13256 (set_attr "fp_int_src" "true")
13257 (set_attr "mode" "<MODE>")])
13259 (define_insn "*fop_xf_4_i387"
13260 [(set (match_operand:XF 0 "register_operand" "=f,f")
13261 (match_operator:XF 3 "binary_fp_operator"
13263 (match_operand:MODEF 1 "nonimmediate_operand" "fm,0"))
13264 (match_operand:XF 2 "register_operand" "0,f")]))]
13266 "* return output_387_binary_op (insn, operands);"
13267 [(set (attr "type")
13268 (cond [(match_operand:XF 3 "mult_operator" "")
13269 (const_string "fmul")
13270 (match_operand:XF 3 "div_operator" "")
13271 (const_string "fdiv")
13273 (const_string "fop")))
13274 (set_attr "mode" "<MODE>")])
13276 (define_insn "*fop_xf_5_i387"
13277 [(set (match_operand:XF 0 "register_operand" "=f,f")
13278 (match_operator:XF 3 "binary_fp_operator"
13279 [(match_operand:XF 1 "register_operand" "0,f")
13281 (match_operand:MODEF 2 "nonimmediate_operand" "fm,0"))]))]
13283 "* return output_387_binary_op (insn, operands);"
13284 [(set (attr "type")
13285 (cond [(match_operand:XF 3 "mult_operator" "")
13286 (const_string "fmul")
13287 (match_operand:XF 3 "div_operator" "")
13288 (const_string "fdiv")
13290 (const_string "fop")))
13291 (set_attr "mode" "<MODE>")])
13293 (define_insn "*fop_xf_6_i387"
13294 [(set (match_operand:XF 0 "register_operand" "=f,f")
13295 (match_operator:XF 3 "binary_fp_operator"
13297 (match_operand:MODEF 1 "register_operand" "0,f"))
13299 (match_operand:MODEF 2 "nonimmediate_operand" "fm,0"))]))]
13301 "* return output_387_binary_op (insn, operands);"
13302 [(set (attr "type")
13303 (cond [(match_operand:XF 3 "mult_operator" "")
13304 (const_string "fmul")
13305 (match_operand:XF 3 "div_operator" "")
13306 (const_string "fdiv")
13308 (const_string "fop")))
13309 (set_attr "mode" "<MODE>")])
13312 [(set (match_operand 0 "register_operand" "")
13313 (match_operator 3 "binary_fp_operator"
13314 [(float (match_operand:SWI24 1 "register_operand" ""))
13315 (match_operand 2 "register_operand" "")]))]
13317 && X87_FLOAT_MODE_P (GET_MODE (operands[0]))
13318 && X87_ENABLE_FLOAT (GET_MODE (operands[0]), GET_MODE (operands[1]))"
13321 operands[4] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
13322 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
13323 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
13324 gen_rtx_fmt_ee (GET_CODE (operands[3]),
13325 GET_MODE (operands[3]),
13328 ix86_free_from_memory (GET_MODE (operands[1]));
13333 [(set (match_operand 0 "register_operand" "")
13334 (match_operator 3 "binary_fp_operator"
13335 [(match_operand 1 "register_operand" "")
13336 (float (match_operand:SWI24 2 "register_operand" ""))]))]
13338 && X87_FLOAT_MODE_P (GET_MODE (operands[0]))
13339 && X87_ENABLE_FLOAT (GET_MODE (operands[0]), GET_MODE (operands[2]))"
13342 operands[4] = ix86_force_to_memory (GET_MODE (operands[2]), operands[2]);
13343 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
13344 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
13345 gen_rtx_fmt_ee (GET_CODE (operands[3]),
13346 GET_MODE (operands[3]),
13349 ix86_free_from_memory (GET_MODE (operands[2]));
13353 ;; FPU special functions.
13355 ;; This pattern implements a no-op XFmode truncation for
13356 ;; all fancy i386 XFmode math functions.
13358 (define_insn "truncxf<mode>2_i387_noop_unspec"
13359 [(set (match_operand:MODEF 0 "register_operand" "=f")
13360 (unspec:MODEF [(match_operand:XF 1 "register_operand" "f")]
13361 UNSPEC_TRUNC_NOOP))]
13362 "TARGET_USE_FANCY_MATH_387"
13363 "* return output_387_reg_move (insn, operands);"
13364 [(set_attr "type" "fmov")
13365 (set_attr "mode" "<MODE>")])
13367 (define_insn "sqrtxf2"
13368 [(set (match_operand:XF 0 "register_operand" "=f")
13369 (sqrt:XF (match_operand:XF 1 "register_operand" "0")))]
13370 "TARGET_USE_FANCY_MATH_387"
13372 [(set_attr "type" "fpspc")
13373 (set_attr "mode" "XF")
13374 (set_attr "athlon_decode" "direct")
13375 (set_attr "amdfam10_decode" "direct")
13376 (set_attr "bdver1_decode" "direct")])
13378 (define_insn "sqrt_extend<mode>xf2_i387"
13379 [(set (match_operand:XF 0 "register_operand" "=f")
13382 (match_operand:MODEF 1 "register_operand" "0"))))]
13383 "TARGET_USE_FANCY_MATH_387"
13385 [(set_attr "type" "fpspc")
13386 (set_attr "mode" "XF")
13387 (set_attr "athlon_decode" "direct")
13388 (set_attr "amdfam10_decode" "direct")
13389 (set_attr "bdver1_decode" "direct")])
13391 (define_insn "*rsqrtsf2_sse"
13392 [(set (match_operand:SF 0 "register_operand" "=x")
13393 (unspec:SF [(match_operand:SF 1 "nonimmediate_operand" "xm")]
13396 "%vrsqrtss\t{%1, %d0|%d0, %1}"
13397 [(set_attr "type" "sse")
13398 (set_attr "atom_sse_attr" "rcp")
13399 (set_attr "prefix" "maybe_vex")
13400 (set_attr "mode" "SF")])
13402 (define_expand "rsqrtsf2"
13403 [(set (match_operand:SF 0 "register_operand" "")
13404 (unspec:SF [(match_operand:SF 1 "nonimmediate_operand" "")]
13408 ix86_emit_swsqrtsf (operands[0], operands[1], SFmode, 1);
13412 (define_insn "*sqrt<mode>2_sse"
13413 [(set (match_operand:MODEF 0 "register_operand" "=x")
13415 (match_operand:MODEF 1 "nonimmediate_operand" "xm")))]
13416 "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
13417 "%vsqrt<ssemodesuffix>\t{%1, %d0|%d0, %1}"
13418 [(set_attr "type" "sse")
13419 (set_attr "atom_sse_attr" "sqrt")
13420 (set_attr "prefix" "maybe_vex")
13421 (set_attr "mode" "<MODE>")
13422 (set_attr "athlon_decode" "*")
13423 (set_attr "amdfam10_decode" "*")
13424 (set_attr "bdver1_decode" "*")])
13426 (define_expand "sqrt<mode>2"
13427 [(set (match_operand:MODEF 0 "register_operand" "")
13429 (match_operand:MODEF 1 "nonimmediate_operand" "")))]
13430 "(TARGET_USE_FANCY_MATH_387 && X87_ENABLE_ARITH (<MODE>mode))
13431 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
13433 if (<MODE>mode == SFmode
13435 && TARGET_RECIP_SQRT
13436 && !optimize_function_for_size_p (cfun)
13437 && flag_finite_math_only && !flag_trapping_math
13438 && flag_unsafe_math_optimizations)
13440 ix86_emit_swsqrtsf (operands[0], operands[1], SFmode, 0);
13444 if (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH))
13446 rtx op0 = gen_reg_rtx (XFmode);
13447 rtx op1 = force_reg (<MODE>mode, operands[1]);
13449 emit_insn (gen_sqrt_extend<mode>xf2_i387 (op0, op1));
13450 emit_insn (gen_truncxf<mode>2_i387_noop_unspec (operands[0], op0));
13455 (define_insn "fpremxf4_i387"
13456 [(set (match_operand:XF 0 "register_operand" "=f")
13457 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
13458 (match_operand:XF 3 "register_operand" "1")]
13460 (set (match_operand:XF 1 "register_operand" "=u")
13461 (unspec:XF [(match_dup 2) (match_dup 3)]
13463 (set (reg:CCFP FPSR_REG)
13464 (unspec:CCFP [(match_dup 2) (match_dup 3)]
13466 "TARGET_USE_FANCY_MATH_387"
13468 [(set_attr "type" "fpspc")
13469 (set_attr "mode" "XF")])
13471 (define_expand "fmodxf3"
13472 [(use (match_operand:XF 0 "register_operand" ""))
13473 (use (match_operand:XF 1 "general_operand" ""))
13474 (use (match_operand:XF 2 "general_operand" ""))]
13475 "TARGET_USE_FANCY_MATH_387"
13477 rtx label = gen_label_rtx ();
13479 rtx op1 = gen_reg_rtx (XFmode);
13480 rtx op2 = gen_reg_rtx (XFmode);
13482 emit_move_insn (op2, operands[2]);
13483 emit_move_insn (op1, operands[1]);
13485 emit_label (label);
13486 emit_insn (gen_fpremxf4_i387 (op1, op2, op1, op2));
13487 ix86_emit_fp_unordered_jump (label);
13488 LABEL_NUSES (label) = 1;
13490 emit_move_insn (operands[0], op1);
13494 (define_expand "fmod<mode>3"
13495 [(use (match_operand:MODEF 0 "register_operand" ""))
13496 (use (match_operand:MODEF 1 "general_operand" ""))
13497 (use (match_operand:MODEF 2 "general_operand" ""))]
13498 "TARGET_USE_FANCY_MATH_387"
13500 rtx (*gen_truncxf) (rtx, rtx);
13502 rtx label = gen_label_rtx ();
13504 rtx op1 = gen_reg_rtx (XFmode);
13505 rtx op2 = gen_reg_rtx (XFmode);
13507 emit_insn (gen_extend<mode>xf2 (op2, operands[2]));
13508 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
13510 emit_label (label);
13511 emit_insn (gen_fpremxf4_i387 (op1, op2, op1, op2));
13512 ix86_emit_fp_unordered_jump (label);
13513 LABEL_NUSES (label) = 1;
13515 /* Truncate the result properly for strict SSE math. */
13516 if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
13517 && !TARGET_MIX_SSE_I387)
13518 gen_truncxf = gen_truncxf<mode>2;
13520 gen_truncxf = gen_truncxf<mode>2_i387_noop_unspec;
13522 emit_insn (gen_truncxf (operands[0], op1));
13526 (define_insn "fprem1xf4_i387"
13527 [(set (match_operand:XF 0 "register_operand" "=f")
13528 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
13529 (match_operand:XF 3 "register_operand" "1")]
13531 (set (match_operand:XF 1 "register_operand" "=u")
13532 (unspec:XF [(match_dup 2) (match_dup 3)]
13534 (set (reg:CCFP FPSR_REG)
13535 (unspec:CCFP [(match_dup 2) (match_dup 3)]
13537 "TARGET_USE_FANCY_MATH_387"
13539 [(set_attr "type" "fpspc")
13540 (set_attr "mode" "XF")])
13542 (define_expand "remainderxf3"
13543 [(use (match_operand:XF 0 "register_operand" ""))
13544 (use (match_operand:XF 1 "general_operand" ""))
13545 (use (match_operand:XF 2 "general_operand" ""))]
13546 "TARGET_USE_FANCY_MATH_387"
13548 rtx label = gen_label_rtx ();
13550 rtx op1 = gen_reg_rtx (XFmode);
13551 rtx op2 = gen_reg_rtx (XFmode);
13553 emit_move_insn (op2, operands[2]);
13554 emit_move_insn (op1, operands[1]);
13556 emit_label (label);
13557 emit_insn (gen_fprem1xf4_i387 (op1, op2, op1, op2));
13558 ix86_emit_fp_unordered_jump (label);
13559 LABEL_NUSES (label) = 1;
13561 emit_move_insn (operands[0], op1);
13565 (define_expand "remainder<mode>3"
13566 [(use (match_operand:MODEF 0 "register_operand" ""))
13567 (use (match_operand:MODEF 1 "general_operand" ""))
13568 (use (match_operand:MODEF 2 "general_operand" ""))]
13569 "TARGET_USE_FANCY_MATH_387"
13571 rtx (*gen_truncxf) (rtx, rtx);
13573 rtx label = gen_label_rtx ();
13575 rtx op1 = gen_reg_rtx (XFmode);
13576 rtx op2 = gen_reg_rtx (XFmode);
13578 emit_insn (gen_extend<mode>xf2 (op2, operands[2]));
13579 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
13581 emit_label (label);
13583 emit_insn (gen_fprem1xf4_i387 (op1, op2, op1, op2));
13584 ix86_emit_fp_unordered_jump (label);
13585 LABEL_NUSES (label) = 1;
13587 /* Truncate the result properly for strict SSE math. */
13588 if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
13589 && !TARGET_MIX_SSE_I387)
13590 gen_truncxf = gen_truncxf<mode>2;
13592 gen_truncxf = gen_truncxf<mode>2_i387_noop_unspec;
13594 emit_insn (gen_truncxf (operands[0], op1));
13598 (define_insn "*sinxf2_i387"
13599 [(set (match_operand:XF 0 "register_operand" "=f")
13600 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_SIN))]
13601 "TARGET_USE_FANCY_MATH_387
13602 && flag_unsafe_math_optimizations"
13604 [(set_attr "type" "fpspc")
13605 (set_attr "mode" "XF")])
13607 (define_insn "*sin_extend<mode>xf2_i387"
13608 [(set (match_operand:XF 0 "register_operand" "=f")
13609 (unspec:XF [(float_extend:XF
13610 (match_operand:MODEF 1 "register_operand" "0"))]
13612 "TARGET_USE_FANCY_MATH_387
13613 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
13614 || TARGET_MIX_SSE_I387)
13615 && flag_unsafe_math_optimizations"
13617 [(set_attr "type" "fpspc")
13618 (set_attr "mode" "XF")])
13620 (define_insn "*cosxf2_i387"
13621 [(set (match_operand:XF 0 "register_operand" "=f")
13622 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_COS))]
13623 "TARGET_USE_FANCY_MATH_387
13624 && flag_unsafe_math_optimizations"
13626 [(set_attr "type" "fpspc")
13627 (set_attr "mode" "XF")])
13629 (define_insn "*cos_extend<mode>xf2_i387"
13630 [(set (match_operand:XF 0 "register_operand" "=f")
13631 (unspec:XF [(float_extend:XF
13632 (match_operand:MODEF 1 "register_operand" "0"))]
13634 "TARGET_USE_FANCY_MATH_387
13635 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
13636 || TARGET_MIX_SSE_I387)
13637 && flag_unsafe_math_optimizations"
13639 [(set_attr "type" "fpspc")
13640 (set_attr "mode" "XF")])
13642 ;; When sincos pattern is defined, sin and cos builtin functions will be
13643 ;; expanded to sincos pattern with one of its outputs left unused.
13644 ;; CSE pass will figure out if two sincos patterns can be combined,
13645 ;; otherwise sincos pattern will be split back to sin or cos pattern,
13646 ;; depending on the unused output.
13648 (define_insn "sincosxf3"
13649 [(set (match_operand:XF 0 "register_operand" "=f")
13650 (unspec:XF [(match_operand:XF 2 "register_operand" "0")]
13651 UNSPEC_SINCOS_COS))
13652 (set (match_operand:XF 1 "register_operand" "=u")
13653 (unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
13654 "TARGET_USE_FANCY_MATH_387
13655 && flag_unsafe_math_optimizations"
13657 [(set_attr "type" "fpspc")
13658 (set_attr "mode" "XF")])
13661 [(set (match_operand:XF 0 "register_operand" "")
13662 (unspec:XF [(match_operand:XF 2 "register_operand" "")]
13663 UNSPEC_SINCOS_COS))
13664 (set (match_operand:XF 1 "register_operand" "")
13665 (unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
13666 "find_regno_note (insn, REG_UNUSED, REGNO (operands[0]))
13667 && can_create_pseudo_p ()"
13668 [(set (match_dup 1) (unspec:XF [(match_dup 2)] UNSPEC_SIN))])
13671 [(set (match_operand:XF 0 "register_operand" "")
13672 (unspec:XF [(match_operand:XF 2 "register_operand" "")]
13673 UNSPEC_SINCOS_COS))
13674 (set (match_operand:XF 1 "register_operand" "")
13675 (unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
13676 "find_regno_note (insn, REG_UNUSED, REGNO (operands[1]))
13677 && can_create_pseudo_p ()"
13678 [(set (match_dup 0) (unspec:XF [(match_dup 2)] UNSPEC_COS))])
13680 (define_insn "sincos_extend<mode>xf3_i387"
13681 [(set (match_operand:XF 0 "register_operand" "=f")
13682 (unspec:XF [(float_extend:XF
13683 (match_operand:MODEF 2 "register_operand" "0"))]
13684 UNSPEC_SINCOS_COS))
13685 (set (match_operand:XF 1 "register_operand" "=u")
13686 (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SINCOS_SIN))]
13687 "TARGET_USE_FANCY_MATH_387
13688 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
13689 || TARGET_MIX_SSE_I387)
13690 && flag_unsafe_math_optimizations"
13692 [(set_attr "type" "fpspc")
13693 (set_attr "mode" "XF")])
13696 [(set (match_operand:XF 0 "register_operand" "")
13697 (unspec:XF [(float_extend:XF
13698 (match_operand:MODEF 2 "register_operand" ""))]
13699 UNSPEC_SINCOS_COS))
13700 (set (match_operand:XF 1 "register_operand" "")
13701 (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SINCOS_SIN))]
13702 "find_regno_note (insn, REG_UNUSED, REGNO (operands[0]))
13703 && can_create_pseudo_p ()"
13704 [(set (match_dup 1)
13705 (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SIN))])
13708 [(set (match_operand:XF 0 "register_operand" "")
13709 (unspec:XF [(float_extend:XF
13710 (match_operand:MODEF 2 "register_operand" ""))]
13711 UNSPEC_SINCOS_COS))
13712 (set (match_operand:XF 1 "register_operand" "")
13713 (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SINCOS_SIN))]
13714 "find_regno_note (insn, REG_UNUSED, REGNO (operands[1]))
13715 && can_create_pseudo_p ()"
13716 [(set (match_dup 0)
13717 (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_COS))])
13719 (define_expand "sincos<mode>3"
13720 [(use (match_operand:MODEF 0 "register_operand" ""))
13721 (use (match_operand:MODEF 1 "register_operand" ""))
13722 (use (match_operand:MODEF 2 "register_operand" ""))]
13723 "TARGET_USE_FANCY_MATH_387
13724 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
13725 || TARGET_MIX_SSE_I387)
13726 && flag_unsafe_math_optimizations"
13728 rtx op0 = gen_reg_rtx (XFmode);
13729 rtx op1 = gen_reg_rtx (XFmode);
13731 emit_insn (gen_sincos_extend<mode>xf3_i387 (op0, op1, operands[2]));
13732 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
13733 emit_insn (gen_truncxf<mode>2_i387_noop (operands[1], op1));
13737 (define_insn "fptanxf4_i387"
13738 [(set (match_operand:XF 0 "register_operand" "=f")
13739 (match_operand:XF 3 "const_double_operand" "F"))
13740 (set (match_operand:XF 1 "register_operand" "=u")
13741 (unspec:XF [(match_operand:XF 2 "register_operand" "0")]
13743 "TARGET_USE_FANCY_MATH_387
13744 && flag_unsafe_math_optimizations
13745 && standard_80387_constant_p (operands[3]) == 2"
13747 [(set_attr "type" "fpspc")
13748 (set_attr "mode" "XF")])
13750 (define_insn "fptan_extend<mode>xf4_i387"
13751 [(set (match_operand:MODEF 0 "register_operand" "=f")
13752 (match_operand:MODEF 3 "const_double_operand" "F"))
13753 (set (match_operand:XF 1 "register_operand" "=u")
13754 (unspec:XF [(float_extend:XF
13755 (match_operand:MODEF 2 "register_operand" "0"))]
13757 "TARGET_USE_FANCY_MATH_387
13758 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
13759 || TARGET_MIX_SSE_I387)
13760 && flag_unsafe_math_optimizations
13761 && standard_80387_constant_p (operands[3]) == 2"
13763 [(set_attr "type" "fpspc")
13764 (set_attr "mode" "XF")])
13766 (define_expand "tanxf2"
13767 [(use (match_operand:XF 0 "register_operand" ""))
13768 (use (match_operand:XF 1 "register_operand" ""))]
13769 "TARGET_USE_FANCY_MATH_387
13770 && flag_unsafe_math_optimizations"
13772 rtx one = gen_reg_rtx (XFmode);
13773 rtx op2 = CONST1_RTX (XFmode); /* fld1 */
13775 emit_insn (gen_fptanxf4_i387 (one, operands[0], operands[1], op2));
13779 (define_expand "tan<mode>2"
13780 [(use (match_operand:MODEF 0 "register_operand" ""))
13781 (use (match_operand:MODEF 1 "register_operand" ""))]
13782 "TARGET_USE_FANCY_MATH_387
13783 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
13784 || TARGET_MIX_SSE_I387)
13785 && flag_unsafe_math_optimizations"
13787 rtx op0 = gen_reg_rtx (XFmode);
13789 rtx one = gen_reg_rtx (<MODE>mode);
13790 rtx op2 = CONST1_RTX (<MODE>mode); /* fld1 */
13792 emit_insn (gen_fptan_extend<mode>xf4_i387 (one, op0,
13793 operands[1], op2));
13794 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
13798 (define_insn "*fpatanxf3_i387"
13799 [(set (match_operand:XF 0 "register_operand" "=f")
13800 (unspec:XF [(match_operand:XF 1 "register_operand" "0")
13801 (match_operand:XF 2 "register_operand" "u")]
13803 (clobber (match_scratch:XF 3 "=2"))]
13804 "TARGET_USE_FANCY_MATH_387
13805 && flag_unsafe_math_optimizations"
13807 [(set_attr "type" "fpspc")
13808 (set_attr "mode" "XF")])
13810 (define_insn "fpatan_extend<mode>xf3_i387"
13811 [(set (match_operand:XF 0 "register_operand" "=f")
13812 (unspec:XF [(float_extend:XF
13813 (match_operand:MODEF 1 "register_operand" "0"))
13815 (match_operand:MODEF 2 "register_operand" "u"))]
13817 (clobber (match_scratch:XF 3 "=2"))]
13818 "TARGET_USE_FANCY_MATH_387
13819 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
13820 || TARGET_MIX_SSE_I387)
13821 && flag_unsafe_math_optimizations"
13823 [(set_attr "type" "fpspc")
13824 (set_attr "mode" "XF")])
13826 (define_expand "atan2xf3"
13827 [(parallel [(set (match_operand:XF 0 "register_operand" "")
13828 (unspec:XF [(match_operand:XF 2 "register_operand" "")
13829 (match_operand:XF 1 "register_operand" "")]
13831 (clobber (match_scratch:XF 3 ""))])]
13832 "TARGET_USE_FANCY_MATH_387
13833 && flag_unsafe_math_optimizations")
13835 (define_expand "atan2<mode>3"
13836 [(use (match_operand:MODEF 0 "register_operand" ""))
13837 (use (match_operand:MODEF 1 "register_operand" ""))
13838 (use (match_operand:MODEF 2 "register_operand" ""))]
13839 "TARGET_USE_FANCY_MATH_387
13840 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
13841 || TARGET_MIX_SSE_I387)
13842 && flag_unsafe_math_optimizations"
13844 rtx op0 = gen_reg_rtx (XFmode);
13846 emit_insn (gen_fpatan_extend<mode>xf3_i387 (op0, operands[2], operands[1]));
13847 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
13851 (define_expand "atanxf2"
13852 [(parallel [(set (match_operand:XF 0 "register_operand" "")
13853 (unspec:XF [(match_dup 2)
13854 (match_operand:XF 1 "register_operand" "")]
13856 (clobber (match_scratch:XF 3 ""))])]
13857 "TARGET_USE_FANCY_MATH_387
13858 && flag_unsafe_math_optimizations"
13860 operands[2] = gen_reg_rtx (XFmode);
13861 emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */
13864 (define_expand "atan<mode>2"
13865 [(use (match_operand:MODEF 0 "register_operand" ""))
13866 (use (match_operand:MODEF 1 "register_operand" ""))]
13867 "TARGET_USE_FANCY_MATH_387
13868 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
13869 || TARGET_MIX_SSE_I387)
13870 && flag_unsafe_math_optimizations"
13872 rtx op0 = gen_reg_rtx (XFmode);
13874 rtx op2 = gen_reg_rtx (<MODE>mode);
13875 emit_move_insn (op2, CONST1_RTX (<MODE>mode)); /* fld1 */
13877 emit_insn (gen_fpatan_extend<mode>xf3_i387 (op0, op2, operands[1]));
13878 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
13882 (define_expand "asinxf2"
13883 [(set (match_dup 2)
13884 (mult:XF (match_operand:XF 1 "register_operand" "")
13886 (set (match_dup 4) (minus:XF (match_dup 3) (match_dup 2)))
13887 (set (match_dup 5) (sqrt:XF (match_dup 4)))
13888 (parallel [(set (match_operand:XF 0 "register_operand" "")
13889 (unspec:XF [(match_dup 5) (match_dup 1)]
13891 (clobber (match_scratch:XF 6 ""))])]
13892 "TARGET_USE_FANCY_MATH_387
13893 && flag_unsafe_math_optimizations"
13897 if (optimize_insn_for_size_p ())
13900 for (i = 2; i < 6; i++)
13901 operands[i] = gen_reg_rtx (XFmode);
13903 emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */
13906 (define_expand "asin<mode>2"
13907 [(use (match_operand:MODEF 0 "register_operand" ""))
13908 (use (match_operand:MODEF 1 "general_operand" ""))]
13909 "TARGET_USE_FANCY_MATH_387
13910 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
13911 || TARGET_MIX_SSE_I387)
13912 && flag_unsafe_math_optimizations"
13914 rtx op0 = gen_reg_rtx (XFmode);
13915 rtx op1 = gen_reg_rtx (XFmode);
13917 if (optimize_insn_for_size_p ())
13920 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
13921 emit_insn (gen_asinxf2 (op0, op1));
13922 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
13926 (define_expand "acosxf2"
13927 [(set (match_dup 2)
13928 (mult:XF (match_operand:XF 1 "register_operand" "")
13930 (set (match_dup 4) (minus:XF (match_dup 3) (match_dup 2)))
13931 (set (match_dup 5) (sqrt:XF (match_dup 4)))
13932 (parallel [(set (match_operand:XF 0 "register_operand" "")
13933 (unspec:XF [(match_dup 1) (match_dup 5)]
13935 (clobber (match_scratch:XF 6 ""))])]
13936 "TARGET_USE_FANCY_MATH_387
13937 && flag_unsafe_math_optimizations"
13941 if (optimize_insn_for_size_p ())
13944 for (i = 2; i < 6; i++)
13945 operands[i] = gen_reg_rtx (XFmode);
13947 emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */
13950 (define_expand "acos<mode>2"
13951 [(use (match_operand:MODEF 0 "register_operand" ""))
13952 (use (match_operand:MODEF 1 "general_operand" ""))]
13953 "TARGET_USE_FANCY_MATH_387
13954 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
13955 || TARGET_MIX_SSE_I387)
13956 && flag_unsafe_math_optimizations"
13958 rtx op0 = gen_reg_rtx (XFmode);
13959 rtx op1 = gen_reg_rtx (XFmode);
13961 if (optimize_insn_for_size_p ())
13964 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
13965 emit_insn (gen_acosxf2 (op0, op1));
13966 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
13970 (define_insn "fyl2xxf3_i387"
13971 [(set (match_operand:XF 0 "register_operand" "=f")
13972 (unspec:XF [(match_operand:XF 1 "register_operand" "0")
13973 (match_operand:XF 2 "register_operand" "u")]
13975 (clobber (match_scratch:XF 3 "=2"))]
13976 "TARGET_USE_FANCY_MATH_387
13977 && flag_unsafe_math_optimizations"
13979 [(set_attr "type" "fpspc")
13980 (set_attr "mode" "XF")])
13982 (define_insn "fyl2x_extend<mode>xf3_i387"
13983 [(set (match_operand:XF 0 "register_operand" "=f")
13984 (unspec:XF [(float_extend:XF
13985 (match_operand:MODEF 1 "register_operand" "0"))
13986 (match_operand:XF 2 "register_operand" "u")]
13988 (clobber (match_scratch:XF 3 "=2"))]
13989 "TARGET_USE_FANCY_MATH_387
13990 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
13991 || TARGET_MIX_SSE_I387)
13992 && flag_unsafe_math_optimizations"
13994 [(set_attr "type" "fpspc")
13995 (set_attr "mode" "XF")])
13997 (define_expand "logxf2"
13998 [(parallel [(set (match_operand:XF 0 "register_operand" "")
13999 (unspec:XF [(match_operand:XF 1 "register_operand" "")
14000 (match_dup 2)] UNSPEC_FYL2X))
14001 (clobber (match_scratch:XF 3 ""))])]
14002 "TARGET_USE_FANCY_MATH_387
14003 && flag_unsafe_math_optimizations"
14005 operands[2] = gen_reg_rtx (XFmode);
14006 emit_move_insn (operands[2], standard_80387_constant_rtx (4)); /* fldln2 */
14009 (define_expand "log<mode>2"
14010 [(use (match_operand:MODEF 0 "register_operand" ""))
14011 (use (match_operand:MODEF 1 "register_operand" ""))]
14012 "TARGET_USE_FANCY_MATH_387
14013 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
14014 || TARGET_MIX_SSE_I387)
14015 && flag_unsafe_math_optimizations"
14017 rtx op0 = gen_reg_rtx (XFmode);
14019 rtx op2 = gen_reg_rtx (XFmode);
14020 emit_move_insn (op2, standard_80387_constant_rtx (4)); /* fldln2 */
14022 emit_insn (gen_fyl2x_extend<mode>xf3_i387 (op0, operands[1], op2));
14023 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
14027 (define_expand "log10xf2"
14028 [(parallel [(set (match_operand:XF 0 "register_operand" "")
14029 (unspec:XF [(match_operand:XF 1 "register_operand" "")
14030 (match_dup 2)] UNSPEC_FYL2X))
14031 (clobber (match_scratch:XF 3 ""))])]
14032 "TARGET_USE_FANCY_MATH_387
14033 && flag_unsafe_math_optimizations"
14035 operands[2] = gen_reg_rtx (XFmode);
14036 emit_move_insn (operands[2], standard_80387_constant_rtx (3)); /* fldlg2 */
14039 (define_expand "log10<mode>2"
14040 [(use (match_operand:MODEF 0 "register_operand" ""))
14041 (use (match_operand:MODEF 1 "register_operand" ""))]
14042 "TARGET_USE_FANCY_MATH_387
14043 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
14044 || TARGET_MIX_SSE_I387)
14045 && flag_unsafe_math_optimizations"
14047 rtx op0 = gen_reg_rtx (XFmode);
14049 rtx op2 = gen_reg_rtx (XFmode);
14050 emit_move_insn (op2, standard_80387_constant_rtx (3)); /* fldlg2 */
14052 emit_insn (gen_fyl2x_extend<mode>xf3_i387 (op0, operands[1], op2));
14053 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
14057 (define_expand "log2xf2"
14058 [(parallel [(set (match_operand:XF 0 "register_operand" "")
14059 (unspec:XF [(match_operand:XF 1 "register_operand" "")
14060 (match_dup 2)] UNSPEC_FYL2X))
14061 (clobber (match_scratch:XF 3 ""))])]
14062 "TARGET_USE_FANCY_MATH_387
14063 && flag_unsafe_math_optimizations"
14065 operands[2] = gen_reg_rtx (XFmode);
14066 emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */
14069 (define_expand "log2<mode>2"
14070 [(use (match_operand:MODEF 0 "register_operand" ""))
14071 (use (match_operand:MODEF 1 "register_operand" ""))]
14072 "TARGET_USE_FANCY_MATH_387
14073 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
14074 || TARGET_MIX_SSE_I387)
14075 && flag_unsafe_math_optimizations"
14077 rtx op0 = gen_reg_rtx (XFmode);
14079 rtx op2 = gen_reg_rtx (XFmode);
14080 emit_move_insn (op2, CONST1_RTX (XFmode)); /* fld1 */
14082 emit_insn (gen_fyl2x_extend<mode>xf3_i387 (op0, operands[1], op2));
14083 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
14087 (define_insn "fyl2xp1xf3_i387"
14088 [(set (match_operand:XF 0 "register_operand" "=f")
14089 (unspec:XF [(match_operand:XF 1 "register_operand" "0")
14090 (match_operand:XF 2 "register_operand" "u")]
14092 (clobber (match_scratch:XF 3 "=2"))]
14093 "TARGET_USE_FANCY_MATH_387
14094 && flag_unsafe_math_optimizations"
14096 [(set_attr "type" "fpspc")
14097 (set_attr "mode" "XF")])
14099 (define_insn "fyl2xp1_extend<mode>xf3_i387"
14100 [(set (match_operand:XF 0 "register_operand" "=f")
14101 (unspec:XF [(float_extend:XF
14102 (match_operand:MODEF 1 "register_operand" "0"))
14103 (match_operand:XF 2 "register_operand" "u")]
14105 (clobber (match_scratch:XF 3 "=2"))]
14106 "TARGET_USE_FANCY_MATH_387
14107 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
14108 || TARGET_MIX_SSE_I387)
14109 && flag_unsafe_math_optimizations"
14111 [(set_attr "type" "fpspc")
14112 (set_attr "mode" "XF")])
14114 (define_expand "log1pxf2"
14115 [(use (match_operand:XF 0 "register_operand" ""))
14116 (use (match_operand:XF 1 "register_operand" ""))]
14117 "TARGET_USE_FANCY_MATH_387
14118 && flag_unsafe_math_optimizations"
14120 if (optimize_insn_for_size_p ())
14123 ix86_emit_i387_log1p (operands[0], operands[1]);
14127 (define_expand "log1p<mode>2"
14128 [(use (match_operand:MODEF 0 "register_operand" ""))
14129 (use (match_operand:MODEF 1 "register_operand" ""))]
14130 "TARGET_USE_FANCY_MATH_387
14131 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
14132 || TARGET_MIX_SSE_I387)
14133 && flag_unsafe_math_optimizations"
14137 if (optimize_insn_for_size_p ())
14140 op0 = gen_reg_rtx (XFmode);
14142 operands[1] = gen_rtx_FLOAT_EXTEND (XFmode, operands[1]);
14144 ix86_emit_i387_log1p (op0, operands[1]);
14145 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
14149 (define_insn "fxtractxf3_i387"
14150 [(set (match_operand:XF 0 "register_operand" "=f")
14151 (unspec:XF [(match_operand:XF 2 "register_operand" "0")]
14152 UNSPEC_XTRACT_FRACT))
14153 (set (match_operand:XF 1 "register_operand" "=u")
14154 (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_EXP))]
14155 "TARGET_USE_FANCY_MATH_387
14156 && flag_unsafe_math_optimizations"
14158 [(set_attr "type" "fpspc")
14159 (set_attr "mode" "XF")])
14161 (define_insn "fxtract_extend<mode>xf3_i387"
14162 [(set (match_operand:XF 0 "register_operand" "=f")
14163 (unspec:XF [(float_extend:XF
14164 (match_operand:MODEF 2 "register_operand" "0"))]
14165 UNSPEC_XTRACT_FRACT))
14166 (set (match_operand:XF 1 "register_operand" "=u")
14167 (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_XTRACT_EXP))]
14168 "TARGET_USE_FANCY_MATH_387
14169 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
14170 || TARGET_MIX_SSE_I387)
14171 && flag_unsafe_math_optimizations"
14173 [(set_attr "type" "fpspc")
14174 (set_attr "mode" "XF")])
14176 (define_expand "logbxf2"
14177 [(parallel [(set (match_dup 2)
14178 (unspec:XF [(match_operand:XF 1 "register_operand" "")]
14179 UNSPEC_XTRACT_FRACT))
14180 (set (match_operand:XF 0 "register_operand" "")
14181 (unspec:XF [(match_dup 1)] UNSPEC_XTRACT_EXP))])]
14182 "TARGET_USE_FANCY_MATH_387
14183 && flag_unsafe_math_optimizations"
14184 "operands[2] = gen_reg_rtx (XFmode);")
14186 (define_expand "logb<mode>2"
14187 [(use (match_operand:MODEF 0 "register_operand" ""))
14188 (use (match_operand:MODEF 1 "register_operand" ""))]
14189 "TARGET_USE_FANCY_MATH_387
14190 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
14191 || TARGET_MIX_SSE_I387)
14192 && flag_unsafe_math_optimizations"
14194 rtx op0 = gen_reg_rtx (XFmode);
14195 rtx op1 = gen_reg_rtx (XFmode);
14197 emit_insn (gen_fxtract_extend<mode>xf3_i387 (op0, op1, operands[1]));
14198 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op1));
14202 (define_expand "ilogbxf2"
14203 [(use (match_operand:SI 0 "register_operand" ""))
14204 (use (match_operand:XF 1 "register_operand" ""))]
14205 "TARGET_USE_FANCY_MATH_387
14206 && flag_unsafe_math_optimizations"
14210 if (optimize_insn_for_size_p ())
14213 op0 = gen_reg_rtx (XFmode);
14214 op1 = gen_reg_rtx (XFmode);
14216 emit_insn (gen_fxtractxf3_i387 (op0, op1, operands[1]));
14217 emit_insn (gen_fix_truncxfsi2 (operands[0], op1));
14221 (define_expand "ilogb<mode>2"
14222 [(use (match_operand:SI 0 "register_operand" ""))
14223 (use (match_operand:MODEF 1 "register_operand" ""))]
14224 "TARGET_USE_FANCY_MATH_387
14225 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
14226 || TARGET_MIX_SSE_I387)
14227 && flag_unsafe_math_optimizations"
14231 if (optimize_insn_for_size_p ())
14234 op0 = gen_reg_rtx (XFmode);
14235 op1 = gen_reg_rtx (XFmode);
14237 emit_insn (gen_fxtract_extend<mode>xf3_i387 (op0, op1, operands[1]));
14238 emit_insn (gen_fix_truncxfsi2 (operands[0], op1));
14242 (define_insn "*f2xm1xf2_i387"
14243 [(set (match_operand:XF 0 "register_operand" "=f")
14244 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
14246 "TARGET_USE_FANCY_MATH_387
14247 && flag_unsafe_math_optimizations"
14249 [(set_attr "type" "fpspc")
14250 (set_attr "mode" "XF")])
14252 (define_insn "*fscalexf4_i387"
14253 [(set (match_operand:XF 0 "register_operand" "=f")
14254 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
14255 (match_operand:XF 3 "register_operand" "1")]
14256 UNSPEC_FSCALE_FRACT))
14257 (set (match_operand:XF 1 "register_operand" "=u")
14258 (unspec:XF [(match_dup 2) (match_dup 3)]
14259 UNSPEC_FSCALE_EXP))]
14260 "TARGET_USE_FANCY_MATH_387
14261 && flag_unsafe_math_optimizations"
14263 [(set_attr "type" "fpspc")
14264 (set_attr "mode" "XF")])
14266 (define_expand "expNcorexf3"
14267 [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand" "")
14268 (match_operand:XF 2 "register_operand" "")))
14269 (set (match_dup 4) (unspec:XF [(match_dup 3)] UNSPEC_FRNDINT))
14270 (set (match_dup 5) (minus:XF (match_dup 3) (match_dup 4)))
14271 (set (match_dup 6) (unspec:XF [(match_dup 5)] UNSPEC_F2XM1))
14272 (set (match_dup 8) (plus:XF (match_dup 6) (match_dup 7)))
14273 (parallel [(set (match_operand:XF 0 "register_operand" "")
14274 (unspec:XF [(match_dup 8) (match_dup 4)]
14275 UNSPEC_FSCALE_FRACT))
14277 (unspec:XF [(match_dup 8) (match_dup 4)]
14278 UNSPEC_FSCALE_EXP))])]
14279 "TARGET_USE_FANCY_MATH_387
14280 && flag_unsafe_math_optimizations"
14284 if (optimize_insn_for_size_p ())
14287 for (i = 3; i < 10; i++)
14288 operands[i] = gen_reg_rtx (XFmode);
14290 emit_move_insn (operands[7], CONST1_RTX (XFmode)); /* fld1 */
14293 (define_expand "expxf2"
14294 [(use (match_operand:XF 0 "register_operand" ""))
14295 (use (match_operand:XF 1 "register_operand" ""))]
14296 "TARGET_USE_FANCY_MATH_387
14297 && flag_unsafe_math_optimizations"
14301 if (optimize_insn_for_size_p ())
14304 op2 = gen_reg_rtx (XFmode);
14305 emit_move_insn (op2, standard_80387_constant_rtx (5)); /* fldl2e */
14307 emit_insn (gen_expNcorexf3 (operands[0], operands[1], op2));
14311 (define_expand "exp<mode>2"
14312 [(use (match_operand:MODEF 0 "register_operand" ""))
14313 (use (match_operand:MODEF 1 "general_operand" ""))]
14314 "TARGET_USE_FANCY_MATH_387
14315 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
14316 || TARGET_MIX_SSE_I387)
14317 && flag_unsafe_math_optimizations"
14321 if (optimize_insn_for_size_p ())
14324 op0 = gen_reg_rtx (XFmode);
14325 op1 = gen_reg_rtx (XFmode);
14327 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
14328 emit_insn (gen_expxf2 (op0, op1));
14329 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
14333 (define_expand "exp10xf2"
14334 [(use (match_operand:XF 0 "register_operand" ""))
14335 (use (match_operand:XF 1 "register_operand" ""))]
14336 "TARGET_USE_FANCY_MATH_387
14337 && flag_unsafe_math_optimizations"
14341 if (optimize_insn_for_size_p ())
14344 op2 = gen_reg_rtx (XFmode);
14345 emit_move_insn (op2, standard_80387_constant_rtx (6)); /* fldl2t */
14347 emit_insn (gen_expNcorexf3 (operands[0], operands[1], op2));
14351 (define_expand "exp10<mode>2"
14352 [(use (match_operand:MODEF 0 "register_operand" ""))
14353 (use (match_operand:MODEF 1 "general_operand" ""))]
14354 "TARGET_USE_FANCY_MATH_387
14355 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
14356 || TARGET_MIX_SSE_I387)
14357 && flag_unsafe_math_optimizations"
14361 if (optimize_insn_for_size_p ())
14364 op0 = gen_reg_rtx (XFmode);
14365 op1 = gen_reg_rtx (XFmode);
14367 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
14368 emit_insn (gen_exp10xf2 (op0, op1));
14369 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
14373 (define_expand "exp2xf2"
14374 [(use (match_operand:XF 0 "register_operand" ""))
14375 (use (match_operand:XF 1 "register_operand" ""))]
14376 "TARGET_USE_FANCY_MATH_387
14377 && flag_unsafe_math_optimizations"
14381 if (optimize_insn_for_size_p ())
14384 op2 = gen_reg_rtx (XFmode);
14385 emit_move_insn (op2, CONST1_RTX (XFmode)); /* fld1 */
14387 emit_insn (gen_expNcorexf3 (operands[0], operands[1], op2));
14391 (define_expand "exp2<mode>2"
14392 [(use (match_operand:MODEF 0 "register_operand" ""))
14393 (use (match_operand:MODEF 1 "general_operand" ""))]
14394 "TARGET_USE_FANCY_MATH_387
14395 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
14396 || TARGET_MIX_SSE_I387)
14397 && flag_unsafe_math_optimizations"
14401 if (optimize_insn_for_size_p ())
14404 op0 = gen_reg_rtx (XFmode);
14405 op1 = gen_reg_rtx (XFmode);
14407 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
14408 emit_insn (gen_exp2xf2 (op0, op1));
14409 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
14413 (define_expand "expm1xf2"
14414 [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand" "")
14416 (set (match_dup 4) (unspec:XF [(match_dup 3)] UNSPEC_FRNDINT))
14417 (set (match_dup 5) (minus:XF (match_dup 3) (match_dup 4)))
14418 (set (match_dup 9) (float_extend:XF (match_dup 13)))
14419 (set (match_dup 6) (unspec:XF [(match_dup 5)] UNSPEC_F2XM1))
14420 (parallel [(set (match_dup 7)
14421 (unspec:XF [(match_dup 6) (match_dup 4)]
14422 UNSPEC_FSCALE_FRACT))
14424 (unspec:XF [(match_dup 6) (match_dup 4)]
14425 UNSPEC_FSCALE_EXP))])
14426 (parallel [(set (match_dup 10)
14427 (unspec:XF [(match_dup 9) (match_dup 8)]
14428 UNSPEC_FSCALE_FRACT))
14429 (set (match_dup 11)
14430 (unspec:XF [(match_dup 9) (match_dup 8)]
14431 UNSPEC_FSCALE_EXP))])
14432 (set (match_dup 12) (minus:XF (match_dup 10)
14433 (float_extend:XF (match_dup 13))))
14434 (set (match_operand:XF 0 "register_operand" "")
14435 (plus:XF (match_dup 12) (match_dup 7)))]
14436 "TARGET_USE_FANCY_MATH_387
14437 && flag_unsafe_math_optimizations"
14441 if (optimize_insn_for_size_p ())
14444 for (i = 2; i < 13; i++)
14445 operands[i] = gen_reg_rtx (XFmode);
14448 = validize_mem (force_const_mem (SFmode, CONST1_RTX (SFmode))); /* fld1 */
14450 emit_move_insn (operands[2], standard_80387_constant_rtx (5)); /* fldl2e */
14453 (define_expand "expm1<mode>2"
14454 [(use (match_operand:MODEF 0 "register_operand" ""))
14455 (use (match_operand:MODEF 1 "general_operand" ""))]
14456 "TARGET_USE_FANCY_MATH_387
14457 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
14458 || TARGET_MIX_SSE_I387)
14459 && flag_unsafe_math_optimizations"
14463 if (optimize_insn_for_size_p ())
14466 op0 = gen_reg_rtx (XFmode);
14467 op1 = gen_reg_rtx (XFmode);
14469 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
14470 emit_insn (gen_expm1xf2 (op0, op1));
14471 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
14475 (define_expand "ldexpxf3"
14476 [(set (match_dup 3)
14477 (float:XF (match_operand:SI 2 "register_operand" "")))
14478 (parallel [(set (match_operand:XF 0 " register_operand" "")
14479 (unspec:XF [(match_operand:XF 1 "register_operand" "")
14481 UNSPEC_FSCALE_FRACT))
14483 (unspec:XF [(match_dup 1) (match_dup 3)]
14484 UNSPEC_FSCALE_EXP))])]
14485 "TARGET_USE_FANCY_MATH_387
14486 && flag_unsafe_math_optimizations"
14488 if (optimize_insn_for_size_p ())
14491 operands[3] = gen_reg_rtx (XFmode);
14492 operands[4] = gen_reg_rtx (XFmode);
14495 (define_expand "ldexp<mode>3"
14496 [(use (match_operand:MODEF 0 "register_operand" ""))
14497 (use (match_operand:MODEF 1 "general_operand" ""))
14498 (use (match_operand:SI 2 "register_operand" ""))]
14499 "TARGET_USE_FANCY_MATH_387
14500 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
14501 || TARGET_MIX_SSE_I387)
14502 && flag_unsafe_math_optimizations"
14506 if (optimize_insn_for_size_p ())
14509 op0 = gen_reg_rtx (XFmode);
14510 op1 = gen_reg_rtx (XFmode);
14512 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
14513 emit_insn (gen_ldexpxf3 (op0, op1, operands[2]));
14514 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
14518 (define_expand "scalbxf3"
14519 [(parallel [(set (match_operand:XF 0 " register_operand" "")
14520 (unspec:XF [(match_operand:XF 1 "register_operand" "")
14521 (match_operand:XF 2 "register_operand" "")]
14522 UNSPEC_FSCALE_FRACT))
14524 (unspec:XF [(match_dup 1) (match_dup 2)]
14525 UNSPEC_FSCALE_EXP))])]
14526 "TARGET_USE_FANCY_MATH_387
14527 && flag_unsafe_math_optimizations"
14529 if (optimize_insn_for_size_p ())
14532 operands[3] = gen_reg_rtx (XFmode);
14535 (define_expand "scalb<mode>3"
14536 [(use (match_operand:MODEF 0 "register_operand" ""))
14537 (use (match_operand:MODEF 1 "general_operand" ""))
14538 (use (match_operand:MODEF 2 "general_operand" ""))]
14539 "TARGET_USE_FANCY_MATH_387
14540 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
14541 || TARGET_MIX_SSE_I387)
14542 && flag_unsafe_math_optimizations"
14546 if (optimize_insn_for_size_p ())
14549 op0 = gen_reg_rtx (XFmode);
14550 op1 = gen_reg_rtx (XFmode);
14551 op2 = gen_reg_rtx (XFmode);
14553 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
14554 emit_insn (gen_extend<mode>xf2 (op2, operands[2]));
14555 emit_insn (gen_scalbxf3 (op0, op1, op2));
14556 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
14560 (define_expand "significandxf2"
14561 [(parallel [(set (match_operand:XF 0 "register_operand" "")
14562 (unspec:XF [(match_operand:XF 1 "register_operand" "")]
14563 UNSPEC_XTRACT_FRACT))
14565 (unspec:XF [(match_dup 1)] UNSPEC_XTRACT_EXP))])]
14566 "TARGET_USE_FANCY_MATH_387
14567 && flag_unsafe_math_optimizations"
14568 "operands[2] = gen_reg_rtx (XFmode);")
14570 (define_expand "significand<mode>2"
14571 [(use (match_operand:MODEF 0 "register_operand" ""))
14572 (use (match_operand:MODEF 1 "register_operand" ""))]
14573 "TARGET_USE_FANCY_MATH_387
14574 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
14575 || TARGET_MIX_SSE_I387)
14576 && flag_unsafe_math_optimizations"
14578 rtx op0 = gen_reg_rtx (XFmode);
14579 rtx op1 = gen_reg_rtx (XFmode);
14581 emit_insn (gen_fxtract_extend<mode>xf3_i387 (op0, op1, operands[1]));
14582 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
14587 (define_insn "sse4_1_round<mode>2"
14588 [(set (match_operand:MODEF 0 "register_operand" "=x")
14589 (unspec:MODEF [(match_operand:MODEF 1 "register_operand" "x")
14590 (match_operand:SI 2 "const_0_to_15_operand" "n")]
14593 "%vround<ssemodesuffix>\t{%2, %1, %d0|%d0, %1, %2}"
14594 [(set_attr "type" "ssecvt")
14595 (set_attr "prefix_extra" "1")
14596 (set_attr "prefix" "maybe_vex")
14597 (set_attr "mode" "<MODE>")])
14599 (define_insn "rintxf2"
14600 [(set (match_operand:XF 0 "register_operand" "=f")
14601 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
14603 "TARGET_USE_FANCY_MATH_387
14604 && flag_unsafe_math_optimizations"
14606 [(set_attr "type" "fpspc")
14607 (set_attr "mode" "XF")])
14609 (define_expand "rint<mode>2"
14610 [(use (match_operand:MODEF 0 "register_operand" ""))
14611 (use (match_operand:MODEF 1 "register_operand" ""))]
14612 "(TARGET_USE_FANCY_MATH_387
14613 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
14614 || TARGET_MIX_SSE_I387)
14615 && flag_unsafe_math_optimizations)
14616 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
14617 && !flag_trapping_math)"
14619 if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
14620 && !flag_trapping_math)
14623 emit_insn (gen_sse4_1_round<mode>2
14624 (operands[0], operands[1], GEN_INT (ROUND_MXCSR)));
14625 else if (optimize_insn_for_size_p ())
14628 ix86_expand_rint (operands[0], operands[1]);
14632 rtx op0 = gen_reg_rtx (XFmode);
14633 rtx op1 = gen_reg_rtx (XFmode);
14635 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
14636 emit_insn (gen_rintxf2 (op0, op1));
14638 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
14643 (define_expand "round<mode>2"
14644 [(match_operand:X87MODEF 0 "register_operand" "")
14645 (match_operand:X87MODEF 1 "nonimmediate_operand" "")]
14646 "(TARGET_USE_FANCY_MATH_387
14647 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
14648 || TARGET_MIX_SSE_I387)
14649 && flag_unsafe_math_optimizations)
14650 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
14651 && !flag_trapping_math && !flag_rounding_math)"
14653 if (optimize_insn_for_size_p ())
14656 if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
14657 && !flag_trapping_math && !flag_rounding_math)
14661 operands[1] = force_reg (<MODE>mode, operands[1]);
14662 ix86_expand_round_sse4 (operands[0], operands[1]);
14664 else if (TARGET_64BIT || (<MODE>mode != DFmode))
14665 ix86_expand_round (operands[0], operands[1]);
14667 ix86_expand_rounddf_32 (operands[0], operands[1]);
14671 operands[1] = force_reg (<MODE>mode, operands[1]);
14672 ix86_emit_i387_round (operands[0], operands[1]);
14677 (define_insn_and_split "*fistdi2_1"
14678 [(set (match_operand:DI 0 "nonimmediate_operand" "")
14679 (unspec:DI [(match_operand:XF 1 "register_operand" "")]
14681 "TARGET_USE_FANCY_MATH_387
14682 && can_create_pseudo_p ()"
14687 if (memory_operand (operands[0], VOIDmode))
14688 emit_insn (gen_fistdi2 (operands[0], operands[1]));
14691 operands[2] = assign_386_stack_local (DImode, SLOT_TEMP);
14692 emit_insn (gen_fistdi2_with_temp (operands[0], operands[1],
14697 [(set_attr "type" "fpspc")
14698 (set_attr "mode" "DI")])
14700 (define_insn "fistdi2"
14701 [(set (match_operand:DI 0 "memory_operand" "=m")
14702 (unspec:DI [(match_operand:XF 1 "register_operand" "f")]
14704 (clobber (match_scratch:XF 2 "=&1f"))]
14705 "TARGET_USE_FANCY_MATH_387"
14706 "* return output_fix_trunc (insn, operands, false);"
14707 [(set_attr "type" "fpspc")
14708 (set_attr "mode" "DI")])
14710 (define_insn "fistdi2_with_temp"
14711 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
14712 (unspec:DI [(match_operand:XF 1 "register_operand" "f,f")]
14714 (clobber (match_operand:DI 2 "memory_operand" "=X,m"))
14715 (clobber (match_scratch:XF 3 "=&1f,&1f"))]
14716 "TARGET_USE_FANCY_MATH_387"
14718 [(set_attr "type" "fpspc")
14719 (set_attr "mode" "DI")])
14722 [(set (match_operand:DI 0 "register_operand" "")
14723 (unspec:DI [(match_operand:XF 1 "register_operand" "")]
14725 (clobber (match_operand:DI 2 "memory_operand" ""))
14726 (clobber (match_scratch 3 ""))]
14728 [(parallel [(set (match_dup 2) (unspec:DI [(match_dup 1)] UNSPEC_FIST))
14729 (clobber (match_dup 3))])
14730 (set (match_dup 0) (match_dup 2))])
14733 [(set (match_operand:DI 0 "memory_operand" "")
14734 (unspec:DI [(match_operand:XF 1 "register_operand" "")]
14736 (clobber (match_operand:DI 2 "memory_operand" ""))
14737 (clobber (match_scratch 3 ""))]
14739 [(parallel [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_FIST))
14740 (clobber (match_dup 3))])])
14742 (define_insn_and_split "*fist<mode>2_1"
14743 [(set (match_operand:SWI24 0 "register_operand" "")
14744 (unspec:SWI24 [(match_operand:XF 1 "register_operand" "")]
14746 "TARGET_USE_FANCY_MATH_387
14747 && can_create_pseudo_p ()"
14752 operands[2] = assign_386_stack_local (<MODE>mode, SLOT_TEMP);
14753 emit_insn (gen_fist<mode>2_with_temp (operands[0], operands[1],
14757 [(set_attr "type" "fpspc")
14758 (set_attr "mode" "<MODE>")])
14760 (define_insn "fist<mode>2"
14761 [(set (match_operand:SWI24 0 "memory_operand" "=m")
14762 (unspec:SWI24 [(match_operand:XF 1 "register_operand" "f")]
14764 "TARGET_USE_FANCY_MATH_387"
14765 "* return output_fix_trunc (insn, operands, false);"
14766 [(set_attr "type" "fpspc")
14767 (set_attr "mode" "<MODE>")])
14769 (define_insn "fist<mode>2_with_temp"
14770 [(set (match_operand:SWI24 0 "register_operand" "=r")
14771 (unspec:SWI24 [(match_operand:XF 1 "register_operand" "f")]
14773 (clobber (match_operand:SWI24 2 "memory_operand" "=m"))]
14774 "TARGET_USE_FANCY_MATH_387"
14776 [(set_attr "type" "fpspc")
14777 (set_attr "mode" "<MODE>")])
14780 [(set (match_operand:SWI24 0 "register_operand" "")
14781 (unspec:SWI24 [(match_operand:XF 1 "register_operand" "")]
14783 (clobber (match_operand:SWI24 2 "memory_operand" ""))]
14785 [(set (match_dup 2) (unspec:SWI24 [(match_dup 1)] UNSPEC_FIST))
14786 (set (match_dup 0) (match_dup 2))])
14789 [(set (match_operand:SWI24 0 "memory_operand" "")
14790 (unspec:SWI24 [(match_operand:XF 1 "register_operand" "")]
14792 (clobber (match_operand:SWI24 2 "memory_operand" ""))]
14794 [(set (match_dup 0) (unspec:SWI24 [(match_dup 1)] UNSPEC_FIST))])
14796 (define_expand "lrintxf<mode>2"
14797 [(set (match_operand:SWI248x 0 "nonimmediate_operand" "")
14798 (unspec:SWI248x [(match_operand:XF 1 "register_operand" "")]
14800 "TARGET_USE_FANCY_MATH_387")
14802 (define_expand "lrint<MODEF:mode><SWI48x:mode>2"
14803 [(set (match_operand:SWI48x 0 "nonimmediate_operand" "")
14804 (unspec:SWI48x [(match_operand:MODEF 1 "register_operand" "")]
14805 UNSPEC_FIX_NOTRUNC))]
14806 "SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
14807 && ((<SWI48x:MODE>mode != DImode) || TARGET_64BIT)")
14809 (define_expand "lround<X87MODEF:mode><SWI248x:mode>2"
14810 [(match_operand:SWI248x 0 "nonimmediate_operand" "")
14811 (match_operand:X87MODEF 1 "register_operand" "")]
14812 "(TARGET_USE_FANCY_MATH_387
14813 && (!(SSE_FLOAT_MODE_P (<X87MODEF:MODE>mode) && TARGET_SSE_MATH)
14814 || TARGET_MIX_SSE_I387)
14815 && flag_unsafe_math_optimizations)
14816 || (SSE_FLOAT_MODE_P (<X87MODEF:MODE>mode) && TARGET_SSE_MATH
14817 && <SWI248x:MODE>mode != HImode
14818 && ((<SWI248x:MODE>mode != DImode) || TARGET_64BIT)
14819 && !flag_trapping_math && !flag_rounding_math)"
14821 if (optimize_insn_for_size_p ())
14824 if (SSE_FLOAT_MODE_P (<X87MODEF:MODE>mode) && TARGET_SSE_MATH
14825 && <SWI248x:MODE>mode != HImode
14826 && ((<SWI248x:MODE>mode != DImode) || TARGET_64BIT)
14827 && !flag_trapping_math && !flag_rounding_math)
14828 ix86_expand_lround (operands[0], operands[1]);
14830 ix86_emit_i387_round (operands[0], operands[1]);
14834 ;; Rounding mode control word calculation could clobber FLAGS_REG.
14835 (define_insn_and_split "frndintxf2_floor"
14836 [(set (match_operand:XF 0 "register_operand" "")
14837 (unspec:XF [(match_operand:XF 1 "register_operand" "")]
14838 UNSPEC_FRNDINT_FLOOR))
14839 (clobber (reg:CC FLAGS_REG))]
14840 "TARGET_USE_FANCY_MATH_387
14841 && flag_unsafe_math_optimizations
14842 && can_create_pseudo_p ()"
14847 ix86_optimize_mode_switching[I387_FLOOR] = 1;
14849 operands[2] = assign_386_stack_local (HImode, SLOT_CW_STORED);
14850 operands[3] = assign_386_stack_local (HImode, SLOT_CW_FLOOR);
14852 emit_insn (gen_frndintxf2_floor_i387 (operands[0], operands[1],
14853 operands[2], operands[3]));
14856 [(set_attr "type" "frndint")
14857 (set_attr "i387_cw" "floor")
14858 (set_attr "mode" "XF")])
14860 (define_insn "frndintxf2_floor_i387"
14861 [(set (match_operand:XF 0 "register_operand" "=f")
14862 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
14863 UNSPEC_FRNDINT_FLOOR))
14864 (use (match_operand:HI 2 "memory_operand" "m"))
14865 (use (match_operand:HI 3 "memory_operand" "m"))]
14866 "TARGET_USE_FANCY_MATH_387
14867 && flag_unsafe_math_optimizations"
14868 "fldcw\t%3\n\tfrndint\n\tfldcw\t%2"
14869 [(set_attr "type" "frndint")
14870 (set_attr "i387_cw" "floor")
14871 (set_attr "mode" "XF")])
14873 (define_expand "floorxf2"
14874 [(use (match_operand:XF 0 "register_operand" ""))
14875 (use (match_operand:XF 1 "register_operand" ""))]
14876 "TARGET_USE_FANCY_MATH_387
14877 && flag_unsafe_math_optimizations"
14879 if (optimize_insn_for_size_p ())
14881 emit_insn (gen_frndintxf2_floor (operands[0], operands[1]));
14885 (define_expand "floor<mode>2"
14886 [(use (match_operand:MODEF 0 "register_operand" ""))
14887 (use (match_operand:MODEF 1 "register_operand" ""))]
14888 "(TARGET_USE_FANCY_MATH_387
14889 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
14890 || TARGET_MIX_SSE_I387)
14891 && flag_unsafe_math_optimizations)
14892 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
14893 && !flag_trapping_math)"
14895 if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
14896 && !flag_trapping_math)
14899 emit_insn (gen_sse4_1_round<mode>2
14900 (operands[0], operands[1], GEN_INT (ROUND_FLOOR)));
14901 else if (optimize_insn_for_size_p ())
14903 else if (TARGET_64BIT || (<MODE>mode != DFmode))
14904 ix86_expand_floorceil (operands[0], operands[1], true);
14906 ix86_expand_floorceildf_32 (operands[0], operands[1], true);
14912 if (optimize_insn_for_size_p ())
14915 op0 = gen_reg_rtx (XFmode);
14916 op1 = gen_reg_rtx (XFmode);
14917 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
14918 emit_insn (gen_frndintxf2_floor (op0, op1));
14920 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
14925 (define_insn_and_split "*fist<mode>2_floor_1"
14926 [(set (match_operand:SWI248x 0 "nonimmediate_operand" "")
14927 (unspec:SWI248x [(match_operand:XF 1 "register_operand" "")]
14928 UNSPEC_FIST_FLOOR))
14929 (clobber (reg:CC FLAGS_REG))]
14930 "TARGET_USE_FANCY_MATH_387
14931 && flag_unsafe_math_optimizations
14932 && can_create_pseudo_p ()"
14937 ix86_optimize_mode_switching[I387_FLOOR] = 1;
14939 operands[2] = assign_386_stack_local (HImode, SLOT_CW_STORED);
14940 operands[3] = assign_386_stack_local (HImode, SLOT_CW_FLOOR);
14941 if (memory_operand (operands[0], VOIDmode))
14942 emit_insn (gen_fist<mode>2_floor (operands[0], operands[1],
14943 operands[2], operands[3]));
14946 operands[4] = assign_386_stack_local (<MODE>mode, SLOT_TEMP);
14947 emit_insn (gen_fist<mode>2_floor_with_temp (operands[0], operands[1],
14948 operands[2], operands[3],
14953 [(set_attr "type" "fistp")
14954 (set_attr "i387_cw" "floor")
14955 (set_attr "mode" "<MODE>")])
14957 (define_insn "fistdi2_floor"
14958 [(set (match_operand:DI 0 "memory_operand" "=m")
14959 (unspec:DI [(match_operand:XF 1 "register_operand" "f")]
14960 UNSPEC_FIST_FLOOR))
14961 (use (match_operand:HI 2 "memory_operand" "m"))
14962 (use (match_operand:HI 3 "memory_operand" "m"))
14963 (clobber (match_scratch:XF 4 "=&1f"))]
14964 "TARGET_USE_FANCY_MATH_387
14965 && flag_unsafe_math_optimizations"
14966 "* return output_fix_trunc (insn, operands, false);"
14967 [(set_attr "type" "fistp")
14968 (set_attr "i387_cw" "floor")
14969 (set_attr "mode" "DI")])
14971 (define_insn "fistdi2_floor_with_temp"
14972 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
14973 (unspec:DI [(match_operand:XF 1 "register_operand" "f,f")]
14974 UNSPEC_FIST_FLOOR))
14975 (use (match_operand:HI 2 "memory_operand" "m,m"))
14976 (use (match_operand:HI 3 "memory_operand" "m,m"))
14977 (clobber (match_operand:DI 4 "memory_operand" "=X,m"))
14978 (clobber (match_scratch:XF 5 "=&1f,&1f"))]
14979 "TARGET_USE_FANCY_MATH_387
14980 && flag_unsafe_math_optimizations"
14982 [(set_attr "type" "fistp")
14983 (set_attr "i387_cw" "floor")
14984 (set_attr "mode" "DI")])
14987 [(set (match_operand:DI 0 "register_operand" "")
14988 (unspec:DI [(match_operand:XF 1 "register_operand" "")]
14989 UNSPEC_FIST_FLOOR))
14990 (use (match_operand:HI 2 "memory_operand" ""))
14991 (use (match_operand:HI 3 "memory_operand" ""))
14992 (clobber (match_operand:DI 4 "memory_operand" ""))
14993 (clobber (match_scratch 5 ""))]
14995 [(parallel [(set (match_dup 4)
14996 (unspec:DI [(match_dup 1)] UNSPEC_FIST_FLOOR))
14997 (use (match_dup 2))
14998 (use (match_dup 3))
14999 (clobber (match_dup 5))])
15000 (set (match_dup 0) (match_dup 4))])
15003 [(set (match_operand:DI 0 "memory_operand" "")
15004 (unspec:DI [(match_operand:XF 1 "register_operand" "")]
15005 UNSPEC_FIST_FLOOR))
15006 (use (match_operand:HI 2 "memory_operand" ""))
15007 (use (match_operand:HI 3 "memory_operand" ""))
15008 (clobber (match_operand:DI 4 "memory_operand" ""))
15009 (clobber (match_scratch 5 ""))]
15011 [(parallel [(set (match_dup 0)
15012 (unspec:DI [(match_dup 1)] UNSPEC_FIST_FLOOR))
15013 (use (match_dup 2))
15014 (use (match_dup 3))
15015 (clobber (match_dup 5))])])
15017 (define_insn "fist<mode>2_floor"
15018 [(set (match_operand:SWI24 0 "memory_operand" "=m")
15019 (unspec:SWI24 [(match_operand:XF 1 "register_operand" "f")]
15020 UNSPEC_FIST_FLOOR))
15021 (use (match_operand:HI 2 "memory_operand" "m"))
15022 (use (match_operand:HI 3 "memory_operand" "m"))]
15023 "TARGET_USE_FANCY_MATH_387
15024 && flag_unsafe_math_optimizations"
15025 "* return output_fix_trunc (insn, operands, false);"
15026 [(set_attr "type" "fistp")
15027 (set_attr "i387_cw" "floor")
15028 (set_attr "mode" "<MODE>")])
15030 (define_insn "fist<mode>2_floor_with_temp"
15031 [(set (match_operand:SWI24 0 "nonimmediate_operand" "=m,?r")
15032 (unspec:SWI24 [(match_operand:XF 1 "register_operand" "f,f")]
15033 UNSPEC_FIST_FLOOR))
15034 (use (match_operand:HI 2 "memory_operand" "m,m"))
15035 (use (match_operand:HI 3 "memory_operand" "m,m"))
15036 (clobber (match_operand:SWI24 4 "memory_operand" "=X,m"))]
15037 "TARGET_USE_FANCY_MATH_387
15038 && flag_unsafe_math_optimizations"
15040 [(set_attr "type" "fistp")
15041 (set_attr "i387_cw" "floor")
15042 (set_attr "mode" "<MODE>")])
15045 [(set (match_operand:SWI24 0 "register_operand" "")
15046 (unspec:SWI24 [(match_operand:XF 1 "register_operand" "")]
15047 UNSPEC_FIST_FLOOR))
15048 (use (match_operand:HI 2 "memory_operand" ""))
15049 (use (match_operand:HI 3 "memory_operand" ""))
15050 (clobber (match_operand:SWI24 4 "memory_operand" ""))]
15052 [(parallel [(set (match_dup 4)
15053 (unspec:SWI24 [(match_dup 1)] UNSPEC_FIST_FLOOR))
15054 (use (match_dup 2))
15055 (use (match_dup 3))])
15056 (set (match_dup 0) (match_dup 4))])
15059 [(set (match_operand:SWI24 0 "memory_operand" "")
15060 (unspec:SWI24 [(match_operand:XF 1 "register_operand" "")]
15061 UNSPEC_FIST_FLOOR))
15062 (use (match_operand:HI 2 "memory_operand" ""))
15063 (use (match_operand:HI 3 "memory_operand" ""))
15064 (clobber (match_operand:SWI24 4 "memory_operand" ""))]
15066 [(parallel [(set (match_dup 0)
15067 (unspec:SWI24 [(match_dup 1)] UNSPEC_FIST_FLOOR))
15068 (use (match_dup 2))
15069 (use (match_dup 3))])])
15071 (define_expand "lfloorxf<mode>2"
15072 [(parallel [(set (match_operand:SWI248x 0 "nonimmediate_operand" "")
15073 (unspec:SWI248x [(match_operand:XF 1 "register_operand" "")]
15074 UNSPEC_FIST_FLOOR))
15075 (clobber (reg:CC FLAGS_REG))])]
15076 "TARGET_USE_FANCY_MATH_387
15077 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
15078 && flag_unsafe_math_optimizations")
15080 (define_expand "lfloor<MODEF:mode><SWI48:mode>2"
15081 [(match_operand:SWI48 0 "nonimmediate_operand" "")
15082 (match_operand:MODEF 1 "register_operand" "")]
15083 "SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
15084 && !flag_trapping_math"
15086 if (TARGET_64BIT && optimize_insn_for_size_p ())
15088 ix86_expand_lfloorceil (operands[0], operands[1], true);
15092 ;; Rounding mode control word calculation could clobber FLAGS_REG.
15093 (define_insn_and_split "frndintxf2_ceil"
15094 [(set (match_operand:XF 0 "register_operand" "")
15095 (unspec:XF [(match_operand:XF 1 "register_operand" "")]
15096 UNSPEC_FRNDINT_CEIL))
15097 (clobber (reg:CC FLAGS_REG))]
15098 "TARGET_USE_FANCY_MATH_387
15099 && flag_unsafe_math_optimizations
15100 && can_create_pseudo_p ()"
15105 ix86_optimize_mode_switching[I387_CEIL] = 1;
15107 operands[2] = assign_386_stack_local (HImode, SLOT_CW_STORED);
15108 operands[3] = assign_386_stack_local (HImode, SLOT_CW_CEIL);
15110 emit_insn (gen_frndintxf2_ceil_i387 (operands[0], operands[1],
15111 operands[2], operands[3]));
15114 [(set_attr "type" "frndint")
15115 (set_attr "i387_cw" "ceil")
15116 (set_attr "mode" "XF")])
15118 (define_insn "frndintxf2_ceil_i387"
15119 [(set (match_operand:XF 0 "register_operand" "=f")
15120 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
15121 UNSPEC_FRNDINT_CEIL))
15122 (use (match_operand:HI 2 "memory_operand" "m"))
15123 (use (match_operand:HI 3 "memory_operand" "m"))]
15124 "TARGET_USE_FANCY_MATH_387
15125 && flag_unsafe_math_optimizations"
15126 "fldcw\t%3\n\tfrndint\n\tfldcw\t%2"
15127 [(set_attr "type" "frndint")
15128 (set_attr "i387_cw" "ceil")
15129 (set_attr "mode" "XF")])
15131 (define_expand "ceilxf2"
15132 [(use (match_operand:XF 0 "register_operand" ""))
15133 (use (match_operand:XF 1 "register_operand" ""))]
15134 "TARGET_USE_FANCY_MATH_387
15135 && flag_unsafe_math_optimizations"
15137 if (optimize_insn_for_size_p ())
15139 emit_insn (gen_frndintxf2_ceil (operands[0], operands[1]));
15143 (define_expand "ceil<mode>2"
15144 [(use (match_operand:MODEF 0 "register_operand" ""))
15145 (use (match_operand:MODEF 1 "register_operand" ""))]
15146 "(TARGET_USE_FANCY_MATH_387
15147 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
15148 || TARGET_MIX_SSE_I387)
15149 && flag_unsafe_math_optimizations)
15150 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
15151 && !flag_trapping_math)"
15153 if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
15154 && !flag_trapping_math)
15157 emit_insn (gen_sse4_1_round<mode>2
15158 (operands[0], operands[1], GEN_INT (ROUND_CEIL)));
15159 else if (optimize_insn_for_size_p ())
15161 else if (TARGET_64BIT || (<MODE>mode != DFmode))
15162 ix86_expand_floorceil (operands[0], operands[1], false);
15164 ix86_expand_floorceildf_32 (operands[0], operands[1], false);
15170 if (optimize_insn_for_size_p ())
15173 op0 = gen_reg_rtx (XFmode);
15174 op1 = gen_reg_rtx (XFmode);
15175 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
15176 emit_insn (gen_frndintxf2_ceil (op0, op1));
15178 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
15183 (define_insn_and_split "*fist<mode>2_ceil_1"
15184 [(set (match_operand:SWI248x 0 "nonimmediate_operand" "")
15185 (unspec:SWI248x [(match_operand:XF 1 "register_operand" "")]
15187 (clobber (reg:CC FLAGS_REG))]
15188 "TARGET_USE_FANCY_MATH_387
15189 && flag_unsafe_math_optimizations
15190 && can_create_pseudo_p ()"
15195 ix86_optimize_mode_switching[I387_CEIL] = 1;
15197 operands[2] = assign_386_stack_local (HImode, SLOT_CW_STORED);
15198 operands[3] = assign_386_stack_local (HImode, SLOT_CW_CEIL);
15199 if (memory_operand (operands[0], VOIDmode))
15200 emit_insn (gen_fist<mode>2_ceil (operands[0], operands[1],
15201 operands[2], operands[3]));
15204 operands[4] = assign_386_stack_local (<MODE>mode, SLOT_TEMP);
15205 emit_insn (gen_fist<mode>2_ceil_with_temp (operands[0], operands[1],
15206 operands[2], operands[3],
15211 [(set_attr "type" "fistp")
15212 (set_attr "i387_cw" "ceil")
15213 (set_attr "mode" "<MODE>")])
15215 (define_insn "fistdi2_ceil"
15216 [(set (match_operand:DI 0 "memory_operand" "=m")
15217 (unspec:DI [(match_operand:XF 1 "register_operand" "f")]
15219 (use (match_operand:HI 2 "memory_operand" "m"))
15220 (use (match_operand:HI 3 "memory_operand" "m"))
15221 (clobber (match_scratch:XF 4 "=&1f"))]
15222 "TARGET_USE_FANCY_MATH_387
15223 && flag_unsafe_math_optimizations"
15224 "* return output_fix_trunc (insn, operands, false);"
15225 [(set_attr "type" "fistp")
15226 (set_attr "i387_cw" "ceil")
15227 (set_attr "mode" "DI")])
15229 (define_insn "fistdi2_ceil_with_temp"
15230 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
15231 (unspec:DI [(match_operand:XF 1 "register_operand" "f,f")]
15233 (use (match_operand:HI 2 "memory_operand" "m,m"))
15234 (use (match_operand:HI 3 "memory_operand" "m,m"))
15235 (clobber (match_operand:DI 4 "memory_operand" "=X,m"))
15236 (clobber (match_scratch:XF 5 "=&1f,&1f"))]
15237 "TARGET_USE_FANCY_MATH_387
15238 && flag_unsafe_math_optimizations"
15240 [(set_attr "type" "fistp")
15241 (set_attr "i387_cw" "ceil")
15242 (set_attr "mode" "DI")])
15245 [(set (match_operand:DI 0 "register_operand" "")
15246 (unspec:DI [(match_operand:XF 1 "register_operand" "")]
15248 (use (match_operand:HI 2 "memory_operand" ""))
15249 (use (match_operand:HI 3 "memory_operand" ""))
15250 (clobber (match_operand:DI 4 "memory_operand" ""))
15251 (clobber (match_scratch 5 ""))]
15253 [(parallel [(set (match_dup 4)
15254 (unspec:DI [(match_dup 1)] UNSPEC_FIST_CEIL))
15255 (use (match_dup 2))
15256 (use (match_dup 3))
15257 (clobber (match_dup 5))])
15258 (set (match_dup 0) (match_dup 4))])
15261 [(set (match_operand:DI 0 "memory_operand" "")
15262 (unspec:DI [(match_operand:XF 1 "register_operand" "")]
15264 (use (match_operand:HI 2 "memory_operand" ""))
15265 (use (match_operand:HI 3 "memory_operand" ""))
15266 (clobber (match_operand:DI 4 "memory_operand" ""))
15267 (clobber (match_scratch 5 ""))]
15269 [(parallel [(set (match_dup 0)
15270 (unspec:DI [(match_dup 1)] UNSPEC_FIST_CEIL))
15271 (use (match_dup 2))
15272 (use (match_dup 3))
15273 (clobber (match_dup 5))])])
15275 (define_insn "fist<mode>2_ceil"
15276 [(set (match_operand:SWI24 0 "memory_operand" "=m")
15277 (unspec:SWI24 [(match_operand:XF 1 "register_operand" "f")]
15279 (use (match_operand:HI 2 "memory_operand" "m"))
15280 (use (match_operand:HI 3 "memory_operand" "m"))]
15281 "TARGET_USE_FANCY_MATH_387
15282 && flag_unsafe_math_optimizations"
15283 "* return output_fix_trunc (insn, operands, false);"
15284 [(set_attr "type" "fistp")
15285 (set_attr "i387_cw" "ceil")
15286 (set_attr "mode" "<MODE>")])
15288 (define_insn "fist<mode>2_ceil_with_temp"
15289 [(set (match_operand:SWI24 0 "nonimmediate_operand" "=m,?r")
15290 (unspec:SWI24 [(match_operand:XF 1 "register_operand" "f,f")]
15292 (use (match_operand:HI 2 "memory_operand" "m,m"))
15293 (use (match_operand:HI 3 "memory_operand" "m,m"))
15294 (clobber (match_operand:SWI24 4 "memory_operand" "=X,m"))]
15295 "TARGET_USE_FANCY_MATH_387
15296 && flag_unsafe_math_optimizations"
15298 [(set_attr "type" "fistp")
15299 (set_attr "i387_cw" "ceil")
15300 (set_attr "mode" "<MODE>")])
15303 [(set (match_operand:SWI24 0 "register_operand" "")
15304 (unspec:SWI24 [(match_operand:XF 1 "register_operand" "")]
15306 (use (match_operand:HI 2 "memory_operand" ""))
15307 (use (match_operand:HI 3 "memory_operand" ""))
15308 (clobber (match_operand:SWI24 4 "memory_operand" ""))]
15310 [(parallel [(set (match_dup 4)
15311 (unspec:SWI24 [(match_dup 1)] UNSPEC_FIST_CEIL))
15312 (use (match_dup 2))
15313 (use (match_dup 3))])
15314 (set (match_dup 0) (match_dup 4))])
15317 [(set (match_operand:SWI24 0 "memory_operand" "")
15318 (unspec:SWI24 [(match_operand:XF 1 "register_operand" "")]
15320 (use (match_operand:HI 2 "memory_operand" ""))
15321 (use (match_operand:HI 3 "memory_operand" ""))
15322 (clobber (match_operand:SWI24 4 "memory_operand" ""))]
15324 [(parallel [(set (match_dup 0)
15325 (unspec:SWI24 [(match_dup 1)] UNSPEC_FIST_CEIL))
15326 (use (match_dup 2))
15327 (use (match_dup 3))])])
15329 (define_expand "lceilxf<mode>2"
15330 [(parallel [(set (match_operand:SWI248x 0 "nonimmediate_operand" "")
15331 (unspec:SWI248x [(match_operand:XF 1 "register_operand" "")]
15333 (clobber (reg:CC FLAGS_REG))])]
15334 "TARGET_USE_FANCY_MATH_387
15335 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
15336 && flag_unsafe_math_optimizations")
15338 (define_expand "lceil<MODEF:mode><SWI48:mode>2"
15339 [(match_operand:SWI48 0 "nonimmediate_operand" "")
15340 (match_operand:MODEF 1 "register_operand" "")]
15341 "SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
15342 && !flag_trapping_math"
15344 ix86_expand_lfloorceil (operands[0], operands[1], false);
15348 ;; Rounding mode control word calculation could clobber FLAGS_REG.
15349 (define_insn_and_split "frndintxf2_trunc"
15350 [(set (match_operand:XF 0 "register_operand" "")
15351 (unspec:XF [(match_operand:XF 1 "register_operand" "")]
15352 UNSPEC_FRNDINT_TRUNC))
15353 (clobber (reg:CC FLAGS_REG))]
15354 "TARGET_USE_FANCY_MATH_387
15355 && flag_unsafe_math_optimizations
15356 && can_create_pseudo_p ()"
15361 ix86_optimize_mode_switching[I387_TRUNC] = 1;
15363 operands[2] = assign_386_stack_local (HImode, SLOT_CW_STORED);
15364 operands[3] = assign_386_stack_local (HImode, SLOT_CW_TRUNC);
15366 emit_insn (gen_frndintxf2_trunc_i387 (operands[0], operands[1],
15367 operands[2], operands[3]));
15370 [(set_attr "type" "frndint")
15371 (set_attr "i387_cw" "trunc")
15372 (set_attr "mode" "XF")])
15374 (define_insn "frndintxf2_trunc_i387"
15375 [(set (match_operand:XF 0 "register_operand" "=f")
15376 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
15377 UNSPEC_FRNDINT_TRUNC))
15378 (use (match_operand:HI 2 "memory_operand" "m"))
15379 (use (match_operand:HI 3 "memory_operand" "m"))]
15380 "TARGET_USE_FANCY_MATH_387
15381 && flag_unsafe_math_optimizations"
15382 "fldcw\t%3\n\tfrndint\n\tfldcw\t%2"
15383 [(set_attr "type" "frndint")
15384 (set_attr "i387_cw" "trunc")
15385 (set_attr "mode" "XF")])
15387 (define_expand "btruncxf2"
15388 [(use (match_operand:XF 0 "register_operand" ""))
15389 (use (match_operand:XF 1 "register_operand" ""))]
15390 "TARGET_USE_FANCY_MATH_387
15391 && flag_unsafe_math_optimizations"
15393 if (optimize_insn_for_size_p ())
15395 emit_insn (gen_frndintxf2_trunc (operands[0], operands[1]));
15399 (define_expand "btrunc<mode>2"
15400 [(use (match_operand:MODEF 0 "register_operand" ""))
15401 (use (match_operand:MODEF 1 "register_operand" ""))]
15402 "(TARGET_USE_FANCY_MATH_387
15403 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
15404 || TARGET_MIX_SSE_I387)
15405 && flag_unsafe_math_optimizations)
15406 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
15407 && !flag_trapping_math)"
15409 if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
15410 && !flag_trapping_math)
15413 emit_insn (gen_sse4_1_round<mode>2
15414 (operands[0], operands[1], GEN_INT (ROUND_TRUNC)));
15415 else if (optimize_insn_for_size_p ())
15417 else if (TARGET_64BIT || (<MODE>mode != DFmode))
15418 ix86_expand_trunc (operands[0], operands[1]);
15420 ix86_expand_truncdf_32 (operands[0], operands[1]);
15426 if (optimize_insn_for_size_p ())
15429 op0 = gen_reg_rtx (XFmode);
15430 op1 = gen_reg_rtx (XFmode);
15431 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
15432 emit_insn (gen_frndintxf2_trunc (op0, op1));
15434 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
15439 ;; Rounding mode control word calculation could clobber FLAGS_REG.
15440 (define_insn_and_split "frndintxf2_mask_pm"
15441 [(set (match_operand:XF 0 "register_operand" "")
15442 (unspec:XF [(match_operand:XF 1 "register_operand" "")]
15443 UNSPEC_FRNDINT_MASK_PM))
15444 (clobber (reg:CC FLAGS_REG))]
15445 "TARGET_USE_FANCY_MATH_387
15446 && flag_unsafe_math_optimizations
15447 && can_create_pseudo_p ()"
15452 ix86_optimize_mode_switching[I387_MASK_PM] = 1;
15454 operands[2] = assign_386_stack_local (HImode, SLOT_CW_STORED);
15455 operands[3] = assign_386_stack_local (HImode, SLOT_CW_MASK_PM);
15457 emit_insn (gen_frndintxf2_mask_pm_i387 (operands[0], operands[1],
15458 operands[2], operands[3]));
15461 [(set_attr "type" "frndint")
15462 (set_attr "i387_cw" "mask_pm")
15463 (set_attr "mode" "XF")])
15465 (define_insn "frndintxf2_mask_pm_i387"
15466 [(set (match_operand:XF 0 "register_operand" "=f")
15467 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
15468 UNSPEC_FRNDINT_MASK_PM))
15469 (use (match_operand:HI 2 "memory_operand" "m"))
15470 (use (match_operand:HI 3 "memory_operand" "m"))]
15471 "TARGET_USE_FANCY_MATH_387
15472 && flag_unsafe_math_optimizations"
15473 "fldcw\t%3\n\tfrndint\n\tfclex\n\tfldcw\t%2"
15474 [(set_attr "type" "frndint")
15475 (set_attr "i387_cw" "mask_pm")
15476 (set_attr "mode" "XF")])
15478 (define_expand "nearbyintxf2"
15479 [(use (match_operand:XF 0 "register_operand" ""))
15480 (use (match_operand:XF 1 "register_operand" ""))]
15481 "TARGET_USE_FANCY_MATH_387
15482 && flag_unsafe_math_optimizations"
15484 emit_insn (gen_frndintxf2_mask_pm (operands[0], operands[1]));
15488 (define_expand "nearbyint<mode>2"
15489 [(use (match_operand:MODEF 0 "register_operand" ""))
15490 (use (match_operand:MODEF 1 "register_operand" ""))]
15491 "TARGET_USE_FANCY_MATH_387
15492 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
15493 || TARGET_MIX_SSE_I387)
15494 && flag_unsafe_math_optimizations"
15496 rtx op0 = gen_reg_rtx (XFmode);
15497 rtx op1 = gen_reg_rtx (XFmode);
15499 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
15500 emit_insn (gen_frndintxf2_mask_pm (op0, op1));
15502 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
15506 (define_insn "fxam<mode>2_i387"
15507 [(set (match_operand:HI 0 "register_operand" "=a")
15509 [(match_operand:X87MODEF 1 "register_operand" "f")]
15511 "TARGET_USE_FANCY_MATH_387"
15512 "fxam\n\tfnstsw\t%0"
15513 [(set_attr "type" "multi")
15514 (set_attr "length" "4")
15515 (set_attr "unit" "i387")
15516 (set_attr "mode" "<MODE>")])
15518 (define_insn_and_split "fxam<mode>2_i387_with_temp"
15519 [(set (match_operand:HI 0 "register_operand" "")
15521 [(match_operand:MODEF 1 "memory_operand" "")]
15523 "TARGET_USE_FANCY_MATH_387
15524 && can_create_pseudo_p ()"
15527 [(set (match_dup 2)(match_dup 1))
15529 (unspec:HI [(match_dup 2)] UNSPEC_FXAM))]
15531 operands[2] = gen_reg_rtx (<MODE>mode);
15533 MEM_VOLATILE_P (operands[1]) = 1;
15535 [(set_attr "type" "multi")
15536 (set_attr "unit" "i387")
15537 (set_attr "mode" "<MODE>")])
15539 (define_expand "isinfxf2"
15540 [(use (match_operand:SI 0 "register_operand" ""))
15541 (use (match_operand:XF 1 "register_operand" ""))]
15542 "TARGET_USE_FANCY_MATH_387
15543 && TARGET_C99_FUNCTIONS"
15545 rtx mask = GEN_INT (0x45);
15546 rtx val = GEN_INT (0x05);
15550 rtx scratch = gen_reg_rtx (HImode);
15551 rtx res = gen_reg_rtx (QImode);
15553 emit_insn (gen_fxamxf2_i387 (scratch, operands[1]));
15555 emit_insn (gen_andqi_ext_0 (scratch, scratch, mask));
15556 emit_insn (gen_cmpqi_ext_3 (scratch, val));
15557 cond = gen_rtx_fmt_ee (EQ, QImode,
15558 gen_rtx_REG (CCmode, FLAGS_REG),
15560 emit_insn (gen_rtx_SET (VOIDmode, res, cond));
15561 emit_insn (gen_zero_extendqisi2 (operands[0], res));
15565 (define_expand "isinf<mode>2"
15566 [(use (match_operand:SI 0 "register_operand" ""))
15567 (use (match_operand:MODEF 1 "nonimmediate_operand" ""))]
15568 "TARGET_USE_FANCY_MATH_387
15569 && TARGET_C99_FUNCTIONS
15570 && !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
15572 rtx mask = GEN_INT (0x45);
15573 rtx val = GEN_INT (0x05);
15577 rtx scratch = gen_reg_rtx (HImode);
15578 rtx res = gen_reg_rtx (QImode);
15580 /* Remove excess precision by forcing value through memory. */
15581 if (memory_operand (operands[1], VOIDmode))
15582 emit_insn (gen_fxam<mode>2_i387_with_temp (scratch, operands[1]));
15585 rtx temp = assign_386_stack_local (<MODE>mode, SLOT_TEMP);
15587 emit_move_insn (temp, operands[1]);
15588 emit_insn (gen_fxam<mode>2_i387_with_temp (scratch, temp));
15591 emit_insn (gen_andqi_ext_0 (scratch, scratch, mask));
15592 emit_insn (gen_cmpqi_ext_3 (scratch, val));
15593 cond = gen_rtx_fmt_ee (EQ, QImode,
15594 gen_rtx_REG (CCmode, FLAGS_REG),
15596 emit_insn (gen_rtx_SET (VOIDmode, res, cond));
15597 emit_insn (gen_zero_extendqisi2 (operands[0], res));
15601 (define_expand "signbitxf2"
15602 [(use (match_operand:SI 0 "register_operand" ""))
15603 (use (match_operand:XF 1 "register_operand" ""))]
15604 "TARGET_USE_FANCY_MATH_387"
15606 rtx scratch = gen_reg_rtx (HImode);
15608 emit_insn (gen_fxamxf2_i387 (scratch, operands[1]));
15609 emit_insn (gen_andsi3 (operands[0],
15610 gen_lowpart (SImode, scratch), GEN_INT (0x200)));
15614 (define_insn "movmsk_df"
15615 [(set (match_operand:SI 0 "register_operand" "=r")
15617 [(match_operand:DF 1 "register_operand" "x")]
15619 "SSE_FLOAT_MODE_P (DFmode) && TARGET_SSE_MATH"
15620 "%vmovmskpd\t{%1, %0|%0, %1}"
15621 [(set_attr "type" "ssemov")
15622 (set_attr "prefix" "maybe_vex")
15623 (set_attr "mode" "DF")])
15625 ;; Use movmskpd in SSE mode to avoid store forwarding stall
15626 ;; for 32bit targets and movq+shrq sequence for 64bit targets.
15627 (define_expand "signbitdf2"
15628 [(use (match_operand:SI 0 "register_operand" ""))
15629 (use (match_operand:DF 1 "register_operand" ""))]
15630 "TARGET_USE_FANCY_MATH_387
15631 || (SSE_FLOAT_MODE_P (DFmode) && TARGET_SSE_MATH)"
15633 if (SSE_FLOAT_MODE_P (DFmode) && TARGET_SSE_MATH)
15635 emit_insn (gen_movmsk_df (operands[0], operands[1]));
15636 emit_insn (gen_andsi3 (operands[0], operands[0], const1_rtx));
15640 rtx scratch = gen_reg_rtx (HImode);
15642 emit_insn (gen_fxamdf2_i387 (scratch, operands[1]));
15643 emit_insn (gen_andsi3 (operands[0],
15644 gen_lowpart (SImode, scratch), GEN_INT (0x200)));
15649 (define_expand "signbitsf2"
15650 [(use (match_operand:SI 0 "register_operand" ""))
15651 (use (match_operand:SF 1 "register_operand" ""))]
15652 "TARGET_USE_FANCY_MATH_387
15653 && !(SSE_FLOAT_MODE_P (SFmode) && TARGET_SSE_MATH)"
15655 rtx scratch = gen_reg_rtx (HImode);
15657 emit_insn (gen_fxamsf2_i387 (scratch, operands[1]));
15658 emit_insn (gen_andsi3 (operands[0],
15659 gen_lowpart (SImode, scratch), GEN_INT (0x200)));
15663 ;; Block operation instructions
15666 [(unspec_volatile [(const_int 0)] UNSPECV_CLD)]
15669 [(set_attr "length" "1")
15670 (set_attr "length_immediate" "0")
15671 (set_attr "modrm" "0")])
15673 (define_expand "movmem<mode>"
15674 [(use (match_operand:BLK 0 "memory_operand" ""))
15675 (use (match_operand:BLK 1 "memory_operand" ""))
15676 (use (match_operand:SWI48 2 "nonmemory_operand" ""))
15677 (use (match_operand:SWI48 3 "const_int_operand" ""))
15678 (use (match_operand:SI 4 "const_int_operand" ""))
15679 (use (match_operand:SI 5 "const_int_operand" ""))]
15682 if (ix86_expand_movmem (operands[0], operands[1], operands[2], operands[3],
15683 operands[4], operands[5]))
15689 ;; Most CPUs don't like single string operations
15690 ;; Handle this case here to simplify previous expander.
15692 (define_expand "strmov"
15693 [(set (match_dup 4) (match_operand 3 "memory_operand" ""))
15694 (set (match_operand 1 "memory_operand" "") (match_dup 4))
15695 (parallel [(set (match_operand 0 "register_operand" "") (match_dup 5))
15696 (clobber (reg:CC FLAGS_REG))])
15697 (parallel [(set (match_operand 2 "register_operand" "") (match_dup 6))
15698 (clobber (reg:CC FLAGS_REG))])]
15701 rtx adjust = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[1])));
15703 /* If .md ever supports :P for Pmode, these can be directly
15704 in the pattern above. */
15705 operands[5] = gen_rtx_PLUS (Pmode, operands[0], adjust);
15706 operands[6] = gen_rtx_PLUS (Pmode, operands[2], adjust);
15708 /* Can't use this if the user has appropriated esi or edi. */
15709 if ((TARGET_SINGLE_STRINGOP || optimize_insn_for_size_p ())
15710 && !(fixed_regs[SI_REG] || fixed_regs[DI_REG]))
15712 emit_insn (gen_strmov_singleop (operands[0], operands[1],
15713 operands[2], operands[3],
15714 operands[5], operands[6]));
15718 operands[4] = gen_reg_rtx (GET_MODE (operands[1]));
15721 (define_expand "strmov_singleop"
15722 [(parallel [(set (match_operand 1 "memory_operand" "")
15723 (match_operand 3 "memory_operand" ""))
15724 (set (match_operand 0 "register_operand" "")
15725 (match_operand 4 "" ""))
15726 (set (match_operand 2 "register_operand" "")
15727 (match_operand 5 "" ""))])]
15729 "ix86_current_function_needs_cld = 1;")
15731 (define_insn "*strmovdi_rex_1"
15732 [(set (mem:DI (match_operand:DI 2 "register_operand" "0"))
15733 (mem:DI (match_operand:DI 3 "register_operand" "1")))
15734 (set (match_operand:DI 0 "register_operand" "=D")
15735 (plus:DI (match_dup 2)
15737 (set (match_operand:DI 1 "register_operand" "=S")
15738 (plus:DI (match_dup 3)
15741 && !(fixed_regs[SI_REG] || fixed_regs[DI_REG])"
15743 [(set_attr "type" "str")
15744 (set_attr "memory" "both")
15745 (set_attr "mode" "DI")])
15747 (define_insn "*strmovsi_1"
15748 [(set (mem:SI (match_operand:P 2 "register_operand" "0"))
15749 (mem:SI (match_operand:P 3 "register_operand" "1")))
15750 (set (match_operand:P 0 "register_operand" "=D")
15751 (plus:P (match_dup 2)
15753 (set (match_operand:P 1 "register_operand" "=S")
15754 (plus:P (match_dup 3)
15756 "!(fixed_regs[SI_REG] || fixed_regs[DI_REG])"
15758 [(set_attr "type" "str")
15759 (set_attr "memory" "both")
15760 (set_attr "mode" "SI")])
15762 (define_insn "*strmovhi_1"
15763 [(set (mem:HI (match_operand:P 2 "register_operand" "0"))
15764 (mem:HI (match_operand:P 3 "register_operand" "1")))
15765 (set (match_operand:P 0 "register_operand" "=D")
15766 (plus:P (match_dup 2)
15768 (set (match_operand:P 1 "register_operand" "=S")
15769 (plus:P (match_dup 3)
15771 "!(fixed_regs[SI_REG] || fixed_regs[DI_REG])"
15773 [(set_attr "type" "str")
15774 (set_attr "memory" "both")
15775 (set_attr "mode" "HI")])
15777 (define_insn "*strmovqi_1"
15778 [(set (mem:QI (match_operand:P 2 "register_operand" "0"))
15779 (mem:QI (match_operand:P 3 "register_operand" "1")))
15780 (set (match_operand:P 0 "register_operand" "=D")
15781 (plus:P (match_dup 2)
15783 (set (match_operand:P 1 "register_operand" "=S")
15784 (plus:P (match_dup 3)
15786 "!(fixed_regs[SI_REG] || fixed_regs[DI_REG])"
15788 [(set_attr "type" "str")
15789 (set_attr "memory" "both")
15790 (set (attr "prefix_rex")
15792 (match_test "<P:MODE>mode == DImode")
15794 (const_string "*")))
15795 (set_attr "mode" "QI")])
15797 (define_expand "rep_mov"
15798 [(parallel [(set (match_operand 4 "register_operand" "") (const_int 0))
15799 (set (match_operand 0 "register_operand" "")
15800 (match_operand 5 "" ""))
15801 (set (match_operand 2 "register_operand" "")
15802 (match_operand 6 "" ""))
15803 (set (match_operand 1 "memory_operand" "")
15804 (match_operand 3 "memory_operand" ""))
15805 (use (match_dup 4))])]
15807 "ix86_current_function_needs_cld = 1;")
15809 (define_insn "*rep_movdi_rex64"
15810 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
15811 (set (match_operand:DI 0 "register_operand" "=D")
15812 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
15814 (match_operand:DI 3 "register_operand" "0")))
15815 (set (match_operand:DI 1 "register_operand" "=S")
15816 (plus:DI (ashift:DI (match_dup 5) (const_int 3))
15817 (match_operand:DI 4 "register_operand" "1")))
15818 (set (mem:BLK (match_dup 3))
15819 (mem:BLK (match_dup 4)))
15820 (use (match_dup 5))]
15822 && !(fixed_regs[CX_REG] || fixed_regs[SI_REG] || fixed_regs[DI_REG])"
15824 [(set_attr "type" "str")
15825 (set_attr "prefix_rep" "1")
15826 (set_attr "memory" "both")
15827 (set_attr "mode" "DI")])
15829 (define_insn "*rep_movsi"
15830 [(set (match_operand:P 2 "register_operand" "=c") (const_int 0))
15831 (set (match_operand:P 0 "register_operand" "=D")
15832 (plus:P (ashift:P (match_operand:P 5 "register_operand" "2")
15834 (match_operand:P 3 "register_operand" "0")))
15835 (set (match_operand:P 1 "register_operand" "=S")
15836 (plus:P (ashift:P (match_dup 5) (const_int 2))
15837 (match_operand:P 4 "register_operand" "1")))
15838 (set (mem:BLK (match_dup 3))
15839 (mem:BLK (match_dup 4)))
15840 (use (match_dup 5))]
15841 "!(fixed_regs[CX_REG] || fixed_regs[SI_REG] || fixed_regs[DI_REG])"
15842 "rep{%;} movs{l|d}"
15843 [(set_attr "type" "str")
15844 (set_attr "prefix_rep" "1")
15845 (set_attr "memory" "both")
15846 (set_attr "mode" "SI")])
15848 (define_insn "*rep_movqi"
15849 [(set (match_operand:P 2 "register_operand" "=c") (const_int 0))
15850 (set (match_operand:P 0 "register_operand" "=D")
15851 (plus:P (match_operand:P 3 "register_operand" "0")
15852 (match_operand:P 5 "register_operand" "2")))
15853 (set (match_operand:P 1 "register_operand" "=S")
15854 (plus:P (match_operand:P 4 "register_operand" "1") (match_dup 5)))
15855 (set (mem:BLK (match_dup 3))
15856 (mem:BLK (match_dup 4)))
15857 (use (match_dup 5))]
15858 "!(fixed_regs[CX_REG] || fixed_regs[SI_REG] || fixed_regs[DI_REG])"
15860 [(set_attr "type" "str")
15861 (set_attr "prefix_rep" "1")
15862 (set_attr "memory" "both")
15863 (set_attr "mode" "QI")])
15865 (define_expand "setmem<mode>"
15866 [(use (match_operand:BLK 0 "memory_operand" ""))
15867 (use (match_operand:SWI48 1 "nonmemory_operand" ""))
15868 (use (match_operand:QI 2 "nonmemory_operand" ""))
15869 (use (match_operand 3 "const_int_operand" ""))
15870 (use (match_operand:SI 4 "const_int_operand" ""))
15871 (use (match_operand:SI 5 "const_int_operand" ""))]
15874 if (ix86_expand_setmem (operands[0], operands[1],
15875 operands[2], operands[3],
15876 operands[4], operands[5]))
15882 ;; Most CPUs don't like single string operations
15883 ;; Handle this case here to simplify previous expander.
15885 (define_expand "strset"
15886 [(set (match_operand 1 "memory_operand" "")
15887 (match_operand 2 "register_operand" ""))
15888 (parallel [(set (match_operand 0 "register_operand" "")
15890 (clobber (reg:CC FLAGS_REG))])]
15893 if (GET_MODE (operands[1]) != GET_MODE (operands[2]))
15894 operands[1] = adjust_address_nv (operands[1], GET_MODE (operands[2]), 0);
15896 /* If .md ever supports :P for Pmode, this can be directly
15897 in the pattern above. */
15898 operands[3] = gen_rtx_PLUS (Pmode, operands[0],
15899 GEN_INT (GET_MODE_SIZE (GET_MODE
15901 /* Can't use this if the user has appropriated eax or edi. */
15902 if ((TARGET_SINGLE_STRINGOP || optimize_insn_for_size_p ())
15903 && !(fixed_regs[AX_REG] || fixed_regs[DI_REG]))
15905 emit_insn (gen_strset_singleop (operands[0], operands[1], operands[2],
15911 (define_expand "strset_singleop"
15912 [(parallel [(set (match_operand 1 "memory_operand" "")
15913 (match_operand 2 "register_operand" ""))
15914 (set (match_operand 0 "register_operand" "")
15915 (match_operand 3 "" ""))])]
15917 "ix86_current_function_needs_cld = 1;")
15919 (define_insn "*strsetdi_rex_1"
15920 [(set (mem:DI (match_operand:DI 1 "register_operand" "0"))
15921 (match_operand:DI 2 "register_operand" "a"))
15922 (set (match_operand:DI 0 "register_operand" "=D")
15923 (plus:DI (match_dup 1)
15926 && !(fixed_regs[AX_REG] || fixed_regs[DI_REG])"
15928 [(set_attr "type" "str")
15929 (set_attr "memory" "store")
15930 (set_attr "mode" "DI")])
15932 (define_insn "*strsetsi_1"
15933 [(set (mem:SI (match_operand:P 1 "register_operand" "0"))
15934 (match_operand:SI 2 "register_operand" "a"))
15935 (set (match_operand:P 0 "register_operand" "=D")
15936 (plus:P (match_dup 1)
15938 "!(fixed_regs[AX_REG] || fixed_regs[DI_REG])"
15940 [(set_attr "type" "str")
15941 (set_attr "memory" "store")
15942 (set_attr "mode" "SI")])
15944 (define_insn "*strsethi_1"
15945 [(set (mem:HI (match_operand:P 1 "register_operand" "0"))
15946 (match_operand:HI 2 "register_operand" "a"))
15947 (set (match_operand:P 0 "register_operand" "=D")
15948 (plus:P (match_dup 1)
15950 "!(fixed_regs[AX_REG] || fixed_regs[DI_REG])"
15952 [(set_attr "type" "str")
15953 (set_attr "memory" "store")
15954 (set_attr "mode" "HI")])
15956 (define_insn "*strsetqi_1"
15957 [(set (mem:QI (match_operand:P 1 "register_operand" "0"))
15958 (match_operand:QI 2 "register_operand" "a"))
15959 (set (match_operand:P 0 "register_operand" "=D")
15960 (plus:P (match_dup 1)
15962 "!(fixed_regs[AX_REG] || fixed_regs[DI_REG])"
15964 [(set_attr "type" "str")
15965 (set_attr "memory" "store")
15966 (set (attr "prefix_rex")
15968 (match_test "<P:MODE>mode == DImode")
15970 (const_string "*")))
15971 (set_attr "mode" "QI")])
15973 (define_expand "rep_stos"
15974 [(parallel [(set (match_operand 1 "register_operand" "") (const_int 0))
15975 (set (match_operand 0 "register_operand" "")
15976 (match_operand 4 "" ""))
15977 (set (match_operand 2 "memory_operand" "") (const_int 0))
15978 (use (match_operand 3 "register_operand" ""))
15979 (use (match_dup 1))])]
15981 "ix86_current_function_needs_cld = 1;")
15983 (define_insn "*rep_stosdi_rex64"
15984 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
15985 (set (match_operand:DI 0 "register_operand" "=D")
15986 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
15988 (match_operand:DI 3 "register_operand" "0")))
15989 (set (mem:BLK (match_dup 3))
15991 (use (match_operand:DI 2 "register_operand" "a"))
15992 (use (match_dup 4))]
15994 && !(fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])"
15996 [(set_attr "type" "str")
15997 (set_attr "prefix_rep" "1")
15998 (set_attr "memory" "store")
15999 (set_attr "mode" "DI")])
16001 (define_insn "*rep_stossi"
16002 [(set (match_operand:P 1 "register_operand" "=c") (const_int 0))
16003 (set (match_operand:P 0 "register_operand" "=D")
16004 (plus:P (ashift:P (match_operand:P 4 "register_operand" "1")
16006 (match_operand:P 3 "register_operand" "0")))
16007 (set (mem:BLK (match_dup 3))
16009 (use (match_operand:SI 2 "register_operand" "a"))
16010 (use (match_dup 4))]
16011 "!(fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])"
16012 "rep{%;} stos{l|d}"
16013 [(set_attr "type" "str")
16014 (set_attr "prefix_rep" "1")
16015 (set_attr "memory" "store")
16016 (set_attr "mode" "SI")])
16018 (define_insn "*rep_stosqi"
16019 [(set (match_operand:P 1 "register_operand" "=c") (const_int 0))
16020 (set (match_operand:P 0 "register_operand" "=D")
16021 (plus:P (match_operand:P 3 "register_operand" "0")
16022 (match_operand:P 4 "register_operand" "1")))
16023 (set (mem:BLK (match_dup 3))
16025 (use (match_operand:QI 2 "register_operand" "a"))
16026 (use (match_dup 4))]
16027 "!(fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])"
16029 [(set_attr "type" "str")
16030 (set_attr "prefix_rep" "1")
16031 (set_attr "memory" "store")
16032 (set (attr "prefix_rex")
16034 (match_test "<P:MODE>mode == DImode")
16036 (const_string "*")))
16037 (set_attr "mode" "QI")])
16039 (define_expand "cmpstrnsi"
16040 [(set (match_operand:SI 0 "register_operand" "")
16041 (compare:SI (match_operand:BLK 1 "general_operand" "")
16042 (match_operand:BLK 2 "general_operand" "")))
16043 (use (match_operand 3 "general_operand" ""))
16044 (use (match_operand 4 "immediate_operand" ""))]
16047 rtx addr1, addr2, out, outlow, count, countreg, align;
16049 if (optimize_insn_for_size_p () && !TARGET_INLINE_ALL_STRINGOPS)
16052 /* Can't use this if the user has appropriated ecx, esi or edi. */
16053 if (fixed_regs[CX_REG] || fixed_regs[SI_REG] || fixed_regs[DI_REG])
16058 out = gen_reg_rtx (SImode);
16060 addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
16061 addr2 = copy_to_mode_reg (Pmode, XEXP (operands[2], 0));
16062 if (addr1 != XEXP (operands[1], 0))
16063 operands[1] = replace_equiv_address_nv (operands[1], addr1);
16064 if (addr2 != XEXP (operands[2], 0))
16065 operands[2] = replace_equiv_address_nv (operands[2], addr2);
16067 count = operands[3];
16068 countreg = ix86_zero_extend_to_Pmode (count);
16070 /* %%% Iff we are testing strict equality, we can use known alignment
16071 to good advantage. This may be possible with combine, particularly
16072 once cc0 is dead. */
16073 align = operands[4];
16075 if (CONST_INT_P (count))
16077 if (INTVAL (count) == 0)
16079 emit_move_insn (operands[0], const0_rtx);
16082 emit_insn (gen_cmpstrnqi_nz_1 (addr1, addr2, countreg, align,
16083 operands[1], operands[2]));
16087 rtx (*gen_cmp) (rtx, rtx);
16089 gen_cmp = (TARGET_64BIT
16090 ? gen_cmpdi_1 : gen_cmpsi_1);
16092 emit_insn (gen_cmp (countreg, countreg));
16093 emit_insn (gen_cmpstrnqi_1 (addr1, addr2, countreg, align,
16094 operands[1], operands[2]));
16097 outlow = gen_lowpart (QImode, out);
16098 emit_insn (gen_cmpintqi (outlow));
16099 emit_move_insn (out, gen_rtx_SIGN_EXTEND (SImode, outlow));
16101 if (operands[0] != out)
16102 emit_move_insn (operands[0], out);
16107 ;; Produce a tri-state integer (-1, 0, 1) from condition codes.
16109 (define_expand "cmpintqi"
16110 [(set (match_dup 1)
16111 (gtu:QI (reg:CC FLAGS_REG) (const_int 0)))
16113 (ltu:QI (reg:CC FLAGS_REG) (const_int 0)))
16114 (parallel [(set (match_operand:QI 0 "register_operand" "")
16115 (minus:QI (match_dup 1)
16117 (clobber (reg:CC FLAGS_REG))])]
16120 operands[1] = gen_reg_rtx (QImode);
16121 operands[2] = gen_reg_rtx (QImode);
16124 ;; memcmp recognizers. The `cmpsb' opcode does nothing if the count is
16125 ;; zero. Emit extra code to make sure that a zero-length compare is EQ.
16127 (define_expand "cmpstrnqi_nz_1"
16128 [(parallel [(set (reg:CC FLAGS_REG)
16129 (compare:CC (match_operand 4 "memory_operand" "")
16130 (match_operand 5 "memory_operand" "")))
16131 (use (match_operand 2 "register_operand" ""))
16132 (use (match_operand:SI 3 "immediate_operand" ""))
16133 (clobber (match_operand 0 "register_operand" ""))
16134 (clobber (match_operand 1 "register_operand" ""))
16135 (clobber (match_dup 2))])]
16137 "ix86_current_function_needs_cld = 1;")
16139 (define_insn "*cmpstrnqi_nz_1"
16140 [(set (reg:CC FLAGS_REG)
16141 (compare:CC (mem:BLK (match_operand:P 4 "register_operand" "0"))
16142 (mem:BLK (match_operand:P 5 "register_operand" "1"))))
16143 (use (match_operand:P 6 "register_operand" "2"))
16144 (use (match_operand:SI 3 "immediate_operand" "i"))
16145 (clobber (match_operand:P 0 "register_operand" "=S"))
16146 (clobber (match_operand:P 1 "register_operand" "=D"))
16147 (clobber (match_operand:P 2 "register_operand" "=c"))]
16148 "!(fixed_regs[CX_REG] || fixed_regs[SI_REG] || fixed_regs[DI_REG])"
16150 [(set_attr "type" "str")
16151 (set_attr "mode" "QI")
16152 (set (attr "prefix_rex")
16154 (match_test "<P:MODE>mode == DImode")
16156 (const_string "*")))
16157 (set_attr "prefix_rep" "1")])
16159 ;; The same, but the count is not known to not be zero.
16161 (define_expand "cmpstrnqi_1"
16162 [(parallel [(set (reg:CC FLAGS_REG)
16163 (if_then_else:CC (ne (match_operand 2 "register_operand" "")
16165 (compare:CC (match_operand 4 "memory_operand" "")
16166 (match_operand 5 "memory_operand" ""))
16168 (use (match_operand:SI 3 "immediate_operand" ""))
16169 (use (reg:CC FLAGS_REG))
16170 (clobber (match_operand 0 "register_operand" ""))
16171 (clobber (match_operand 1 "register_operand" ""))
16172 (clobber (match_dup 2))])]
16174 "ix86_current_function_needs_cld = 1;")
16176 (define_insn "*cmpstrnqi_1"
16177 [(set (reg:CC FLAGS_REG)
16178 (if_then_else:CC (ne (match_operand:P 6 "register_operand" "2")
16180 (compare:CC (mem:BLK (match_operand:P 4 "register_operand" "0"))
16181 (mem:BLK (match_operand:P 5 "register_operand" "1")))
16183 (use (match_operand:SI 3 "immediate_operand" "i"))
16184 (use (reg:CC FLAGS_REG))
16185 (clobber (match_operand:P 0 "register_operand" "=S"))
16186 (clobber (match_operand:P 1 "register_operand" "=D"))
16187 (clobber (match_operand:P 2 "register_operand" "=c"))]
16188 "!(fixed_regs[CX_REG] || fixed_regs[SI_REG] || fixed_regs[DI_REG])"
16190 [(set_attr "type" "str")
16191 (set_attr "mode" "QI")
16192 (set (attr "prefix_rex")
16194 (match_test "<P:MODE>mode == DImode")
16196 (const_string "*")))
16197 (set_attr "prefix_rep" "1")])
16199 (define_expand "strlen<mode>"
16200 [(set (match_operand:P 0 "register_operand" "")
16201 (unspec:P [(match_operand:BLK 1 "general_operand" "")
16202 (match_operand:QI 2 "immediate_operand" "")
16203 (match_operand 3 "immediate_operand" "")]
16207 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
16213 (define_expand "strlenqi_1"
16214 [(parallel [(set (match_operand 0 "register_operand" "")
16215 (match_operand 2 "" ""))
16216 (clobber (match_operand 1 "register_operand" ""))
16217 (clobber (reg:CC FLAGS_REG))])]
16219 "ix86_current_function_needs_cld = 1;")
16221 (define_insn "*strlenqi_1"
16222 [(set (match_operand:P 0 "register_operand" "=&c")
16223 (unspec:P [(mem:BLK (match_operand:P 5 "register_operand" "1"))
16224 (match_operand:QI 2 "register_operand" "a")
16225 (match_operand:P 3 "immediate_operand" "i")
16226 (match_operand:P 4 "register_operand" "0")] UNSPEC_SCAS))
16227 (clobber (match_operand:P 1 "register_operand" "=D"))
16228 (clobber (reg:CC FLAGS_REG))]
16229 "!(fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])"
16231 [(set_attr "type" "str")
16232 (set_attr "mode" "QI")
16233 (set (attr "prefix_rex")
16235 (match_test "<P:MODE>mode == DImode")
16237 (const_string "*")))
16238 (set_attr "prefix_rep" "1")])
16240 ;; Peephole optimizations to clean up after cmpstrn*. This should be
16241 ;; handled in combine, but it is not currently up to the task.
16242 ;; When used for their truth value, the cmpstrn* expanders generate
16251 ;; The intermediate three instructions are unnecessary.
16253 ;; This one handles cmpstrn*_nz_1...
16256 (set (reg:CC FLAGS_REG)
16257 (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
16258 (mem:BLK (match_operand 5 "register_operand" ""))))
16259 (use (match_operand 6 "register_operand" ""))
16260 (use (match_operand:SI 3 "immediate_operand" ""))
16261 (clobber (match_operand 0 "register_operand" ""))
16262 (clobber (match_operand 1 "register_operand" ""))
16263 (clobber (match_operand 2 "register_operand" ""))])
16264 (set (match_operand:QI 7 "register_operand" "")
16265 (gtu:QI (reg:CC FLAGS_REG) (const_int 0)))
16266 (set (match_operand:QI 8 "register_operand" "")
16267 (ltu:QI (reg:CC FLAGS_REG) (const_int 0)))
16268 (set (reg FLAGS_REG)
16269 (compare (match_dup 7) (match_dup 8)))
16271 "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])"
16273 (set (reg:CC FLAGS_REG)
16274 (compare:CC (mem:BLK (match_dup 4))
16275 (mem:BLK (match_dup 5))))
16276 (use (match_dup 6))
16277 (use (match_dup 3))
16278 (clobber (match_dup 0))
16279 (clobber (match_dup 1))
16280 (clobber (match_dup 2))])])
16282 ;; ...and this one handles cmpstrn*_1.
16285 (set (reg:CC FLAGS_REG)
16286 (if_then_else:CC (ne (match_operand 6 "register_operand" "")
16288 (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
16289 (mem:BLK (match_operand 5 "register_operand" "")))
16291 (use (match_operand:SI 3 "immediate_operand" ""))
16292 (use (reg:CC FLAGS_REG))
16293 (clobber (match_operand 0 "register_operand" ""))
16294 (clobber (match_operand 1 "register_operand" ""))
16295 (clobber (match_operand 2 "register_operand" ""))])
16296 (set (match_operand:QI 7 "register_operand" "")
16297 (gtu:QI (reg:CC FLAGS_REG) (const_int 0)))
16298 (set (match_operand:QI 8 "register_operand" "")
16299 (ltu:QI (reg:CC FLAGS_REG) (const_int 0)))
16300 (set (reg FLAGS_REG)
16301 (compare (match_dup 7) (match_dup 8)))
16303 "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])"
16305 (set (reg:CC FLAGS_REG)
16306 (if_then_else:CC (ne (match_dup 6)
16308 (compare:CC (mem:BLK (match_dup 4))
16309 (mem:BLK (match_dup 5)))
16311 (use (match_dup 3))
16312 (use (reg:CC FLAGS_REG))
16313 (clobber (match_dup 0))
16314 (clobber (match_dup 1))
16315 (clobber (match_dup 2))])])
16317 ;; Conditional move instructions.
16319 (define_expand "mov<mode>cc"
16320 [(set (match_operand:SWIM 0 "register_operand" "")
16321 (if_then_else:SWIM (match_operand 1 "ordered_comparison_operator" "")
16322 (match_operand:SWIM 2 "<general_operand>" "")
16323 (match_operand:SWIM 3 "<general_operand>" "")))]
16325 "if (ix86_expand_int_movcc (operands)) DONE; else FAIL;")
16327 ;; Data flow gets confused by our desire for `sbbl reg,reg', and clearing
16328 ;; the register first winds up with `sbbl $0,reg', which is also weird.
16329 ;; So just document what we're doing explicitly.
16331 (define_expand "x86_mov<mode>cc_0_m1"
16333 [(set (match_operand:SWI48 0 "register_operand" "")
16334 (if_then_else:SWI48
16335 (match_operator:SWI48 2 "ix86_carry_flag_operator"
16336 [(match_operand 1 "flags_reg_operand" "")
16340 (clobber (reg:CC FLAGS_REG))])])
16342 (define_insn "*x86_mov<mode>cc_0_m1"
16343 [(set (match_operand:SWI48 0 "register_operand" "=r")
16344 (if_then_else:SWI48 (match_operator 1 "ix86_carry_flag_operator"
16345 [(reg FLAGS_REG) (const_int 0)])
16348 (clobber (reg:CC FLAGS_REG))]
16350 "sbb{<imodesuffix>}\t%0, %0"
16351 ; Since we don't have the proper number of operands for an alu insn,
16352 ; fill in all the blanks.
16353 [(set_attr "type" "alu")
16354 (set_attr "use_carry" "1")
16355 (set_attr "pent_pair" "pu")
16356 (set_attr "memory" "none")
16357 (set_attr "imm_disp" "false")
16358 (set_attr "mode" "<MODE>")
16359 (set_attr "length_immediate" "0")])
16361 (define_insn "*x86_mov<mode>cc_0_m1_se"
16362 [(set (match_operand:SWI48 0 "register_operand" "=r")
16363 (sign_extract:SWI48 (match_operator 1 "ix86_carry_flag_operator"
16364 [(reg FLAGS_REG) (const_int 0)])
16367 (clobber (reg:CC FLAGS_REG))]
16369 "sbb{<imodesuffix>}\t%0, %0"
16370 [(set_attr "type" "alu")
16371 (set_attr "use_carry" "1")
16372 (set_attr "pent_pair" "pu")
16373 (set_attr "memory" "none")
16374 (set_attr "imm_disp" "false")
16375 (set_attr "mode" "<MODE>")
16376 (set_attr "length_immediate" "0")])
16378 (define_insn "*x86_mov<mode>cc_0_m1_neg"
16379 [(set (match_operand:SWI48 0 "register_operand" "=r")
16380 (neg:SWI48 (match_operator 1 "ix86_carry_flag_operator"
16381 [(reg FLAGS_REG) (const_int 0)])))
16382 (clobber (reg:CC FLAGS_REG))]
16384 "sbb{<imodesuffix>}\t%0, %0"
16385 [(set_attr "type" "alu")
16386 (set_attr "use_carry" "1")
16387 (set_attr "pent_pair" "pu")
16388 (set_attr "memory" "none")
16389 (set_attr "imm_disp" "false")
16390 (set_attr "mode" "<MODE>")
16391 (set_attr "length_immediate" "0")])
16393 (define_insn "*mov<mode>cc_noc"
16394 [(set (match_operand:SWI248 0 "register_operand" "=r,r")
16395 (if_then_else:SWI248 (match_operator 1 "ix86_comparison_operator"
16396 [(reg FLAGS_REG) (const_int 0)])
16397 (match_operand:SWI248 2 "nonimmediate_operand" "rm,0")
16398 (match_operand:SWI248 3 "nonimmediate_operand" "0,rm")))]
16399 "TARGET_CMOVE && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
16401 cmov%O2%C1\t{%2, %0|%0, %2}
16402 cmov%O2%c1\t{%3, %0|%0, %3}"
16403 [(set_attr "type" "icmov")
16404 (set_attr "mode" "<MODE>")])
16406 (define_insn "*movqicc_noc"
16407 [(set (match_operand:QI 0 "register_operand" "=r,r")
16408 (if_then_else:QI (match_operator 1 "ix86_comparison_operator"
16409 [(reg FLAGS_REG) (const_int 0)])
16410 (match_operand:QI 2 "register_operand" "r,0")
16411 (match_operand:QI 3 "register_operand" "0,r")))]
16412 "TARGET_CMOVE && !TARGET_PARTIAL_REG_STALL"
16414 [(set_attr "type" "icmov")
16415 (set_attr "mode" "QI")])
16418 [(set (match_operand 0 "register_operand")
16419 (if_then_else (match_operator 1 "ix86_comparison_operator"
16420 [(reg FLAGS_REG) (const_int 0)])
16421 (match_operand 2 "register_operand")
16422 (match_operand 3 "register_operand")))]
16423 "TARGET_CMOVE && !TARGET_PARTIAL_REG_STALL
16424 && (GET_MODE (operands[0]) == QImode
16425 || GET_MODE (operands[0]) == HImode)
16426 && reload_completed"
16427 [(set (match_dup 0)
16428 (if_then_else:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
16430 operands[0] = gen_lowpart (SImode, operands[0]);
16431 operands[2] = gen_lowpart (SImode, operands[2]);
16432 operands[3] = gen_lowpart (SImode, operands[3]);
16435 (define_expand "mov<mode>cc"
16436 [(set (match_operand:X87MODEF 0 "register_operand" "")
16437 (if_then_else:X87MODEF
16438 (match_operand 1 "ix86_fp_comparison_operator" "")
16439 (match_operand:X87MODEF 2 "register_operand" "")
16440 (match_operand:X87MODEF 3 "register_operand" "")))]
16441 "(TARGET_80387 && TARGET_CMOVE)
16442 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
16443 "if (ix86_expand_fp_movcc (operands)) DONE; else FAIL;")
16445 (define_insn "*movxfcc_1"
16446 [(set (match_operand:XF 0 "register_operand" "=f,f")
16447 (if_then_else:XF (match_operator 1 "fcmov_comparison_operator"
16448 [(reg FLAGS_REG) (const_int 0)])
16449 (match_operand:XF 2 "register_operand" "f,0")
16450 (match_operand:XF 3 "register_operand" "0,f")))]
16451 "TARGET_80387 && TARGET_CMOVE"
16453 fcmov%F1\t{%2, %0|%0, %2}
16454 fcmov%f1\t{%3, %0|%0, %3}"
16455 [(set_attr "type" "fcmov")
16456 (set_attr "mode" "XF")])
16458 (define_insn "*movdfcc_1_rex64"
16459 [(set (match_operand:DF 0 "register_operand" "=f,f,r,r")
16460 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
16461 [(reg FLAGS_REG) (const_int 0)])
16462 (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0")
16463 (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))]
16464 "TARGET_64BIT && TARGET_80387 && TARGET_CMOVE
16465 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
16467 fcmov%F1\t{%2, %0|%0, %2}
16468 fcmov%f1\t{%3, %0|%0, %3}
16469 cmov%O2%C1\t{%2, %0|%0, %2}
16470 cmov%O2%c1\t{%3, %0|%0, %3}"
16471 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
16472 (set_attr "mode" "DF,DF,DI,DI")])
16474 (define_insn "*movdfcc_1"
16475 [(set (match_operand:DF 0 "register_operand" "=f,f,&r,&r")
16476 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
16477 [(reg FLAGS_REG) (const_int 0)])
16478 (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0")
16479 (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))]
16480 "!TARGET_64BIT && TARGET_80387 && TARGET_CMOVE
16481 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
16483 fcmov%F1\t{%2, %0|%0, %2}
16484 fcmov%f1\t{%3, %0|%0, %3}
16487 [(set_attr "type" "fcmov,fcmov,multi,multi")
16488 (set_attr "mode" "DF,DF,DI,DI")])
16491 [(set (match_operand:DF 0 "register_and_not_any_fp_reg_operand")
16492 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
16493 [(reg FLAGS_REG) (const_int 0)])
16494 (match_operand:DF 2 "nonimmediate_operand")
16495 (match_operand:DF 3 "nonimmediate_operand")))]
16496 "!TARGET_64BIT && reload_completed"
16497 [(set (match_dup 2)
16498 (if_then_else:SI (match_dup 1) (match_dup 4) (match_dup 5)))
16500 (if_then_else:SI (match_dup 1) (match_dup 6) (match_dup 7)))]
16502 split_double_mode (DImode, &operands[2], 2, &operands[4], &operands[6]);
16503 split_double_mode (DImode, &operands[0], 1, &operands[2], &operands[3]);
16506 (define_insn "*movsfcc_1_387"
16507 [(set (match_operand:SF 0 "register_operand" "=f,f,r,r")
16508 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
16509 [(reg FLAGS_REG) (const_int 0)])
16510 (match_operand:SF 2 "nonimmediate_operand" "f,0,rm,0")
16511 (match_operand:SF 3 "nonimmediate_operand" "0,f,0,rm")))]
16512 "TARGET_80387 && TARGET_CMOVE
16513 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
16515 fcmov%F1\t{%2, %0|%0, %2}
16516 fcmov%f1\t{%3, %0|%0, %3}
16517 cmov%O2%C1\t{%2, %0|%0, %2}
16518 cmov%O2%c1\t{%3, %0|%0, %3}"
16519 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
16520 (set_attr "mode" "SF,SF,SI,SI")])
16522 ;; All moves in XOP pcmov instructions are 128 bits and hence we restrict
16523 ;; the scalar versions to have only XMM registers as operands.
16525 ;; XOP conditional move
16526 (define_insn "*xop_pcmov_<mode>"
16527 [(set (match_operand:MODEF 0 "register_operand" "=x")
16528 (if_then_else:MODEF
16529 (match_operand:MODEF 1 "register_operand" "x")
16530 (match_operand:MODEF 2 "register_operand" "x")
16531 (match_operand:MODEF 3 "register_operand" "x")))]
16533 "vpcmov\t{%1, %3, %2, %0|%0, %2, %3, %1}"
16534 [(set_attr "type" "sse4arg")])
16536 ;; These versions of the min/max patterns are intentionally ignorant of
16537 ;; their behavior wrt -0.0 and NaN (via the commutative operand mark).
16538 ;; Since both the tree-level MAX_EXPR and the rtl-level SMAX operator
16539 ;; are undefined in this condition, we're certain this is correct.
16541 (define_insn "<code><mode>3"
16542 [(set (match_operand:MODEF 0 "register_operand" "=x,x")
16544 (match_operand:MODEF 1 "nonimmediate_operand" "%0,x")
16545 (match_operand:MODEF 2 "nonimmediate_operand" "xm,xm")))]
16546 "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
16548 <maxmin_float><ssemodesuffix>\t{%2, %0|%0, %2}
16549 v<maxmin_float><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
16550 [(set_attr "isa" "noavx,avx")
16551 (set_attr "prefix" "orig,vex")
16552 (set_attr "type" "sseadd")
16553 (set_attr "mode" "<MODE>")])
16555 ;; These versions of the min/max patterns implement exactly the operations
16556 ;; min = (op1 < op2 ? op1 : op2)
16557 ;; max = (!(op1 < op2) ? op1 : op2)
16558 ;; Their operands are not commutative, and thus they may be used in the
16559 ;; presence of -0.0 and NaN.
16561 (define_insn "*ieee_smin<mode>3"
16562 [(set (match_operand:MODEF 0 "register_operand" "=x,x")
16564 [(match_operand:MODEF 1 "register_operand" "0,x")
16565 (match_operand:MODEF 2 "nonimmediate_operand" "xm,xm")]
16567 "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
16569 min<ssemodesuffix>\t{%2, %0|%0, %2}
16570 vmin<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
16571 [(set_attr "isa" "noavx,avx")
16572 (set_attr "prefix" "orig,vex")
16573 (set_attr "type" "sseadd")
16574 (set_attr "mode" "<MODE>")])
16576 (define_insn "*ieee_smax<mode>3"
16577 [(set (match_operand:MODEF 0 "register_operand" "=x,x")
16579 [(match_operand:MODEF 1 "register_operand" "0,x")
16580 (match_operand:MODEF 2 "nonimmediate_operand" "xm,xm")]
16582 "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
16584 max<ssemodesuffix>\t{%2, %0|%0, %2}
16585 vmax<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
16586 [(set_attr "isa" "noavx,avx")
16587 (set_attr "prefix" "orig,vex")
16588 (set_attr "type" "sseadd")
16589 (set_attr "mode" "<MODE>")])
16591 ;; Make two stack loads independent:
16593 ;; fld %st(0) -> fld bb
16594 ;; fmul bb fmul %st(1), %st
16596 ;; Actually we only match the last two instructions for simplicity.
16598 [(set (match_operand 0 "fp_register_operand" "")
16599 (match_operand 1 "fp_register_operand" ""))
16601 (match_operator 2 "binary_fp_operator"
16603 (match_operand 3 "memory_operand" "")]))]
16604 "REGNO (operands[0]) != REGNO (operands[1])"
16605 [(set (match_dup 0) (match_dup 3))
16606 (set (match_dup 0) (match_dup 4))]
16608 ;; The % modifier is not operational anymore in peephole2's, so we have to
16609 ;; swap the operands manually in the case of addition and multiplication.
16613 if (COMMUTATIVE_ARITH_P (operands[2]))
16614 op0 = operands[0], op1 = operands[1];
16616 op0 = operands[1], op1 = operands[0];
16618 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[2]),
16619 GET_MODE (operands[2]),
16623 ;; Conditional addition patterns
16624 (define_expand "add<mode>cc"
16625 [(match_operand:SWI 0 "register_operand" "")
16626 (match_operand 1 "ordered_comparison_operator" "")
16627 (match_operand:SWI 2 "register_operand" "")
16628 (match_operand:SWI 3 "const_int_operand" "")]
16630 "if (ix86_expand_int_addcc (operands)) DONE; else FAIL;")
16632 ;; Misc patterns (?)
16634 ;; This pattern exists to put a dependency on all ebp-based memory accesses.
16635 ;; Otherwise there will be nothing to keep
16637 ;; [(set (reg ebp) (reg esp))]
16638 ;; [(set (reg esp) (plus (reg esp) (const_int -160000)))
16639 ;; (clobber (eflags)]
16640 ;; [(set (mem (plus (reg ebp) (const_int -160000))) (const_int 0))]
16642 ;; in proper program order.
16644 (define_insn "pro_epilogue_adjust_stack_<mode>_add"
16645 [(set (match_operand:P 0 "register_operand" "=r,r")
16646 (plus:P (match_operand:P 1 "register_operand" "0,r")
16647 (match_operand:P 2 "<nonmemory_operand>" "r<i>,l<i>")))
16648 (clobber (reg:CC FLAGS_REG))
16649 (clobber (mem:BLK (scratch)))]
16652 switch (get_attr_type (insn))
16655 return "mov{<imodesuffix>}\t{%1, %0|%0, %1}";
16658 gcc_assert (rtx_equal_p (operands[0], operands[1]));
16659 if (x86_maybe_negate_const_int (&operands[2], <MODE>mode))
16660 return "sub{<imodesuffix>}\t{%2, %0|%0, %2}";
16662 return "add{<imodesuffix>}\t{%2, %0|%0, %2}";
16665 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
16666 return "lea{<imodesuffix>}\t{%E2, %0|%0, %E2}";
16669 [(set (attr "type")
16670 (cond [(and (eq_attr "alternative" "0")
16671 (not (match_test "TARGET_OPT_AGU")))
16672 (const_string "alu")
16673 (match_operand:<MODE> 2 "const0_operand" "")
16674 (const_string "imov")
16676 (const_string "lea")))
16677 (set (attr "length_immediate")
16678 (cond [(eq_attr "type" "imov")
16680 (and (eq_attr "type" "alu")
16681 (match_operand 2 "const128_operand" ""))
16684 (const_string "*")))
16685 (set_attr "mode" "<MODE>")])
16687 (define_insn "pro_epilogue_adjust_stack_<mode>_sub"
16688 [(set (match_operand:P 0 "register_operand" "=r")
16689 (minus:P (match_operand:P 1 "register_operand" "0")
16690 (match_operand:P 2 "register_operand" "r")))
16691 (clobber (reg:CC FLAGS_REG))
16692 (clobber (mem:BLK (scratch)))]
16694 "sub{<imodesuffix>}\t{%2, %0|%0, %2}"
16695 [(set_attr "type" "alu")
16696 (set_attr "mode" "<MODE>")])
16698 (define_insn "allocate_stack_worker_probe_<mode>"
16699 [(set (match_operand:P 0 "register_operand" "=a")
16700 (unspec_volatile:P [(match_operand:P 1 "register_operand" "0")]
16701 UNSPECV_STACK_PROBE))
16702 (clobber (reg:CC FLAGS_REG))]
16703 "ix86_target_stack_probe ()"
16704 "call\t___chkstk_ms"
16705 [(set_attr "type" "multi")
16706 (set_attr "length" "5")])
16708 (define_expand "allocate_stack"
16709 [(match_operand 0 "register_operand" "")
16710 (match_operand 1 "general_operand" "")]
16711 "ix86_target_stack_probe ()"
16715 #ifndef CHECK_STACK_LIMIT
16716 #define CHECK_STACK_LIMIT 0
16719 if (CHECK_STACK_LIMIT && CONST_INT_P (operands[1])
16720 && INTVAL (operands[1]) < CHECK_STACK_LIMIT)
16722 x = expand_simple_binop (Pmode, MINUS, stack_pointer_rtx, operands[1],
16723 stack_pointer_rtx, 0, OPTAB_DIRECT);
16724 if (x != stack_pointer_rtx)
16725 emit_move_insn (stack_pointer_rtx, x);
16729 x = copy_to_mode_reg (Pmode, operands[1]);
16731 emit_insn (gen_allocate_stack_worker_probe_di (x, x));
16733 emit_insn (gen_allocate_stack_worker_probe_si (x, x));
16734 x = expand_simple_binop (Pmode, MINUS, stack_pointer_rtx, x,
16735 stack_pointer_rtx, 0, OPTAB_DIRECT);
16736 if (x != stack_pointer_rtx)
16737 emit_move_insn (stack_pointer_rtx, x);
16740 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
16744 ;; Use IOR for stack probes, this is shorter.
16745 (define_expand "probe_stack"
16746 [(match_operand 0 "memory_operand" "")]
16749 rtx (*gen_ior3) (rtx, rtx, rtx);
16751 gen_ior3 = (GET_MODE (operands[0]) == DImode
16752 ? gen_iordi3 : gen_iorsi3);
16754 emit_insn (gen_ior3 (operands[0], operands[0], const0_rtx));
16758 (define_insn "adjust_stack_and_probe<mode>"
16759 [(set (match_operand:P 0 "register_operand" "=r")
16760 (unspec_volatile:P [(match_operand:P 1 "register_operand" "0")]
16761 UNSPECV_PROBE_STACK_RANGE))
16762 (set (reg:P SP_REG)
16763 (minus:P (reg:P SP_REG) (match_operand:P 2 "const_int_operand" "n")))
16764 (clobber (reg:CC FLAGS_REG))
16765 (clobber (mem:BLK (scratch)))]
16767 "* return output_adjust_stack_and_probe (operands[0]);"
16768 [(set_attr "type" "multi")])
16770 (define_insn "probe_stack_range<mode>"
16771 [(set (match_operand:P 0 "register_operand" "=r")
16772 (unspec_volatile:P [(match_operand:P 1 "register_operand" "0")
16773 (match_operand:P 2 "const_int_operand" "n")]
16774 UNSPECV_PROBE_STACK_RANGE))
16775 (clobber (reg:CC FLAGS_REG))]
16777 "* return output_probe_stack_range (operands[0], operands[2]);"
16778 [(set_attr "type" "multi")])
16780 (define_expand "builtin_setjmp_receiver"
16781 [(label_ref (match_operand 0 "" ""))]
16782 "!TARGET_64BIT && flag_pic"
16788 rtx picreg = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM);
16789 rtx label_rtx = gen_label_rtx ();
16790 emit_insn (gen_set_got_labelled (pic_offset_table_rtx, label_rtx));
16791 xops[0] = xops[1] = picreg;
16792 xops[2] = machopic_gen_offset (gen_rtx_LABEL_REF (SImode, label_rtx));
16793 ix86_expand_binary_operator (MINUS, SImode, xops);
16797 emit_insn (gen_set_got (pic_offset_table_rtx));
16801 ;; Avoid redundant prefixes by splitting HImode arithmetic to SImode.
16804 [(set (match_operand 0 "register_operand" "")
16805 (match_operator 3 "promotable_binary_operator"
16806 [(match_operand 1 "register_operand" "")
16807 (match_operand 2 "aligned_operand" "")]))
16808 (clobber (reg:CC FLAGS_REG))]
16809 "! TARGET_PARTIAL_REG_STALL && reload_completed
16810 && ((GET_MODE (operands[0]) == HImode
16811 && ((optimize_function_for_speed_p (cfun) && !TARGET_FAST_PREFIX)
16812 /* ??? next two lines just !satisfies_constraint_K (...) */
16813 || !CONST_INT_P (operands[2])
16814 || satisfies_constraint_K (operands[2])))
16815 || (GET_MODE (operands[0]) == QImode
16816 && (TARGET_PROMOTE_QImode || optimize_function_for_size_p (cfun))))"
16817 [(parallel [(set (match_dup 0)
16818 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
16819 (clobber (reg:CC FLAGS_REG))])]
16821 operands[0] = gen_lowpart (SImode, operands[0]);
16822 operands[1] = gen_lowpart (SImode, operands[1]);
16823 if (GET_CODE (operands[3]) != ASHIFT)
16824 operands[2] = gen_lowpart (SImode, operands[2]);
16825 PUT_MODE (operands[3], SImode);
16828 ; Promote the QImode tests, as i386 has encoding of the AND
16829 ; instruction with 32-bit sign-extended immediate and thus the
16830 ; instruction size is unchanged, except in the %eax case for
16831 ; which it is increased by one byte, hence the ! optimize_size.
16833 [(set (match_operand 0 "flags_reg_operand" "")
16834 (match_operator 2 "compare_operator"
16835 [(and (match_operand 3 "aligned_operand" "")
16836 (match_operand 4 "const_int_operand" ""))
16838 (set (match_operand 1 "register_operand" "")
16839 (and (match_dup 3) (match_dup 4)))]
16840 "! TARGET_PARTIAL_REG_STALL && reload_completed
16841 && optimize_insn_for_speed_p ()
16842 && ((GET_MODE (operands[1]) == HImode && ! TARGET_FAST_PREFIX)
16843 || (GET_MODE (operands[1]) == QImode && TARGET_PROMOTE_QImode))
16844 /* Ensure that the operand will remain sign-extended immediate. */
16845 && ix86_match_ccmode (insn, INTVAL (operands[4]) >= 0 ? CCNOmode : CCZmode)"
16846 [(parallel [(set (match_dup 0)
16847 (match_op_dup 2 [(and:SI (match_dup 3) (match_dup 4))
16850 (and:SI (match_dup 3) (match_dup 4)))])]
16853 = gen_int_mode (INTVAL (operands[4])
16854 & GET_MODE_MASK (GET_MODE (operands[1])), SImode);
16855 operands[1] = gen_lowpart (SImode, operands[1]);
16856 operands[3] = gen_lowpart (SImode, operands[3]);
16859 ; Don't promote the QImode tests, as i386 doesn't have encoding of
16860 ; the TEST instruction with 32-bit sign-extended immediate and thus
16861 ; the instruction size would at least double, which is not what we
16862 ; want even with ! optimize_size.
16864 [(set (match_operand 0 "flags_reg_operand" "")
16865 (match_operator 1 "compare_operator"
16866 [(and (match_operand:HI 2 "aligned_operand" "")
16867 (match_operand:HI 3 "const_int_operand" ""))
16869 "! TARGET_PARTIAL_REG_STALL && reload_completed
16870 && ! TARGET_FAST_PREFIX
16871 && optimize_insn_for_speed_p ()
16872 /* Ensure that the operand will remain sign-extended immediate. */
16873 && ix86_match_ccmode (insn, INTVAL (operands[3]) >= 0 ? CCNOmode : CCZmode)"
16874 [(set (match_dup 0)
16875 (match_op_dup 1 [(and:SI (match_dup 2) (match_dup 3))
16879 = gen_int_mode (INTVAL (operands[3])
16880 & GET_MODE_MASK (GET_MODE (operands[2])), SImode);
16881 operands[2] = gen_lowpart (SImode, operands[2]);
16885 [(set (match_operand 0 "register_operand" "")
16886 (neg (match_operand 1 "register_operand" "")))
16887 (clobber (reg:CC FLAGS_REG))]
16888 "! TARGET_PARTIAL_REG_STALL && reload_completed
16889 && (GET_MODE (operands[0]) == HImode
16890 || (GET_MODE (operands[0]) == QImode
16891 && (TARGET_PROMOTE_QImode
16892 || optimize_insn_for_size_p ())))"
16893 [(parallel [(set (match_dup 0)
16894 (neg:SI (match_dup 1)))
16895 (clobber (reg:CC FLAGS_REG))])]
16897 operands[0] = gen_lowpart (SImode, operands[0]);
16898 operands[1] = gen_lowpart (SImode, operands[1]);
16902 [(set (match_operand 0 "register_operand" "")
16903 (not (match_operand 1 "register_operand" "")))]
16904 "! TARGET_PARTIAL_REG_STALL && reload_completed
16905 && (GET_MODE (operands[0]) == HImode
16906 || (GET_MODE (operands[0]) == QImode
16907 && (TARGET_PROMOTE_QImode
16908 || optimize_insn_for_size_p ())))"
16909 [(set (match_dup 0)
16910 (not:SI (match_dup 1)))]
16912 operands[0] = gen_lowpart (SImode, operands[0]);
16913 operands[1] = gen_lowpart (SImode, operands[1]);
16916 ;; RTL Peephole optimizations, run before sched2. These primarily look to
16917 ;; transform a complex memory operation into two memory to register operations.
16919 ;; Don't push memory operands
16921 [(set (match_operand:SWI 0 "push_operand" "")
16922 (match_operand:SWI 1 "memory_operand" ""))
16923 (match_scratch:SWI 2 "<r>")]
16924 "!(TARGET_PUSH_MEMORY || optimize_insn_for_size_p ())
16925 && !RTX_FRAME_RELATED_P (peep2_next_insn (0))"
16926 [(set (match_dup 2) (match_dup 1))
16927 (set (match_dup 0) (match_dup 2))])
16929 ;; We need to handle SFmode only, because DFmode and XFmode are split to
16932 [(set (match_operand:SF 0 "push_operand" "")
16933 (match_operand:SF 1 "memory_operand" ""))
16934 (match_scratch:SF 2 "r")]
16935 "!(TARGET_PUSH_MEMORY || optimize_insn_for_size_p ())
16936 && !RTX_FRAME_RELATED_P (peep2_next_insn (0))"
16937 [(set (match_dup 2) (match_dup 1))
16938 (set (match_dup 0) (match_dup 2))])
16940 ;; Don't move an immediate directly to memory when the instruction
16943 [(match_scratch:SWI124 1 "<r>")
16944 (set (match_operand:SWI124 0 "memory_operand" "")
16946 "optimize_insn_for_speed_p ()
16947 && !TARGET_USE_MOV0
16948 && TARGET_SPLIT_LONG_MOVES
16949 && get_attr_length (insn) >= ix86_cur_cost ()->large_insn
16950 && peep2_regno_dead_p (0, FLAGS_REG)"
16951 [(parallel [(set (match_dup 2) (const_int 0))
16952 (clobber (reg:CC FLAGS_REG))])
16953 (set (match_dup 0) (match_dup 1))]
16954 "operands[2] = gen_lowpart (SImode, operands[1]);")
16957 [(match_scratch:SWI124 2 "<r>")
16958 (set (match_operand:SWI124 0 "memory_operand" "")
16959 (match_operand:SWI124 1 "immediate_operand" ""))]
16960 "optimize_insn_for_speed_p ()
16961 && TARGET_SPLIT_LONG_MOVES
16962 && get_attr_length (insn) >= ix86_cur_cost ()->large_insn"
16963 [(set (match_dup 2) (match_dup 1))
16964 (set (match_dup 0) (match_dup 2))])
16966 ;; Don't compare memory with zero, load and use a test instead.
16968 [(set (match_operand 0 "flags_reg_operand" "")
16969 (match_operator 1 "compare_operator"
16970 [(match_operand:SI 2 "memory_operand" "")
16972 (match_scratch:SI 3 "r")]
16973 "optimize_insn_for_speed_p () && ix86_match_ccmode (insn, CCNOmode)"
16974 [(set (match_dup 3) (match_dup 2))
16975 (set (match_dup 0) (match_op_dup 1 [(match_dup 3) (const_int 0)]))])
16977 ;; NOT is not pairable on Pentium, while XOR is, but one byte longer.
16978 ;; Don't split NOTs with a displacement operand, because resulting XOR
16979 ;; will not be pairable anyway.
16981 ;; On AMD K6, NOT is vector decoded with memory operand that cannot be
16982 ;; represented using a modRM byte. The XOR replacement is long decoded,
16983 ;; so this split helps here as well.
16985 ;; Note: Can't do this as a regular split because we can't get proper
16986 ;; lifetime information then.
16989 [(set (match_operand:SWI124 0 "nonimmediate_operand" "")
16990 (not:SWI124 (match_operand:SWI124 1 "nonimmediate_operand" "")))]
16991 "optimize_insn_for_speed_p ()
16992 && ((TARGET_NOT_UNPAIRABLE
16993 && (!MEM_P (operands[0])
16994 || !memory_displacement_operand (operands[0], <MODE>mode)))
16995 || (TARGET_NOT_VECTORMODE
16996 && long_memory_operand (operands[0], <MODE>mode)))
16997 && peep2_regno_dead_p (0, FLAGS_REG)"
16998 [(parallel [(set (match_dup 0)
16999 (xor:SWI124 (match_dup 1) (const_int -1)))
17000 (clobber (reg:CC FLAGS_REG))])])
17002 ;; Non pairable "test imm, reg" instructions can be translated to
17003 ;; "and imm, reg" if reg dies. The "and" form is also shorter (one
17004 ;; byte opcode instead of two, have a short form for byte operands),
17005 ;; so do it for other CPUs as well. Given that the value was dead,
17006 ;; this should not create any new dependencies. Pass on the sub-word
17007 ;; versions if we're concerned about partial register stalls.
17010 [(set (match_operand 0 "flags_reg_operand" "")
17011 (match_operator 1 "compare_operator"
17012 [(and:SI (match_operand:SI 2 "register_operand" "")
17013 (match_operand:SI 3 "immediate_operand" ""))
17015 "ix86_match_ccmode (insn, CCNOmode)
17016 && (true_regnum (operands[2]) != AX_REG
17017 || satisfies_constraint_K (operands[3]))
17018 && peep2_reg_dead_p (1, operands[2])"
17020 [(set (match_dup 0)
17021 (match_op_dup 1 [(and:SI (match_dup 2) (match_dup 3))
17024 (and:SI (match_dup 2) (match_dup 3)))])])
17026 ;; We don't need to handle HImode case, because it will be promoted to SImode
17027 ;; on ! TARGET_PARTIAL_REG_STALL
17030 [(set (match_operand 0 "flags_reg_operand" "")
17031 (match_operator 1 "compare_operator"
17032 [(and:QI (match_operand:QI 2 "register_operand" "")
17033 (match_operand:QI 3 "immediate_operand" ""))
17035 "! TARGET_PARTIAL_REG_STALL
17036 && ix86_match_ccmode (insn, CCNOmode)
17037 && true_regnum (operands[2]) != AX_REG
17038 && peep2_reg_dead_p (1, operands[2])"
17040 [(set (match_dup 0)
17041 (match_op_dup 1 [(and:QI (match_dup 2) (match_dup 3))
17044 (and:QI (match_dup 2) (match_dup 3)))])])
17047 [(set (match_operand 0 "flags_reg_operand" "")
17048 (match_operator 1 "compare_operator"
17051 (match_operand 2 "ext_register_operand" "")
17054 (match_operand 3 "const_int_operand" ""))
17056 "! TARGET_PARTIAL_REG_STALL
17057 && ix86_match_ccmode (insn, CCNOmode)
17058 && true_regnum (operands[2]) != AX_REG
17059 && peep2_reg_dead_p (1, operands[2])"
17060 [(parallel [(set (match_dup 0)
17069 (set (zero_extract:SI (match_dup 2)
17077 (match_dup 3)))])])
17079 ;; Don't do logical operations with memory inputs.
17081 [(match_scratch:SI 2 "r")
17082 (parallel [(set (match_operand:SI 0 "register_operand" "")
17083 (match_operator:SI 3 "arith_or_logical_operator"
17085 (match_operand:SI 1 "memory_operand" "")]))
17086 (clobber (reg:CC FLAGS_REG))])]
17087 "!(TARGET_READ_MODIFY || optimize_insn_for_size_p ())"
17088 [(set (match_dup 2) (match_dup 1))
17089 (parallel [(set (match_dup 0)
17090 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
17091 (clobber (reg:CC FLAGS_REG))])])
17094 [(match_scratch:SI 2 "r")
17095 (parallel [(set (match_operand:SI 0 "register_operand" "")
17096 (match_operator:SI 3 "arith_or_logical_operator"
17097 [(match_operand:SI 1 "memory_operand" "")
17099 (clobber (reg:CC FLAGS_REG))])]
17100 "!(TARGET_READ_MODIFY || optimize_insn_for_size_p ())"
17101 [(set (match_dup 2) (match_dup 1))
17102 (parallel [(set (match_dup 0)
17103 (match_op_dup 3 [(match_dup 2) (match_dup 0)]))
17104 (clobber (reg:CC FLAGS_REG))])])
17106 ;; Prefer Load+RegOp to Mov+MemOp. Watch out for cases when the memory address
17107 ;; refers to the destination of the load!
17110 [(set (match_operand:SI 0 "register_operand" "")
17111 (match_operand:SI 1 "register_operand" ""))
17112 (parallel [(set (match_dup 0)
17113 (match_operator:SI 3 "commutative_operator"
17115 (match_operand:SI 2 "memory_operand" "")]))
17116 (clobber (reg:CC FLAGS_REG))])]
17117 "REGNO (operands[0]) != REGNO (operands[1])
17118 && GENERAL_REGNO_P (REGNO (operands[0]))
17119 && GENERAL_REGNO_P (REGNO (operands[1]))"
17120 [(set (match_dup 0) (match_dup 4))
17121 (parallel [(set (match_dup 0)
17122 (match_op_dup 3 [(match_dup 0) (match_dup 1)]))
17123 (clobber (reg:CC FLAGS_REG))])]
17124 "operands[4] = replace_rtx (operands[2], operands[0], operands[1]);")
17127 [(set (match_operand 0 "register_operand" "")
17128 (match_operand 1 "register_operand" ""))
17130 (match_operator 3 "commutative_operator"
17132 (match_operand 2 "memory_operand" "")]))]
17133 "REGNO (operands[0]) != REGNO (operands[1])
17134 && ((MMX_REG_P (operands[0]) && MMX_REG_P (operands[1]))
17135 || (SSE_REG_P (operands[0]) && SSE_REG_P (operands[1])))"
17136 [(set (match_dup 0) (match_dup 2))
17138 (match_op_dup 3 [(match_dup 0) (match_dup 1)]))])
17140 ; Don't do logical operations with memory outputs
17142 ; These two don't make sense for PPro/PII -- we're expanding a 4-uop
17143 ; instruction into two 1-uop insns plus a 2-uop insn. That last has
17144 ; the same decoder scheduling characteristics as the original.
17147 [(match_scratch:SI 2 "r")
17148 (parallel [(set (match_operand:SI 0 "memory_operand" "")
17149 (match_operator:SI 3 "arith_or_logical_operator"
17151 (match_operand:SI 1 "nonmemory_operand" "")]))
17152 (clobber (reg:CC FLAGS_REG))])]
17153 "!(TARGET_READ_MODIFY_WRITE || optimize_insn_for_size_p ())
17154 /* Do not split stack checking probes. */
17155 && GET_CODE (operands[3]) != IOR && operands[1] != const0_rtx"
17156 [(set (match_dup 2) (match_dup 0))
17157 (parallel [(set (match_dup 2)
17158 (match_op_dup 3 [(match_dup 2) (match_dup 1)]))
17159 (clobber (reg:CC FLAGS_REG))])
17160 (set (match_dup 0) (match_dup 2))])
17163 [(match_scratch:SI 2 "r")
17164 (parallel [(set (match_operand:SI 0 "memory_operand" "")
17165 (match_operator:SI 3 "arith_or_logical_operator"
17166 [(match_operand:SI 1 "nonmemory_operand" "")
17168 (clobber (reg:CC FLAGS_REG))])]
17169 "!(TARGET_READ_MODIFY_WRITE || optimize_insn_for_size_p ())
17170 /* Do not split stack checking probes. */
17171 && GET_CODE (operands[3]) != IOR && operands[1] != const0_rtx"
17172 [(set (match_dup 2) (match_dup 0))
17173 (parallel [(set (match_dup 2)
17174 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
17175 (clobber (reg:CC FLAGS_REG))])
17176 (set (match_dup 0) (match_dup 2))])
17178 ;; Attempt to use arith or logical operations with memory outputs with
17179 ;; setting of flags.
17181 [(set (match_operand:SWI 0 "register_operand" "")
17182 (match_operand:SWI 1 "memory_operand" ""))
17183 (parallel [(set (match_dup 0)
17184 (match_operator:SWI 3 "plusminuslogic_operator"
17186 (match_operand:SWI 2 "<nonmemory_operand>" "")]))
17187 (clobber (reg:CC FLAGS_REG))])
17188 (set (match_dup 1) (match_dup 0))
17189 (set (reg FLAGS_REG) (compare (match_dup 0) (const_int 0)))]
17190 "(TARGET_READ_MODIFY_WRITE || optimize_insn_for_size_p ())
17191 && peep2_reg_dead_p (4, operands[0])
17192 && !reg_overlap_mentioned_p (operands[0], operands[1])
17193 && (<MODE>mode != QImode
17194 || immediate_operand (operands[2], QImode)
17195 || q_regs_operand (operands[2], QImode))
17196 && ix86_match_ccmode (peep2_next_insn (3),
17197 (GET_CODE (operands[3]) == PLUS
17198 || GET_CODE (operands[3]) == MINUS)
17199 ? CCGOCmode : CCNOmode)"
17200 [(parallel [(set (match_dup 4) (match_dup 5))
17201 (set (match_dup 1) (match_op_dup 3 [(match_dup 1)
17202 (match_dup 2)]))])]
17204 operands[4] = SET_DEST (PATTERN (peep2_next_insn (3)));
17205 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), <MODE>mode,
17206 copy_rtx (operands[1]),
17207 copy_rtx (operands[2]));
17208 operands[5] = gen_rtx_COMPARE (GET_MODE (operands[4]),
17209 operands[5], const0_rtx);
17213 [(parallel [(set (match_operand:SWI 0 "register_operand" "")
17214 (match_operator:SWI 2 "plusminuslogic_operator"
17216 (match_operand:SWI 1 "memory_operand" "")]))
17217 (clobber (reg:CC FLAGS_REG))])
17218 (set (match_dup 1) (match_dup 0))
17219 (set (reg FLAGS_REG) (compare (match_dup 0) (const_int 0)))]
17220 "(TARGET_READ_MODIFY_WRITE || optimize_insn_for_size_p ())
17221 && GET_CODE (operands[2]) != MINUS
17222 && peep2_reg_dead_p (3, operands[0])
17223 && !reg_overlap_mentioned_p (operands[0], operands[1])
17224 && ix86_match_ccmode (peep2_next_insn (2),
17225 GET_CODE (operands[2]) == PLUS
17226 ? CCGOCmode : CCNOmode)"
17227 [(parallel [(set (match_dup 3) (match_dup 4))
17228 (set (match_dup 1) (match_op_dup 2 [(match_dup 1)
17229 (match_dup 0)]))])]
17231 operands[3] = SET_DEST (PATTERN (peep2_next_insn (2)));
17232 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[2]), <MODE>mode,
17233 copy_rtx (operands[1]),
17234 copy_rtx (operands[0]));
17235 operands[4] = gen_rtx_COMPARE (GET_MODE (operands[3]),
17236 operands[4], const0_rtx);
17240 [(set (match_operand:SWI12 0 "register_operand" "")
17241 (match_operand:SWI12 1 "memory_operand" ""))
17242 (parallel [(set (match_operand:SI 4 "register_operand" "")
17243 (match_operator:SI 3 "plusminuslogic_operator"
17245 (match_operand:SI 2 "nonmemory_operand" "")]))
17246 (clobber (reg:CC FLAGS_REG))])
17247 (set (match_dup 1) (match_dup 0))
17248 (set (reg FLAGS_REG) (compare (match_dup 0) (const_int 0)))]
17249 "(TARGET_READ_MODIFY_WRITE || optimize_insn_for_size_p ())
17250 && REG_P (operands[0]) && REG_P (operands[4])
17251 && REGNO (operands[0]) == REGNO (operands[4])
17252 && peep2_reg_dead_p (4, operands[0])
17253 && (<MODE>mode != QImode
17254 || immediate_operand (operands[2], SImode)
17255 || q_regs_operand (operands[2], SImode))
17256 && !reg_overlap_mentioned_p (operands[0], operands[1])
17257 && ix86_match_ccmode (peep2_next_insn (3),
17258 (GET_CODE (operands[3]) == PLUS
17259 || GET_CODE (operands[3]) == MINUS)
17260 ? CCGOCmode : CCNOmode)"
17261 [(parallel [(set (match_dup 4) (match_dup 5))
17262 (set (match_dup 1) (match_dup 6))])]
17264 operands[2] = gen_lowpart (<MODE>mode, operands[2]);
17265 operands[4] = SET_DEST (PATTERN (peep2_next_insn (3)));
17266 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), <MODE>mode,
17267 copy_rtx (operands[1]), operands[2]);
17268 operands[5] = gen_rtx_COMPARE (GET_MODE (operands[4]),
17269 operands[5], const0_rtx);
17270 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[3]), <MODE>mode,
17271 copy_rtx (operands[1]),
17272 copy_rtx (operands[2]));
17275 ;; Attempt to always use XOR for zeroing registers.
17277 [(set (match_operand 0 "register_operand" "")
17278 (match_operand 1 "const0_operand" ""))]
17279 "GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
17280 && (! TARGET_USE_MOV0 || optimize_insn_for_size_p ())
17281 && GENERAL_REG_P (operands[0])
17282 && peep2_regno_dead_p (0, FLAGS_REG)"
17283 [(parallel [(set (match_dup 0) (const_int 0))
17284 (clobber (reg:CC FLAGS_REG))])]
17285 "operands[0] = gen_lowpart (word_mode, operands[0]);")
17288 [(set (strict_low_part (match_operand 0 "register_operand" ""))
17290 "(GET_MODE (operands[0]) == QImode
17291 || GET_MODE (operands[0]) == HImode)
17292 && (! TARGET_USE_MOV0 || optimize_insn_for_size_p ())
17293 && peep2_regno_dead_p (0, FLAGS_REG)"
17294 [(parallel [(set (strict_low_part (match_dup 0)) (const_int 0))
17295 (clobber (reg:CC FLAGS_REG))])])
17297 ;; For HI, SI and DI modes, or $-1,reg is smaller than mov $-1,reg.
17299 [(set (match_operand:SWI248 0 "register_operand" "")
17301 "(optimize_insn_for_size_p () || TARGET_MOVE_M1_VIA_OR)
17302 && peep2_regno_dead_p (0, FLAGS_REG)"
17303 [(parallel [(set (match_dup 0) (const_int -1))
17304 (clobber (reg:CC FLAGS_REG))])]
17306 if (GET_MODE_SIZE (<MODE>mode) < GET_MODE_SIZE (SImode))
17307 operands[0] = gen_lowpart (SImode, operands[0]);
17310 ;; Attempt to convert simple lea to add/shift.
17311 ;; These can be created by move expanders.
17314 [(set (match_operand:SWI48 0 "register_operand" "")
17315 (plus:SWI48 (match_dup 0)
17316 (match_operand:SWI48 1 "<nonmemory_operand>" "")))]
17317 "peep2_regno_dead_p (0, FLAGS_REG)"
17318 [(parallel [(set (match_dup 0) (plus:SWI48 (match_dup 0) (match_dup 1)))
17319 (clobber (reg:CC FLAGS_REG))])])
17322 [(set (match_operand:SI 0 "register_operand" "")
17323 (subreg:SI (plus:DI (match_operand:DI 1 "register_operand" "")
17324 (match_operand:DI 2 "nonmemory_operand" "")) 0))]
17326 && peep2_regno_dead_p (0, FLAGS_REG)
17327 && REGNO (operands[0]) == REGNO (operands[1])"
17328 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
17329 (clobber (reg:CC FLAGS_REG))])]
17330 "operands[2] = gen_lowpart (SImode, operands[2]);")
17333 [(set (match_operand:SWI48 0 "register_operand" "")
17334 (mult:SWI48 (match_dup 0)
17335 (match_operand:SWI48 1 "const_int_operand" "")))]
17336 "exact_log2 (INTVAL (operands[1])) >= 0
17337 && peep2_regno_dead_p (0, FLAGS_REG)"
17338 [(parallel [(set (match_dup 0) (ashift:SWI48 (match_dup 0) (match_dup 2)))
17339 (clobber (reg:CC FLAGS_REG))])]
17340 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
17343 [(set (match_operand:SI 0 "register_operand" "")
17344 (subreg:SI (mult:DI (match_operand:DI 1 "register_operand" "")
17345 (match_operand:DI 2 "const_int_operand" "")) 0))]
17347 && exact_log2 (INTVAL (operands[2])) >= 0
17348 && REGNO (operands[0]) == REGNO (operands[1])
17349 && peep2_regno_dead_p (0, FLAGS_REG)"
17350 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
17351 (clobber (reg:CC FLAGS_REG))])]
17352 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));")
17354 ;; The ESP adjustments can be done by the push and pop instructions. Resulting
17355 ;; code is shorter, since push is only 1 byte, while add imm, %esp is 3 bytes.
17356 ;; On many CPUs it is also faster, since special hardware to avoid esp
17357 ;; dependencies is present.
17359 ;; While some of these conversions may be done using splitters, we use
17360 ;; peepholes in order to allow combine_stack_adjustments pass to see
17361 ;; nonobfuscated RTL.
17363 ;; Convert prologue esp subtractions to push.
17364 ;; We need register to push. In order to keep verify_flow_info happy we have
17366 ;; - use scratch and clobber it in order to avoid dependencies
17367 ;; - use already live register
17368 ;; We can't use the second way right now, since there is no reliable way how to
17369 ;; verify that given register is live. First choice will also most likely in
17370 ;; fewer dependencies. On the place of esp adjustments it is very likely that
17371 ;; call clobbered registers are dead. We may want to use base pointer as an
17372 ;; alternative when no register is available later.
17375 [(match_scratch:P 1 "r")
17376 (parallel [(set (reg:P SP_REG)
17377 (plus:P (reg:P SP_REG)
17378 (match_operand:P 0 "const_int_operand" "")))
17379 (clobber (reg:CC FLAGS_REG))
17380 (clobber (mem:BLK (scratch)))])]
17381 "(TARGET_SINGLE_PUSH || optimize_insn_for_size_p ())
17382 && INTVAL (operands[0]) == -GET_MODE_SIZE (Pmode)"
17383 [(clobber (match_dup 1))
17384 (parallel [(set (mem:P (pre_dec:P (reg:P SP_REG))) (match_dup 1))
17385 (clobber (mem:BLK (scratch)))])])
17388 [(match_scratch:P 1 "r")
17389 (parallel [(set (reg:P SP_REG)
17390 (plus:P (reg:P SP_REG)
17391 (match_operand:P 0 "const_int_operand" "")))
17392 (clobber (reg:CC FLAGS_REG))
17393 (clobber (mem:BLK (scratch)))])]
17394 "(TARGET_DOUBLE_PUSH || optimize_insn_for_size_p ())
17395 && INTVAL (operands[0]) == -2*GET_MODE_SIZE (Pmode)"
17396 [(clobber (match_dup 1))
17397 (set (mem:P (pre_dec:P (reg:P SP_REG))) (match_dup 1))
17398 (parallel [(set (mem:P (pre_dec:P (reg:P SP_REG))) (match_dup 1))
17399 (clobber (mem:BLK (scratch)))])])
17401 ;; Convert esp subtractions to push.
17403 [(match_scratch:P 1 "r")
17404 (parallel [(set (reg:P SP_REG)
17405 (plus:P (reg:P SP_REG)
17406 (match_operand:P 0 "const_int_operand" "")))
17407 (clobber (reg:CC FLAGS_REG))])]
17408 "(TARGET_SINGLE_PUSH || optimize_insn_for_size_p ())
17409 && INTVAL (operands[0]) == -GET_MODE_SIZE (Pmode)"
17410 [(clobber (match_dup 1))
17411 (set (mem:P (pre_dec:P (reg:P SP_REG))) (match_dup 1))])
17414 [(match_scratch:P 1 "r")
17415 (parallel [(set (reg:P SP_REG)
17416 (plus:P (reg:P SP_REG)
17417 (match_operand:P 0 "const_int_operand" "")))
17418 (clobber (reg:CC FLAGS_REG))])]
17419 "(TARGET_DOUBLE_PUSH || optimize_insn_for_size_p ())
17420 && INTVAL (operands[0]) == -2*GET_MODE_SIZE (Pmode)"
17421 [(clobber (match_dup 1))
17422 (set (mem:P (pre_dec:P (reg:P SP_REG))) (match_dup 1))
17423 (set (mem:P (pre_dec:P (reg:P SP_REG))) (match_dup 1))])
17425 ;; Convert epilogue deallocator to pop.
17427 [(match_scratch:P 1 "r")
17428 (parallel [(set (reg:P SP_REG)
17429 (plus:P (reg:P SP_REG)
17430 (match_operand:P 0 "const_int_operand" "")))
17431 (clobber (reg:CC FLAGS_REG))
17432 (clobber (mem:BLK (scratch)))])]
17433 "(TARGET_SINGLE_POP || optimize_insn_for_size_p ())
17434 && INTVAL (operands[0]) == GET_MODE_SIZE (Pmode)"
17435 [(parallel [(set (match_dup 1) (mem:P (post_inc:P (reg:P SP_REG))))
17436 (clobber (mem:BLK (scratch)))])])
17438 ;; Two pops case is tricky, since pop causes dependency
17439 ;; on destination register. We use two registers if available.
17441 [(match_scratch:P 1 "r")
17442 (match_scratch:P 2 "r")
17443 (parallel [(set (reg:P SP_REG)
17444 (plus:P (reg:P SP_REG)
17445 (match_operand:P 0 "const_int_operand" "")))
17446 (clobber (reg:CC FLAGS_REG))
17447 (clobber (mem:BLK (scratch)))])]
17448 "(TARGET_DOUBLE_POP || optimize_insn_for_size_p ())
17449 && INTVAL (operands[0]) == 2*GET_MODE_SIZE (Pmode)"
17450 [(parallel [(set (match_dup 1) (mem:P (post_inc:P (reg:P SP_REG))))
17451 (clobber (mem:BLK (scratch)))])
17452 (set (match_dup 2) (mem:P (post_inc:P (reg:P SP_REG))))])
17455 [(match_scratch:P 1 "r")
17456 (parallel [(set (reg:P SP_REG)
17457 (plus:P (reg:P SP_REG)
17458 (match_operand:P 0 "const_int_operand" "")))
17459 (clobber (reg:CC FLAGS_REG))
17460 (clobber (mem:BLK (scratch)))])]
17461 "optimize_insn_for_size_p ()
17462 && INTVAL (operands[0]) == 2*GET_MODE_SIZE (Pmode)"
17463 [(parallel [(set (match_dup 1) (mem:P (post_inc:P (reg:P SP_REG))))
17464 (clobber (mem:BLK (scratch)))])
17465 (set (match_dup 1) (mem:P (post_inc:P (reg:P SP_REG))))])
17467 ;; Convert esp additions to pop.
17469 [(match_scratch:P 1 "r")
17470 (parallel [(set (reg:P SP_REG)
17471 (plus:P (reg:P SP_REG)
17472 (match_operand:P 0 "const_int_operand" "")))
17473 (clobber (reg:CC FLAGS_REG))])]
17474 "INTVAL (operands[0]) == GET_MODE_SIZE (Pmode)"
17475 [(set (match_dup 1) (mem:P (post_inc:P (reg:P SP_REG))))])
17477 ;; Two pops case is tricky, since pop causes dependency
17478 ;; on destination register. We use two registers if available.
17480 [(match_scratch:P 1 "r")
17481 (match_scratch:P 2 "r")
17482 (parallel [(set (reg:P SP_REG)
17483 (plus:P (reg:P SP_REG)
17484 (match_operand:P 0 "const_int_operand" "")))
17485 (clobber (reg:CC FLAGS_REG))])]
17486 "INTVAL (operands[0]) == 2*GET_MODE_SIZE (Pmode)"
17487 [(set (match_dup 1) (mem:P (post_inc:P (reg:P SP_REG))))
17488 (set (match_dup 2) (mem:P (post_inc:P (reg:P SP_REG))))])
17491 [(match_scratch:P 1 "r")
17492 (parallel [(set (reg:P SP_REG)
17493 (plus:P (reg:P SP_REG)
17494 (match_operand:P 0 "const_int_operand" "")))
17495 (clobber (reg:CC FLAGS_REG))])]
17496 "optimize_insn_for_size_p ()
17497 && INTVAL (operands[0]) == 2*GET_MODE_SIZE (Pmode)"
17498 [(set (match_dup 1) (mem:P (post_inc:P (reg:P SP_REG))))
17499 (set (match_dup 1) (mem:P (post_inc:P (reg:P SP_REG))))])
17501 ;; Convert compares with 1 to shorter inc/dec operations when CF is not
17502 ;; required and register dies. Similarly for 128 to -128.
17504 [(set (match_operand 0 "flags_reg_operand" "")
17505 (match_operator 1 "compare_operator"
17506 [(match_operand 2 "register_operand" "")
17507 (match_operand 3 "const_int_operand" "")]))]
17508 "(((!TARGET_FUSE_CMP_AND_BRANCH || optimize_insn_for_size_p ())
17509 && incdec_operand (operands[3], GET_MODE (operands[3])))
17510 || (!TARGET_FUSE_CMP_AND_BRANCH
17511 && INTVAL (operands[3]) == 128))
17512 && ix86_match_ccmode (insn, CCGCmode)
17513 && peep2_reg_dead_p (1, operands[2])"
17514 [(parallel [(set (match_dup 0)
17515 (match_op_dup 1 [(match_dup 2) (match_dup 3)]))
17516 (clobber (match_dup 2))])])
17518 ;; Convert imul by three, five and nine into lea
17521 [(set (match_operand:SWI48 0 "register_operand" "")
17522 (mult:SWI48 (match_operand:SWI48 1 "register_operand" "")
17523 (match_operand:SWI48 2 "const359_operand" "")))
17524 (clobber (reg:CC FLAGS_REG))])]
17525 "!TARGET_PARTIAL_REG_STALL
17526 || <MODE>mode == SImode
17527 || optimize_function_for_size_p (cfun)"
17528 [(set (match_dup 0)
17529 (plus:SWI48 (mult:SWI48 (match_dup 1) (match_dup 2))
17531 "operands[2] = GEN_INT (INTVAL (operands[2]) - 1);")
17535 [(set (match_operand:SWI48 0 "register_operand" "")
17536 (mult:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "")
17537 (match_operand:SWI48 2 "const359_operand" "")))
17538 (clobber (reg:CC FLAGS_REG))])]
17539 "optimize_insn_for_speed_p ()
17540 && (!TARGET_PARTIAL_REG_STALL || <MODE>mode == SImode)"
17541 [(set (match_dup 0) (match_dup 1))
17543 (plus:SWI48 (mult:SWI48 (match_dup 0) (match_dup 2))
17545 "operands[2] = GEN_INT (INTVAL (operands[2]) - 1);")
17547 ;; imul $32bit_imm, mem, reg is vector decoded, while
17548 ;; imul $32bit_imm, reg, reg is direct decoded.
17550 [(match_scratch:SWI48 3 "r")
17551 (parallel [(set (match_operand:SWI48 0 "register_operand" "")
17552 (mult:SWI48 (match_operand:SWI48 1 "memory_operand" "")
17553 (match_operand:SWI48 2 "immediate_operand" "")))
17554 (clobber (reg:CC FLAGS_REG))])]
17555 "TARGET_SLOW_IMUL_IMM32_MEM && optimize_insn_for_speed_p ()
17556 && !satisfies_constraint_K (operands[2])"
17557 [(set (match_dup 3) (match_dup 1))
17558 (parallel [(set (match_dup 0) (mult:SWI48 (match_dup 3) (match_dup 2)))
17559 (clobber (reg:CC FLAGS_REG))])])
17562 [(match_scratch:SI 3 "r")
17563 (parallel [(set (match_operand:DI 0 "register_operand" "")
17565 (mult:SI (match_operand:SI 1 "memory_operand" "")
17566 (match_operand:SI 2 "immediate_operand" ""))))
17567 (clobber (reg:CC FLAGS_REG))])]
17569 && TARGET_SLOW_IMUL_IMM32_MEM && optimize_insn_for_speed_p ()
17570 && !satisfies_constraint_K (operands[2])"
17571 [(set (match_dup 3) (match_dup 1))
17572 (parallel [(set (match_dup 0)
17573 (zero_extend:DI (mult:SI (match_dup 3) (match_dup 2))))
17574 (clobber (reg:CC FLAGS_REG))])])
17576 ;; imul $8/16bit_imm, regmem, reg is vector decoded.
17577 ;; Convert it into imul reg, reg
17578 ;; It would be better to force assembler to encode instruction using long
17579 ;; immediate, but there is apparently no way to do so.
17581 [(parallel [(set (match_operand:SWI248 0 "register_operand" "")
17583 (match_operand:SWI248 1 "nonimmediate_operand" "")
17584 (match_operand:SWI248 2 "const_int_operand" "")))
17585 (clobber (reg:CC FLAGS_REG))])
17586 (match_scratch:SWI248 3 "r")]
17587 "TARGET_SLOW_IMUL_IMM8 && optimize_insn_for_speed_p ()
17588 && satisfies_constraint_K (operands[2])"
17589 [(set (match_dup 3) (match_dup 2))
17590 (parallel [(set (match_dup 0) (mult:SWI248 (match_dup 0) (match_dup 3)))
17591 (clobber (reg:CC FLAGS_REG))])]
17593 if (!rtx_equal_p (operands[0], operands[1]))
17594 emit_move_insn (operands[0], operands[1]);
17597 ;; After splitting up read-modify operations, array accesses with memory
17598 ;; operands might end up in form:
17600 ;; movl 4(%esp), %edx
17602 ;; instead of pre-splitting:
17604 ;; addl 4(%esp), %eax
17606 ;; movl 4(%esp), %edx
17607 ;; leal (%edx,%eax,4), %eax
17610 [(match_scratch:P 5 "r")
17611 (parallel [(set (match_operand 0 "register_operand" "")
17612 (ashift (match_operand 1 "register_operand" "")
17613 (match_operand 2 "const_int_operand" "")))
17614 (clobber (reg:CC FLAGS_REG))])
17615 (parallel [(set (match_operand 3 "register_operand" "")
17616 (plus (match_dup 0)
17617 (match_operand 4 "x86_64_general_operand" "")))
17618 (clobber (reg:CC FLAGS_REG))])]
17619 "IN_RANGE (INTVAL (operands[2]), 1, 3)
17620 /* Validate MODE for lea. */
17621 && ((!TARGET_PARTIAL_REG_STALL
17622 && (GET_MODE (operands[0]) == QImode
17623 || GET_MODE (operands[0]) == HImode))
17624 || GET_MODE (operands[0]) == SImode
17625 || (TARGET_64BIT && GET_MODE (operands[0]) == DImode))
17626 && (rtx_equal_p (operands[0], operands[3])
17627 || peep2_reg_dead_p (2, operands[0]))
17628 /* We reorder load and the shift. */
17629 && !reg_overlap_mentioned_p (operands[0], operands[4])"
17630 [(set (match_dup 5) (match_dup 4))
17631 (set (match_dup 0) (match_dup 1))]
17633 enum machine_mode op1mode = GET_MODE (operands[1]);
17634 enum machine_mode mode = op1mode == DImode ? DImode : SImode;
17635 int scale = 1 << INTVAL (operands[2]);
17636 rtx index = gen_lowpart (Pmode, operands[1]);
17637 rtx base = gen_lowpart (Pmode, operands[5]);
17638 rtx dest = gen_lowpart (mode, operands[3]);
17640 operands[1] = gen_rtx_PLUS (Pmode, base,
17641 gen_rtx_MULT (Pmode, index, GEN_INT (scale)));
17642 operands[5] = base;
17644 operands[1] = gen_rtx_SUBREG (mode, operands[1], 0);
17645 if (op1mode != Pmode)
17646 operands[5] = gen_rtx_SUBREG (op1mode, operands[5], 0);
17647 operands[0] = dest;
17650 ;; We used to use "int $5", in honor of #BR which maps to interrupt vector 5.
17651 ;; That, however, is usually mapped by the OS to SIGSEGV, which is often
17652 ;; caught for use by garbage collectors and the like. Using an insn that
17653 ;; maps to SIGILL makes it more likely the program will rightfully die.
17654 ;; Keeping with tradition, "6" is in honor of #UD.
17655 (define_insn "trap"
17656 [(trap_if (const_int 1) (const_int 6))]
17658 { return ASM_SHORT "0x0b0f"; }
17659 [(set_attr "length" "2")])
17661 (define_expand "prefetch"
17662 [(prefetch (match_operand 0 "address_operand" "")
17663 (match_operand:SI 1 "const_int_operand" "")
17664 (match_operand:SI 2 "const_int_operand" ""))]
17665 "TARGET_PREFETCH_SSE || TARGET_3DNOW"
17667 int rw = INTVAL (operands[1]);
17668 int locality = INTVAL (operands[2]);
17670 gcc_assert (rw == 0 || rw == 1);
17671 gcc_assert (IN_RANGE (locality, 0, 3));
17673 if (TARGET_PREFETCHW && rw)
17674 operands[2] = GEN_INT (3);
17675 /* Use 3dNOW prefetch in case we are asking for write prefetch not
17676 supported by SSE counterpart or the SSE prefetch is not available
17677 (K6 machines). Otherwise use SSE prefetch as it allows specifying
17679 else if (TARGET_3DNOW && (!TARGET_PREFETCH_SSE || rw))
17680 operands[2] = GEN_INT (3);
17682 operands[1] = const0_rtx;
17685 (define_insn "*prefetch_sse"
17686 [(prefetch (match_operand 0 "address_operand" "p")
17688 (match_operand:SI 1 "const_int_operand" ""))]
17689 "TARGET_PREFETCH_SSE"
17691 static const char * const patterns[4] = {
17692 "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0"
17695 int locality = INTVAL (operands[1]);
17696 gcc_assert (IN_RANGE (locality, 0, 3));
17698 return patterns[locality];
17700 [(set_attr "type" "sse")
17701 (set_attr "atom_sse_attr" "prefetch")
17702 (set (attr "length_address")
17703 (symbol_ref "memory_address_length (operands[0], false)"))
17704 (set_attr "memory" "none")])
17706 (define_insn "*prefetch_3dnow"
17707 [(prefetch (match_operand 0 "address_operand" "p")
17708 (match_operand:SI 1 "const_int_operand" "n")
17710 "TARGET_3DNOW || TARGET_PREFETCHW"
17712 if (INTVAL (operands[1]) == 0)
17713 return "prefetch\t%a0";
17715 return "prefetchw\t%a0";
17717 [(set_attr "type" "mmx")
17718 (set (attr "length_address")
17719 (symbol_ref "memory_address_length (operands[0], false)"))
17720 (set_attr "memory" "none")])
17722 (define_expand "stack_protect_set"
17723 [(match_operand 0 "memory_operand" "")
17724 (match_operand 1 "memory_operand" "")]
17725 "!TARGET_HAS_BIONIC"
17727 rtx (*insn)(rtx, rtx);
17729 #ifdef TARGET_THREAD_SSP_OFFSET
17730 operands[1] = GEN_INT (TARGET_THREAD_SSP_OFFSET);
17731 insn = (TARGET_LP64
17732 ? gen_stack_tls_protect_set_di
17733 : gen_stack_tls_protect_set_si);
17735 insn = (TARGET_LP64
17736 ? gen_stack_protect_set_di
17737 : gen_stack_protect_set_si);
17740 emit_insn (insn (operands[0], operands[1]));
17744 (define_insn "stack_protect_set_<mode>"
17745 [(set (match_operand:PTR 0 "memory_operand" "=m")
17746 (unspec:PTR [(match_operand:PTR 1 "memory_operand" "m")]
17748 (set (match_scratch:PTR 2 "=&r") (const_int 0))
17749 (clobber (reg:CC FLAGS_REG))]
17750 "!TARGET_HAS_BIONIC"
17751 "mov{<imodesuffix>}\t{%1, %2|%2, %1}\;mov{<imodesuffix>}\t{%2, %0|%0, %2}\;xor{l}\t%k2, %k2"
17752 [(set_attr "type" "multi")])
17754 (define_insn "stack_tls_protect_set_<mode>"
17755 [(set (match_operand:PTR 0 "memory_operand" "=m")
17756 (unspec:PTR [(match_operand:PTR 1 "const_int_operand" "i")]
17757 UNSPEC_SP_TLS_SET))
17758 (set (match_scratch:PTR 2 "=&r") (const_int 0))
17759 (clobber (reg:CC FLAGS_REG))]
17761 "mov{<imodesuffix>}\t{%@:%P1, %2|%2, <iptrsize> PTR %@:%P1}\;mov{<imodesuffix>}\t{%2, %0|%0, %2}\;xor{l}\t%k2, %k2"
17762 [(set_attr "type" "multi")])
17764 (define_expand "stack_protect_test"
17765 [(match_operand 0 "memory_operand" "")
17766 (match_operand 1 "memory_operand" "")
17767 (match_operand 2 "" "")]
17768 "!TARGET_HAS_BIONIC"
17770 rtx flags = gen_rtx_REG (CCZmode, FLAGS_REG);
17772 rtx (*insn)(rtx, rtx, rtx);
17774 #ifdef TARGET_THREAD_SSP_OFFSET
17775 operands[1] = GEN_INT (TARGET_THREAD_SSP_OFFSET);
17776 insn = (TARGET_LP64
17777 ? gen_stack_tls_protect_test_di
17778 : gen_stack_tls_protect_test_si);
17780 insn = (TARGET_LP64
17781 ? gen_stack_protect_test_di
17782 : gen_stack_protect_test_si);
17785 emit_insn (insn (flags, operands[0], operands[1]));
17787 emit_jump_insn (gen_cbranchcc4 (gen_rtx_EQ (VOIDmode, flags, const0_rtx),
17788 flags, const0_rtx, operands[2]));
17792 (define_insn "stack_protect_test_<mode>"
17793 [(set (match_operand:CCZ 0 "flags_reg_operand" "")
17794 (unspec:CCZ [(match_operand:PTR 1 "memory_operand" "m")
17795 (match_operand:PTR 2 "memory_operand" "m")]
17797 (clobber (match_scratch:PTR 3 "=&r"))]
17798 "!TARGET_HAS_BIONIC"
17799 "mov{<imodesuffix>}\t{%1, %3|%3, %1}\;xor{<imodesuffix>}\t{%2, %3|%3, %2}"
17800 [(set_attr "type" "multi")])
17802 (define_insn "stack_tls_protect_test_<mode>"
17803 [(set (match_operand:CCZ 0 "flags_reg_operand" "")
17804 (unspec:CCZ [(match_operand:PTR 1 "memory_operand" "m")
17805 (match_operand:PTR 2 "const_int_operand" "i")]
17806 UNSPEC_SP_TLS_TEST))
17807 (clobber (match_scratch:PTR 3 "=r"))]
17809 "mov{<imodesuffix>}\t{%1, %3|%3, %1}\;xor{<imodesuffix>}\t{%@:%P2, %3|%3, <iptrsize> PTR %@:%P2}"
17810 [(set_attr "type" "multi")])
17812 (define_insn "sse4_2_crc32<mode>"
17813 [(set (match_operand:SI 0 "register_operand" "=r")
17815 [(match_operand:SI 1 "register_operand" "0")
17816 (match_operand:SWI124 2 "nonimmediate_operand" "<r>m")]
17818 "TARGET_SSE4_2 || TARGET_CRC32"
17819 "crc32{<imodesuffix>}\t{%2, %0|%0, %2}"
17820 [(set_attr "type" "sselog1")
17821 (set_attr "prefix_rep" "1")
17822 (set_attr "prefix_extra" "1")
17823 (set (attr "prefix_data16")
17824 (if_then_else (match_operand:HI 2 "" "")
17826 (const_string "*")))
17827 (set (attr "prefix_rex")
17828 (if_then_else (match_operand:QI 2 "ext_QIreg_operand" "")
17830 (const_string "*")))
17831 (set_attr "mode" "SI")])
17833 (define_insn "sse4_2_crc32di"
17834 [(set (match_operand:DI 0 "register_operand" "=r")
17836 [(match_operand:DI 1 "register_operand" "0")
17837 (match_operand:DI 2 "nonimmediate_operand" "rm")]
17839 "TARGET_64BIT && (TARGET_SSE4_2 || TARGET_CRC32)"
17840 "crc32{q}\t{%2, %0|%0, %2}"
17841 [(set_attr "type" "sselog1")
17842 (set_attr "prefix_rep" "1")
17843 (set_attr "prefix_extra" "1")
17844 (set_attr "mode" "DI")])
17846 (define_expand "rdpmc"
17847 [(match_operand:DI 0 "register_operand" "")
17848 (match_operand:SI 1 "register_operand" "")]
17851 rtx reg = gen_reg_rtx (DImode);
17854 /* Force operand 1 into ECX. */
17855 rtx ecx = gen_rtx_REG (SImode, CX_REG);
17856 emit_insn (gen_rtx_SET (VOIDmode, ecx, operands[1]));
17857 si = gen_rtx_UNSPEC_VOLATILE (DImode, gen_rtvec (1, ecx),
17862 rtvec vec = rtvec_alloc (2);
17863 rtx load = gen_rtx_PARALLEL (VOIDmode, vec);
17864 rtx upper = gen_reg_rtx (DImode);
17865 rtx di = gen_rtx_UNSPEC_VOLATILE (DImode,
17866 gen_rtvec (1, const0_rtx),
17868 RTVEC_ELT (vec, 0) = gen_rtx_SET (VOIDmode, reg, si);
17869 RTVEC_ELT (vec, 1) = gen_rtx_SET (VOIDmode, upper, di);
17871 upper = expand_simple_binop (DImode, ASHIFT, upper, GEN_INT (32),
17872 NULL, 1, OPTAB_DIRECT);
17873 reg = expand_simple_binop (DImode, IOR, reg, upper, reg, 1,
17877 emit_insn (gen_rtx_SET (VOIDmode, reg, si));
17878 emit_insn (gen_rtx_SET (VOIDmode, operands[0], reg));
17882 (define_insn "*rdpmc"
17883 [(set (match_operand:DI 0 "register_operand" "=A")
17884 (unspec_volatile:DI [(match_operand:SI 1 "register_operand" "c")]
17888 [(set_attr "type" "other")
17889 (set_attr "length" "2")])
17891 (define_insn "*rdpmc_rex64"
17892 [(set (match_operand:DI 0 "register_operand" "=a")
17893 (unspec_volatile:DI [(match_operand:SI 2 "register_operand" "c")]
17895 (set (match_operand:DI 1 "register_operand" "=d")
17896 (unspec_volatile:DI [(const_int 0)] UNSPECV_RDPMC))]
17899 [(set_attr "type" "other")
17900 (set_attr "length" "2")])
17902 (define_expand "rdtsc"
17903 [(set (match_operand:DI 0 "register_operand" "")
17904 (unspec_volatile:DI [(const_int 0)] UNSPECV_RDTSC))]
17909 rtvec vec = rtvec_alloc (2);
17910 rtx load = gen_rtx_PARALLEL (VOIDmode, vec);
17911 rtx upper = gen_reg_rtx (DImode);
17912 rtx lower = gen_reg_rtx (DImode);
17913 rtx src = gen_rtx_UNSPEC_VOLATILE (DImode,
17914 gen_rtvec (1, const0_rtx),
17916 RTVEC_ELT (vec, 0) = gen_rtx_SET (VOIDmode, lower, src);
17917 RTVEC_ELT (vec, 1) = gen_rtx_SET (VOIDmode, upper, src);
17919 upper = expand_simple_binop (DImode, ASHIFT, upper, GEN_INT (32),
17920 NULL, 1, OPTAB_DIRECT);
17921 lower = expand_simple_binop (DImode, IOR, lower, upper, lower, 1,
17923 emit_insn (gen_rtx_SET (VOIDmode, operands[0], lower));
17928 (define_insn "*rdtsc"
17929 [(set (match_operand:DI 0 "register_operand" "=A")
17930 (unspec_volatile:DI [(const_int 0)] UNSPECV_RDTSC))]
17933 [(set_attr "type" "other")
17934 (set_attr "length" "2")])
17936 (define_insn "*rdtsc_rex64"
17937 [(set (match_operand:DI 0 "register_operand" "=a")
17938 (unspec_volatile:DI [(const_int 0)] UNSPECV_RDTSC))
17939 (set (match_operand:DI 1 "register_operand" "=d")
17940 (unspec_volatile:DI [(const_int 0)] UNSPECV_RDTSC))]
17943 [(set_attr "type" "other")
17944 (set_attr "length" "2")])
17946 (define_expand "rdtscp"
17947 [(match_operand:DI 0 "register_operand" "")
17948 (match_operand:SI 1 "memory_operand" "")]
17951 rtx di = gen_rtx_UNSPEC_VOLATILE (DImode,
17952 gen_rtvec (1, const0_rtx),
17954 rtx si = gen_rtx_UNSPEC_VOLATILE (SImode,
17955 gen_rtvec (1, const0_rtx),
17957 rtx reg = gen_reg_rtx (DImode);
17958 rtx tmp = gen_reg_rtx (SImode);
17962 rtvec vec = rtvec_alloc (3);
17963 rtx load = gen_rtx_PARALLEL (VOIDmode, vec);
17964 rtx upper = gen_reg_rtx (DImode);
17965 RTVEC_ELT (vec, 0) = gen_rtx_SET (VOIDmode, reg, di);
17966 RTVEC_ELT (vec, 1) = gen_rtx_SET (VOIDmode, upper, di);
17967 RTVEC_ELT (vec, 2) = gen_rtx_SET (VOIDmode, tmp, si);
17969 upper = expand_simple_binop (DImode, ASHIFT, upper, GEN_INT (32),
17970 NULL, 1, OPTAB_DIRECT);
17971 reg = expand_simple_binop (DImode, IOR, reg, upper, reg, 1,
17976 rtvec vec = rtvec_alloc (2);
17977 rtx load = gen_rtx_PARALLEL (VOIDmode, vec);
17978 RTVEC_ELT (vec, 0) = gen_rtx_SET (VOIDmode, reg, di);
17979 RTVEC_ELT (vec, 1) = gen_rtx_SET (VOIDmode, tmp, si);
17982 emit_insn (gen_rtx_SET (VOIDmode, operands[0], reg));
17983 emit_insn (gen_rtx_SET (VOIDmode, operands[1], tmp));
17987 (define_insn "*rdtscp"
17988 [(set (match_operand:DI 0 "register_operand" "=A")
17989 (unspec_volatile:DI [(const_int 0)] UNSPECV_RDTSCP))
17990 (set (match_operand:SI 1 "register_operand" "=c")
17991 (unspec_volatile:SI [(const_int 0)] UNSPECV_RDTSCP))]
17994 [(set_attr "type" "other")
17995 (set_attr "length" "3")])
17997 (define_insn "*rdtscp_rex64"
17998 [(set (match_operand:DI 0 "register_operand" "=a")
17999 (unspec_volatile:DI [(const_int 0)] UNSPECV_RDTSCP))
18000 (set (match_operand:DI 1 "register_operand" "=d")
18001 (unspec_volatile:DI [(const_int 0)] UNSPECV_RDTSCP))
18002 (set (match_operand:SI 2 "register_operand" "=c")
18003 (unspec_volatile:SI [(const_int 0)] UNSPECV_RDTSCP))]
18006 [(set_attr "type" "other")
18007 (set_attr "length" "3")])
18009 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
18011 ;; LWP instructions
18013 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
18015 (define_expand "lwp_llwpcb"
18016 [(unspec_volatile [(match_operand 0 "register_operand" "r")]
18017 UNSPECV_LLWP_INTRINSIC)]
18020 (define_insn "*lwp_llwpcb<mode>1"
18021 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
18022 UNSPECV_LLWP_INTRINSIC)]
18025 [(set_attr "type" "lwp")
18026 (set_attr "mode" "<MODE>")
18027 (set_attr "length" "5")])
18029 (define_expand "lwp_slwpcb"
18030 [(set (match_operand 0 "register_operand" "=r")
18031 (unspec_volatile [(const_int 0)] UNSPECV_SLWP_INTRINSIC))]
18036 insn = (TARGET_64BIT
18038 : gen_lwp_slwpcbsi);
18040 emit_insn (insn (operands[0]));
18044 (define_insn "lwp_slwpcb<mode>"
18045 [(set (match_operand:P 0 "register_operand" "=r")
18046 (unspec_volatile:P [(const_int 0)] UNSPECV_SLWP_INTRINSIC))]
18049 [(set_attr "type" "lwp")
18050 (set_attr "mode" "<MODE>")
18051 (set_attr "length" "5")])
18053 (define_expand "lwp_lwpval<mode>3"
18054 [(unspec_volatile [(match_operand:SWI48 1 "register_operand" "r")
18055 (match_operand:SI 2 "nonimmediate_operand" "rm")
18056 (match_operand:SI 3 "const_int_operand" "i")]
18057 UNSPECV_LWPVAL_INTRINSIC)]
18059 ;; Avoid unused variable warning.
18060 "(void) operands[0];")
18062 (define_insn "*lwp_lwpval<mode>3_1"
18063 [(unspec_volatile [(match_operand:SWI48 0 "register_operand" "r")
18064 (match_operand:SI 1 "nonimmediate_operand" "rm")
18065 (match_operand:SI 2 "const_int_operand" "i")]
18066 UNSPECV_LWPVAL_INTRINSIC)]
18068 "lwpval\t{%2, %1, %0|%0, %1, %2}"
18069 [(set_attr "type" "lwp")
18070 (set_attr "mode" "<MODE>")
18071 (set (attr "length")
18072 (symbol_ref "ix86_attr_length_address_default (insn) + 9"))])
18074 (define_expand "lwp_lwpins<mode>3"
18075 [(set (reg:CCC FLAGS_REG)
18076 (unspec_volatile:CCC [(match_operand:SWI48 1 "register_operand" "r")
18077 (match_operand:SI 2 "nonimmediate_operand" "rm")
18078 (match_operand:SI 3 "const_int_operand" "i")]
18079 UNSPECV_LWPINS_INTRINSIC))
18080 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
18081 (eq:QI (reg:CCC FLAGS_REG) (const_int 0)))]
18084 (define_insn "*lwp_lwpins<mode>3_1"
18085 [(set (reg:CCC FLAGS_REG)
18086 (unspec_volatile:CCC [(match_operand:SWI48 0 "register_operand" "r")
18087 (match_operand:SI 1 "nonimmediate_operand" "rm")
18088 (match_operand:SI 2 "const_int_operand" "i")]
18089 UNSPECV_LWPINS_INTRINSIC))]
18091 "lwpins\t{%2, %1, %0|%0, %1, %2}"
18092 [(set_attr "type" "lwp")
18093 (set_attr "mode" "<MODE>")
18094 (set (attr "length")
18095 (symbol_ref "ix86_attr_length_address_default (insn) + 9"))])
18097 (define_insn "rdfsbase<mode>"
18098 [(set (match_operand:SWI48 0 "register_operand" "=r")
18099 (unspec_volatile:SWI48 [(const_int 0)] UNSPECV_RDFSBASE))]
18100 "TARGET_64BIT && TARGET_FSGSBASE"
18102 [(set_attr "type" "other")
18103 (set_attr "prefix_extra" "2")])
18105 (define_insn "rdgsbase<mode>"
18106 [(set (match_operand:SWI48 0 "register_operand" "=r")
18107 (unspec_volatile:SWI48 [(const_int 0)] UNSPECV_RDGSBASE))]
18108 "TARGET_64BIT && TARGET_FSGSBASE"
18110 [(set_attr "type" "other")
18111 (set_attr "prefix_extra" "2")])
18113 (define_insn "wrfsbase<mode>"
18114 [(unspec_volatile [(match_operand:SWI48 0 "register_operand" "r")]
18116 "TARGET_64BIT && TARGET_FSGSBASE"
18118 [(set_attr "type" "other")
18119 (set_attr "prefix_extra" "2")])
18121 (define_insn "wrgsbase<mode>"
18122 [(unspec_volatile [(match_operand:SWI48 0 "register_operand" "r")]
18124 "TARGET_64BIT && TARGET_FSGSBASE"
18126 [(set_attr "type" "other")
18127 (set_attr "prefix_extra" "2")])
18129 (define_insn "rdrand<mode>_1"
18130 [(set (match_operand:SWI248 0 "register_operand" "=r")
18131 (unspec_volatile:SWI248 [(const_int 0)] UNSPECV_RDRAND))
18132 (set (reg:CCC FLAGS_REG)
18133 (unspec_volatile:CCC [(const_int 0)] UNSPECV_RDRAND))]
18136 [(set_attr "type" "other")
18137 (set_attr "prefix_extra" "1")])
18139 (define_expand "pause"
18140 [(set (match_dup 0)
18141 (unspec:BLK [(match_dup 0)] UNSPEC_PAUSE))]
18144 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
18145 MEM_VOLATILE_P (operands[0]) = 1;
18148 ;; Use "rep; nop", instead of "pause", to support older assemblers.
18149 ;; They have the same encoding.
18150 (define_insn "*pause"
18151 [(set (match_operand:BLK 0 "" "")
18152 (unspec:BLK [(match_dup 0)] UNSPEC_PAUSE))]
18155 [(set_attr "length" "2")
18156 (set_attr "memory" "unknown")])
18160 (include "sync.md")